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Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +01001/*
2 * Copyright (C) 2009
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
Stefano Babicd8e0ca82011-08-21 10:45:44 +02005 * Copyright (C) 2011
6 * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +01009 */
10#include <common.h>
Simon Glass441d0cf2014-10-01 19:57:26 -060011#include <errno.h>
12#include <dm.h>
13#include <malloc.h>
Stefano Babicc4ea1422010-07-06 17:05:06 +020014#include <asm/arch/imx-regs.h>
Stefano Babicd8e0ca82011-08-21 10:45:44 +020015#include <asm/gpio.h>
Stefano Babicc4ea1422010-07-06 17:05:06 +020016#include <asm/io.h>
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010017
Stefano Babicd8e0ca82011-08-21 10:45:44 +020018enum mxc_gpio_direction {
19 MXC_GPIO_DIRECTION_IN,
20 MXC_GPIO_DIRECTION_OUT,
21};
22
Simon Glass441d0cf2014-10-01 19:57:26 -060023#define GPIO_PER_BANK 32
24
25struct mxc_gpio_plat {
Peng Fan637a7692015-02-10 14:46:33 +080026 int bank_index;
Simon Glass441d0cf2014-10-01 19:57:26 -060027 struct gpio_regs *regs;
28};
29
30struct mxc_bank_info {
Simon Glass441d0cf2014-10-01 19:57:26 -060031 struct gpio_regs *regs;
32};
33
34#ifndef CONFIG_DM_GPIO
Vikram Narayanan8d28c212012-04-10 04:26:08 +000035#define GPIO_TO_PORT(n) (n / 32)
Stefano Babicd8e0ca82011-08-21 10:45:44 +020036
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010037/* GPIO port description */
38static unsigned long gpio_ports[] = {
Stefano Babicc4ea1422010-07-06 17:05:06 +020039 [0] = GPIO1_BASE_ADDR,
40 [1] = GPIO2_BASE_ADDR,
41 [2] = GPIO3_BASE_ADDR,
treme71c39d2012-08-25 05:30:33 +000042#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
Troy Kisky5ea6d7c2012-10-23 10:57:47 +000043 defined(CONFIG_MX53) || defined(CONFIG_MX6)
Stefano Babicc4ea1422010-07-06 17:05:06 +020044 [3] = GPIO4_BASE_ADDR,
45#endif
Troy Kisky5ea6d7c2012-10-23 10:57:47 +000046#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
Liu Hui-R6434301643ec2011-01-03 22:27:38 +000047 [4] = GPIO5_BASE_ADDR,
Peng Fanf2753b02015-07-20 19:28:31 +080048#ifndef CONFIG_MX6UL
Liu Hui-R6434301643ec2011-01-03 22:27:38 +000049 [5] = GPIO6_BASE_ADDR,
treme71c39d2012-08-25 05:30:33 +000050#endif
Peng Fanf2753b02015-07-20 19:28:31 +080051#endif
Troy Kisky5ea6d7c2012-10-23 10:57:47 +000052#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
Peng Fanf2753b02015-07-20 19:28:31 +080053#ifndef CONFIG_MX6UL
Liu Hui-R6434301643ec2011-01-03 22:27:38 +000054 [6] = GPIO7_BASE_ADDR,
55#endif
Peng Fanf2753b02015-07-20 19:28:31 +080056#endif
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010057};
58
Stefano Babicd8e0ca82011-08-21 10:45:44 +020059static int mxc_gpio_direction(unsigned int gpio,
60 enum mxc_gpio_direction direction)
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010061{
Vikram Narayananbe282552012-04-10 04:26:20 +000062 unsigned int port = GPIO_TO_PORT(gpio);
Stefano Babicc4ea1422010-07-06 17:05:06 +020063 struct gpio_regs *regs;
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010064 u32 l;
65
66 if (port >= ARRAY_SIZE(gpio_ports))
Joe Hershberger365d6072011-11-11 15:55:36 -060067 return -1;
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010068
69 gpio &= 0x1f;
70
Stefano Babicc4ea1422010-07-06 17:05:06 +020071 regs = (struct gpio_regs *)gpio_ports[port];
72
73 l = readl(&regs->gpio_dir);
74
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010075 switch (direction) {
Stefano Babicc4ea1422010-07-06 17:05:06 +020076 case MXC_GPIO_DIRECTION_OUT:
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010077 l |= 1 << gpio;
78 break;
Stefano Babicc4ea1422010-07-06 17:05:06 +020079 case MXC_GPIO_DIRECTION_IN:
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010080 l &= ~(1 << gpio);
81 }
Stefano Babicc4ea1422010-07-06 17:05:06 +020082 writel(l, &regs->gpio_dir);
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010083
84 return 0;
85}
86
Joe Hershberger365d6072011-11-11 15:55:36 -060087int gpio_set_value(unsigned gpio, int value)
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010088{
Vikram Narayananbe282552012-04-10 04:26:20 +000089 unsigned int port = GPIO_TO_PORT(gpio);
Stefano Babicc4ea1422010-07-06 17:05:06 +020090 struct gpio_regs *regs;
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010091 u32 l;
92
93 if (port >= ARRAY_SIZE(gpio_ports))
Joe Hershberger365d6072011-11-11 15:55:36 -060094 return -1;
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +010095
96 gpio &= 0x1f;
97
Stefano Babicc4ea1422010-07-06 17:05:06 +020098 regs = (struct gpio_regs *)gpio_ports[port];
99
100 l = readl(&regs->gpio_dr);
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +0100101 if (value)
102 l |= 1 << gpio;
103 else
104 l &= ~(1 << gpio);
Stefano Babicc4ea1422010-07-06 17:05:06 +0200105 writel(l, &regs->gpio_dr);
Joe Hershberger365d6072011-11-11 15:55:36 -0600106
107 return 0;
Guennadi Liakhovetskib30de3c2009-02-07 01:18:07 +0100108}
Stefano Babic7d27cd02010-04-13 12:07:00 +0200109
Joe Hershberger365d6072011-11-11 15:55:36 -0600110int gpio_get_value(unsigned gpio)
Stefano Babic7d27cd02010-04-13 12:07:00 +0200111{
Vikram Narayananbe282552012-04-10 04:26:20 +0000112 unsigned int port = GPIO_TO_PORT(gpio);
Stefano Babicc4ea1422010-07-06 17:05:06 +0200113 struct gpio_regs *regs;
Joe Hershberger365d6072011-11-11 15:55:36 -0600114 u32 val;
Stefano Babic7d27cd02010-04-13 12:07:00 +0200115
116 if (port >= ARRAY_SIZE(gpio_ports))
Joe Hershberger365d6072011-11-11 15:55:36 -0600117 return -1;
Stefano Babic7d27cd02010-04-13 12:07:00 +0200118
119 gpio &= 0x1f;
120
Stefano Babicc4ea1422010-07-06 17:05:06 +0200121 regs = (struct gpio_regs *)gpio_ports[port];
122
Benoît Thébaudeau5dafa452012-08-20 10:55:41 +0000123 val = (readl(&regs->gpio_psr) >> gpio) & 0x01;
Stefano Babic7d27cd02010-04-13 12:07:00 +0200124
Joe Hershberger365d6072011-11-11 15:55:36 -0600125 return val;
Stefano Babic7d27cd02010-04-13 12:07:00 +0200126}
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200127
Joe Hershberger365d6072011-11-11 15:55:36 -0600128int gpio_request(unsigned gpio, const char *label)
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200129{
Vikram Narayananbe282552012-04-10 04:26:20 +0000130 unsigned int port = GPIO_TO_PORT(gpio);
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200131 if (port >= ARRAY_SIZE(gpio_ports))
Joe Hershberger365d6072011-11-11 15:55:36 -0600132 return -1;
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200133 return 0;
134}
135
Joe Hershberger365d6072011-11-11 15:55:36 -0600136int gpio_free(unsigned gpio)
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200137{
Joe Hershberger365d6072011-11-11 15:55:36 -0600138 return 0;
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200139}
140
Joe Hershberger365d6072011-11-11 15:55:36 -0600141int gpio_direction_input(unsigned gpio)
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200142{
Joe Hershberger365d6072011-11-11 15:55:36 -0600143 return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200144}
145
Joe Hershberger365d6072011-11-11 15:55:36 -0600146int gpio_direction_output(unsigned gpio, int value)
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200147{
Dirk Behme04c79cb2013-07-15 15:58:27 +0200148 int ret = gpio_set_value(gpio, value);
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200149
150 if (ret < 0)
151 return ret;
152
Dirk Behme04c79cb2013-07-15 15:58:27 +0200153 return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
Stefano Babicd8e0ca82011-08-21 10:45:44 +0200154}
Simon Glass441d0cf2014-10-01 19:57:26 -0600155#endif
156
157#ifdef CONFIG_DM_GPIO
Peng Fan99c0ae12015-02-10 14:46:34 +0800158#include <fdtdec.h>
159DECLARE_GLOBAL_DATA_PTR;
160
Simon Glass441d0cf2014-10-01 19:57:26 -0600161static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
162{
163 u32 val;
164
165 val = readl(&regs->gpio_dir);
166
167 return val & (1 << offset) ? 1 : 0;
168}
169
170static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
171 enum mxc_gpio_direction direction)
172{
173 u32 l;
174
175 l = readl(&regs->gpio_dir);
176
177 switch (direction) {
178 case MXC_GPIO_DIRECTION_OUT:
179 l |= 1 << offset;
180 break;
181 case MXC_GPIO_DIRECTION_IN:
182 l &= ~(1 << offset);
183 }
184 writel(l, &regs->gpio_dir);
185}
186
187static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
188 int value)
189{
190 u32 l;
191
192 l = readl(&regs->gpio_dr);
193 if (value)
194 l |= 1 << offset;
195 else
196 l &= ~(1 << offset);
197 writel(l, &regs->gpio_dr);
198}
199
200static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
201{
202 return (readl(&regs->gpio_psr) >> offset) & 0x01;
203}
204
Simon Glass441d0cf2014-10-01 19:57:26 -0600205/* set GPIO pin 'gpio' as an input */
206static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
207{
208 struct mxc_bank_info *bank = dev_get_priv(dev);
Simon Glass441d0cf2014-10-01 19:57:26 -0600209
210 /* Configure GPIO direction as input. */
211 mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
212
213 return 0;
214}
215
216/* set GPIO pin 'gpio' as an output, with polarity 'value' */
217static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
218 int value)
219{
220 struct mxc_bank_info *bank = dev_get_priv(dev);
Simon Glass441d0cf2014-10-01 19:57:26 -0600221
222 /* Configure GPIO output value. */
223 mxc_gpio_bank_set_value(bank->regs, offset, value);
224
225 /* Configure GPIO direction as output. */
226 mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
227
228 return 0;
229}
230
231/* read GPIO IN value of pin 'gpio' */
232static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
233{
234 struct mxc_bank_info *bank = dev_get_priv(dev);
Simon Glass441d0cf2014-10-01 19:57:26 -0600235
236 return mxc_gpio_bank_get_value(bank->regs, offset);
237}
238
239/* write GPIO OUT value to pin 'gpio' */
240static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
241 int value)
242{
243 struct mxc_bank_info *bank = dev_get_priv(dev);
Simon Glass441d0cf2014-10-01 19:57:26 -0600244
245 mxc_gpio_bank_set_value(bank->regs, offset, value);
246
247 return 0;
248}
249
Simon Glass441d0cf2014-10-01 19:57:26 -0600250static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
251{
252 struct mxc_bank_info *bank = dev_get_priv(dev);
253
Simon Glass441d0cf2014-10-01 19:57:26 -0600254 /* GPIOF_FUNC is not implemented yet */
255 if (mxc_gpio_is_output(bank->regs, offset))
256 return GPIOF_OUTPUT;
257 else
258 return GPIOF_INPUT;
259}
260
261static const struct dm_gpio_ops gpio_mxc_ops = {
Simon Glass441d0cf2014-10-01 19:57:26 -0600262 .direction_input = mxc_gpio_direction_input,
263 .direction_output = mxc_gpio_direction_output,
264 .get_value = mxc_gpio_get_value,
265 .set_value = mxc_gpio_set_value,
266 .get_function = mxc_gpio_get_function,
Simon Glass441d0cf2014-10-01 19:57:26 -0600267};
268
Simon Glass441d0cf2014-10-01 19:57:26 -0600269static int mxc_gpio_probe(struct udevice *dev)
270{
271 struct mxc_bank_info *bank = dev_get_priv(dev);
272 struct mxc_gpio_plat *plat = dev_get_platdata(dev);
Simon Glasse564f052015-03-05 12:25:20 -0700273 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass441d0cf2014-10-01 19:57:26 -0600274 int banknum;
275 char name[18], *str;
276
Peng Fan637a7692015-02-10 14:46:33 +0800277 banknum = plat->bank_index;
Simon Glass441d0cf2014-10-01 19:57:26 -0600278 sprintf(name, "GPIO%d_", banknum + 1);
279 str = strdup(name);
280 if (!str)
281 return -ENOMEM;
282 uc_priv->bank_name = str;
283 uc_priv->gpio_count = GPIO_PER_BANK;
284 bank->regs = plat->regs;
285
286 return 0;
287}
288
Peng Fan99c0ae12015-02-10 14:46:34 +0800289static int mxc_gpio_bind(struct udevice *dev)
290{
291 struct mxc_gpio_plat *plat = dev->platdata;
292 fdt_addr_t addr;
293
294 /*
295 * If platdata already exsits, directly return.
296 * Actually only when DT is not supported, platdata
297 * is statically initialized in U_BOOT_DEVICES.Here
298 * will return.
299 */
300 if (plat)
301 return 0;
302
303 addr = dev_get_addr(dev);
304 if (addr == FDT_ADDR_T_NONE)
305 return -ENODEV;
306
307 /*
308 * TODO:
309 * When every board is converted to driver model and DT is supported,
310 * this can be done by auto-alloc feature, but not using calloc
311 * to alloc memory for platdata.
312 */
313 plat = calloc(1, sizeof(*plat));
314 if (!plat)
315 return -ENOMEM;
316
317 plat->regs = (struct gpio_regs *)addr;
318 plat->bank_index = dev->req_seq;
319 dev->platdata = plat;
320
321 return 0;
322}
323
324static const struct udevice_id mxc_gpio_ids[] = {
325 { .compatible = "fsl,imx35-gpio" },
326 { }
327};
328
Simon Glass441d0cf2014-10-01 19:57:26 -0600329U_BOOT_DRIVER(gpio_mxc) = {
330 .name = "gpio_mxc",
331 .id = UCLASS_GPIO,
332 .ops = &gpio_mxc_ops,
333 .probe = mxc_gpio_probe,
334 .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
Peng Fan99c0ae12015-02-10 14:46:34 +0800335 .of_match = mxc_gpio_ids,
336 .bind = mxc_gpio_bind,
337};
338
339#ifndef CONFIG_OF_CONTROL
340static const struct mxc_gpio_plat mxc_plat[] = {
341 { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
342 { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
343 { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
344#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
345 defined(CONFIG_MX53) || defined(CONFIG_MX6)
346 { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
347#endif
348#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
349 { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
350 { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
351#endif
352#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
353 { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
354#endif
Simon Glass441d0cf2014-10-01 19:57:26 -0600355};
356
357U_BOOT_DEVICES(mxc_gpios) = {
358 { "gpio_mxc", &mxc_plat[0] },
359 { "gpio_mxc", &mxc_plat[1] },
360 { "gpio_mxc", &mxc_plat[2] },
361#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
362 defined(CONFIG_MX53) || defined(CONFIG_MX6)
363 { "gpio_mxc", &mxc_plat[3] },
364#endif
365#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
366 { "gpio_mxc", &mxc_plat[4] },
367 { "gpio_mxc", &mxc_plat[5] },
368#endif
369#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
370 { "gpio_mxc", &mxc_plat[6] },
371#endif
372};
373#endif
Peng Fan99c0ae12015-02-10 14:46:34 +0800374#endif