blob: 479bebbe427dca063195ad007eb8b54f4ec907df [file] [log] [blame]
Stefan Roesef0ff4692006-08-15 14:15:51 +02001/*
2 * (C) Copyright 2006
3 * Heiko Schocher, hs@denx.de
4 * Based on ACE1XK.c
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
24 */
25
26#include <common.h> /* core U-Boot definitions */
27#include <altera.h>
28#include <ACEX1K.h> /* ACEX device family */
29
Stefan Roesef0ff4692006-08-15 14:15:51 +020030/* Define FPGA_DEBUG to get debug printf's */
31#ifdef FPGA_DEBUG
32#define PRINTF(fmt,args...) printf (fmt ,##args)
33#else
34#define PRINTF(fmt,args...)
35#endif
36
37/* Note: The assumption is that we cannot possibly run fast enough to
38 * overrun the device (the Slave Parallel mode can free run at 50MHz).
39 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
40 * the board config file to slow things down.
41 */
42#ifndef CONFIG_FPGA_DELAY
43#define CONFIG_FPGA_DELAY()
44#endif
45
46#ifndef CFG_FPGA_WAIT
47#define CFG_FPGA_WAIT CFG_HZ/10 /* 100 ms */
48#endif
49
50static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize );
51static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
52/* static int CYC2_ps_info( Altera_desc *desc ); */
53static int CYC2_ps_reloc( Altera_desc *desc, ulong reloc_offset );
54
55/* ------------------------------------------------------------------------- */
56/* CYCLON2 Generic Implementation */
57int CYC2_load (Altera_desc * desc, void *buf, size_t bsize)
58{
59 int ret_val = FPGA_FAIL;
60
61 switch (desc->iface) {
62 case passive_serial:
63 PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
64 ret_val = CYC2_ps_load (desc, buf, bsize);
65 break;
66
67 /* Add new interface types here */
68
69 default:
70 printf ("%s: Unsupported interface type, %d\n",
71 __FUNCTION__, desc->iface);
72 }
73
74 return ret_val;
75}
76
77int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize)
78{
79 int ret_val = FPGA_FAIL;
80
81 switch (desc->iface) {
82 case passive_serial:
83 PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
84 ret_val = CYC2_ps_dump (desc, buf, bsize);
85 break;
86
87 /* Add new interface types here */
88
89 default:
90 printf ("%s: Unsupported interface type, %d\n",
91 __FUNCTION__, desc->iface);
92 }
93
94 return ret_val;
95}
96
97int CYC2_info( Altera_desc *desc )
98{
99 return FPGA_SUCCESS;
100}
101
102int CYC2_reloc (Altera_desc * desc, ulong reloc_offset)
103{
104 int ret_val = FPGA_FAIL; /* assume a failure */
105
106 if (desc->family != Altera_CYC2) {
107 printf ("%s: Unsupported family type, %d\n",
108 __FUNCTION__, desc->family);
109 return FPGA_FAIL;
110 } else
111 switch (desc->iface) {
112 case passive_serial:
113 ret_val = CYC2_ps_reloc (desc, reloc_offset);
114 break;
115
116 /* Add new interface types here */
117
118 default:
119 printf ("%s: Unsupported interface type, %d\n",
120 __FUNCTION__, desc->iface);
121 }
122
123 return ret_val;
124}
125
126/* ------------------------------------------------------------------------- */
127/* CYCLON2 Passive Serial Generic Implementation */
128static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize)
129{
130 int ret_val = FPGA_FAIL; /* assume the worst */
131 Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
132 int ret = 0;
133
134 PRINTF ("%s: start with interface functions @ 0x%p\n",
135 __FUNCTION__, fn);
136
137 if (fn) {
138 int cookie = desc->cookie; /* make a local copy */
139 unsigned long ts; /* timestamp */
140
141 PRINTF ("%s: Function Table:\n"
142 "ptr:\t0x%p\n"
143 "struct: 0x%p\n"
144 "config:\t0x%p\n"
145 "status:\t0x%p\n"
146 "write:\t0x%p\n"
147 "done:\t0x%p\n\n",
148 __FUNCTION__, &fn, fn, fn->config, fn->status,
149 fn->write, fn->done);
150#ifdef CFG_FPGA_PROG_FEEDBACK
151 printf ("Loading FPGA Device %d...", cookie);
152#endif
153
154 /*
155 * Run the pre configuration function if there is one.
156 */
157 if (*fn->pre) {
158 (*fn->pre) (cookie);
159 }
160
161 /* Establish the initial state */
162 (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
163
164 udelay(2); /* T_cfg > 2us */
165
166 /* Wait for nSTATUS to be asserted */
167 ts = get_timer (0); /* get current time */
168 do {
169 CONFIG_FPGA_DELAY ();
170 if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
171 puts ("** Timeout waiting for STATUS to go high.\n");
172 (*fn->abort) (cookie);
173 return FPGA_FAIL;
174 }
175 } while (!(*fn->status) (cookie));
176
177 /* Get ready for the burn */
178 CONFIG_FPGA_DELAY ();
179
180 ret = (*fn->write) (buf, bsize, TRUE, cookie);
181 if (ret) {
182 puts ("** Write failed.\n");
183 (*fn->abort) (cookie);
184 return FPGA_FAIL;
185 }
186#ifdef CFG_FPGA_PROG_FEEDBACK
187 puts(" OK? ...");
188#endif
189
190 CONFIG_FPGA_DELAY ();
191
192#ifdef CFG_FPGA_PROG_FEEDBACK
193 putc (' '); /* terminate the dotted line */
194#endif
195
196 /*
197 * Checking FPGA's CONF_DONE signal - correctly booted ?
198 */
199
200 if ( ! (*fn->done) (cookie) ) {
201 puts ("** Booting failed! CONF_DONE is still deasserted.\n");
202 (*fn->abort) (cookie);
203 return (FPGA_FAIL);
204 }
205#ifdef CFG_FPGA_PROG_FEEDBACK
206 puts(" OK\n");
207#endif
208
209 ret_val = FPGA_SUCCESS;
210
211#ifdef CFG_FPGA_PROG_FEEDBACK
212 if (ret_val == FPGA_SUCCESS) {
213 puts ("Done.\n");
214 }
215 else {
216 puts ("Fail.\n");
217 }
218#endif
219 (*fn->post) (cookie);
220
221 } else {
222 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
223 }
224
225 return ret_val;
226}
227
228static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
229{
230 /* Readback is only available through the Slave Parallel and */
231 /* boundary-scan interfaces. */
232 printf ("%s: Passive Serial Dumping is unavailable\n",
233 __FUNCTION__);
234 return FPGA_FAIL;
235}
236
237static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset)
238{
239 int ret_val = FPGA_FAIL; /* assume the worst */
240 Altera_CYC2_Passive_Serial_fns *fn_r, *fn =
241 (Altera_CYC2_Passive_Serial_fns *) (desc->iface_fns);
242
243 if (fn) {
244 ulong addr;
245
246 /* Get the relocated table address */
247 addr = (ulong) fn + reloc_offset;
248 fn_r = (Altera_CYC2_Passive_Serial_fns *) addr;
249
250 if (!fn_r->relocated) {
251
252 if (memcmp (fn_r, fn,
253 sizeof (Altera_CYC2_Passive_Serial_fns))
254 == 0) {
255 /* good copy of the table, fix the descriptor pointer */
256 desc->iface_fns = fn_r;
257 } else {
258 PRINTF ("%s: Invalid function table at 0x%p\n",
259 __FUNCTION__, fn_r);
260 return FPGA_FAIL;
261 }
262
263 PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
264 desc);
265
266 addr = (ulong) (fn->pre) + reloc_offset;
267 fn_r->pre = (Altera_pre_fn) addr;
268
269 addr = (ulong) (fn->config) + reloc_offset;
270 fn_r->config = (Altera_config_fn) addr;
271
272 addr = (ulong) (fn->status) + reloc_offset;
273 fn_r->status = (Altera_status_fn) addr;
274
275 addr = (ulong) (fn->done) + reloc_offset;
276 fn_r->done = (Altera_done_fn) addr;
277
278 addr = (ulong) (fn->write) + reloc_offset;
279 fn_r->write = (Altera_write_fn) addr;
280
281 addr = (ulong) (fn->abort) + reloc_offset;
282 fn_r->abort = (Altera_abort_fn) addr;
283
284 addr = (ulong) (fn->post) + reloc_offset;
285 fn_r->post = (Altera_post_fn) addr;
286
287 fn_r->relocated = TRUE;
288
289 } else {
290 /* this table has already been moved */
291 /* XXX - should check to see if the descriptor is correct */
292 desc->iface_fns = fn_r;
293 }
294
295 ret_val = FPGA_SUCCESS;
296 } else {
297 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
298 }
299
300 return ret_val;
301}