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Shengzhou Liuae6b03f2011-11-22 16:51:13 +08001/*
2 * Copyright 2011 Freescale Semiconductor
3 * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Shengzhou Liuae6b03f2011-11-22 16:51:13 +08006 *
7 * This file provides support for the QIXIS of some Freescale reference boards.
Shengzhou Liuae6b03f2011-11-22 16:51:13 +08008 */
9
10#include <common.h>
11#include <command.h>
12#include <asm/io.h>
Prabhakar Kushwaha2ae4e8d2012-12-23 19:24:47 +000013#include <linux/time.h>
Prabhakar Kushwaha960aa892013-01-23 17:59:37 +000014#include <i2c.h>
Shengzhou Liuae6b03f2011-11-22 16:51:13 +080015#include "qixis.h"
16
Prabhakar Kushwaha960aa892013-01-23 17:59:37 +000017#ifdef CONFIG_SYS_I2C_FPGA_ADDR
18u8 qixis_read_i2c(unsigned int reg)
19{
20 return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
21}
22
23void qixis_write_i2c(unsigned int reg, u8 value)
24{
25 u8 val = value;
26 i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
27}
28#endif
29
Shengzhou Liuae6b03f2011-11-22 16:51:13 +080030u8 qixis_read(unsigned int reg)
31{
32 void *p = (void *)QIXIS_BASE;
33
34 return in_8(p + reg);
35}
36
37void qixis_write(unsigned int reg, u8 value)
38{
39 void *p = (void *)QIXIS_BASE;
40
41 out_8(p + reg, value);
42}
43
Prabhakar Kushwaha2ae4e8d2012-12-23 19:24:47 +000044u16 qixis_read_minor(void)
45{
46 u16 minor;
47
48 /* this data is in little endian */
49 QIXIS_WRITE(tagdata, 5);
50 minor = QIXIS_READ(tagdata);
51 QIXIS_WRITE(tagdata, 6);
52 minor += QIXIS_READ(tagdata) << 8;
53
54 return minor;
55}
56
57char *qixis_read_time(char *result)
58{
59 time_t time = 0;
60 int i;
61
62 /* timestamp is in 32-bit big endian */
63 for (i = 8; i <= 11; i++) {
64 QIXIS_WRITE(tagdata, i);
65 time = (time << 8) + QIXIS_READ(tagdata);
66 }
67
68 return ctime_r(&time, result);
69}
70
71char *qixis_read_tag(char *buf)
72{
73 int i;
74 char tag, *ptr = buf;
75
76 for (i = 16; i <= 63; i++) {
77 QIXIS_WRITE(tagdata, i);
78 tag = QIXIS_READ(tagdata);
79 *(ptr++) = tag;
80 if (!tag)
81 break;
82 }
83 if (i > 63)
84 *ptr = '\0';
85
86 return buf;
87}
88
Shaveta Leekhac6cef922012-12-23 19:25:35 +000089/*
90 * return the string of binary of u8 in the format of
91 * 1010 10_0. The masked bit is filled as underscore.
92 */
93const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
94{
95 char *ptr;
96 int i;
97
98 ptr = buf;
99 for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
100 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
101 *(ptr++) = ' ';
102 for (i = 0x08; i > 0 ; i >>= 1, ptr++)
103 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
104
105 *ptr = '\0';
106
107 return buf;
108}
109
York Sunc63e1372013-06-25 11:37:48 -0700110#ifdef QIXIS_RST_FORCE_MEM
111void board_assert_mem_reset(void)
112{
113 u8 rst;
114
115 rst = QIXIS_READ(rst_frc[0]);
116 if (!(rst & QIXIS_RST_FORCE_MEM))
117 QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
118}
119
120void board_deassert_mem_reset(void)
121{
122 u8 rst;
123
124 rst = QIXIS_READ(rst_frc[0]);
125 if (rst & QIXIS_RST_FORCE_MEM)
126 QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
127}
128#endif
129
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800130void qixis_reset(void)
131{
Prabhakar Kushwaha9f26fd72012-09-17 17:30:31 +0000132 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800133}
134
135void qixis_bank_reset(void)
136{
Prabhakar Kushwaha9f26fd72012-09-17 17:30:31 +0000137 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
138 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800139}
140
Scott Wood548cf522015-03-20 19:28:29 -0700141static void __maybe_unused set_lbmap(int lbmap)
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800142{
143 u8 reg;
144
145 reg = QIXIS_READ(brdcfg[0]);
Scott Wood548cf522015-03-20 19:28:29 -0700146 reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800147 QIXIS_WRITE(brdcfg[0], reg);
148}
149
Scott Wood548cf522015-03-20 19:28:29 -0700150static void __maybe_unused set_rcw_src(int rcw_src)
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800151{
152 u8 reg;
153
Scott Wood548cf522015-03-20 19:28:29 -0700154 reg = QIXIS_READ(dutcfg[1]);
155 reg = (reg & ~1) | (rcw_src & 1);
156 QIXIS_WRITE(dutcfg[1], reg);
157 QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800158}
159
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800160static void qixis_dump_regs(void)
161{
162 int i;
163
164 printf("id = %02x\n", QIXIS_READ(id));
165 printf("arch = %02x\n", QIXIS_READ(arch));
166 printf("scver = %02x\n", QIXIS_READ(scver));
167 printf("model = %02x\n", QIXIS_READ(model));
168 printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
169 printf("aux = %02x\n", QIXIS_READ(aux));
170 for (i = 0; i < 16; i++)
171 printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
172 for (i = 0; i < 16; i++)
173 printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
174 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
175 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
176 printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
177 QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
178 printf("aux = %02x\n", QIXIS_READ(aux));
179 printf("watch = %02x\n", QIXIS_READ(watch));
180 printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
181 printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
182 printf("present = %02x\n", QIXIS_READ(present));
Shengzhou Liue4de13e2012-10-07 20:21:02 +0000183 printf("present2 = %02x\n", QIXIS_READ(present2));
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800184 printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
185 printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
186 printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
187 printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800188}
Shaveta Leekhac6cef922012-12-23 19:25:35 +0000189
190static void __qixis_dump_switch(void)
191{
192 puts("Reverse engineering switch is not implemented for this board\n");
193}
194
195void qixis_dump_switch(void)
196 __attribute__((weak, alias("__qixis_dump_switch")));
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800197
198int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
199{
200 int i;
201
202 if (argc <= 1) {
Scott Wood548cf522015-03-20 19:28:29 -0700203 set_lbmap(QIXIS_LBMAP_DFLTBANK);
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800204 qixis_reset();
205 } else if (strcmp(argv[1], "altbank") == 0) {
Scott Wood548cf522015-03-20 19:28:29 -0700206 set_lbmap(QIXIS_LBMAP_ALTBANK);
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800207 qixis_bank_reset();
Scott Wood548cf522015-03-20 19:28:29 -0700208 } else if (strcmp(argv[1], "nand") == 0) {
209#ifdef QIXIS_LBMAP_NAND
210 QIXIS_WRITE(rst_ctl, 0x30);
211 QIXIS_WRITE(rcfg_ctl, 0);
212 set_lbmap(QIXIS_LBMAP_NAND);
213 set_rcw_src(QIXIS_RCW_SRC_NAND);
214 QIXIS_WRITE(rcfg_ctl, 0x20);
215 QIXIS_WRITE(rcfg_ctl, 0x21);
216#else
217 printf("Not implemented\n");
218#endif
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800219 } else if (strcmp(argv[1], "watchdog") == 0) {
220 static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
221 "1min", "2min", "4min", "8min"};
222 u8 rcfg = QIXIS_READ(rcfg_ctl);
223
224 if (argv[2] == NULL) {
225 printf("qixis watchdog <watchdog_period>\n");
226 return 0;
227 }
228 for (i = 0; i < ARRAY_SIZE(period); i++) {
229 if (strcmp(argv[2], period[i]) == 0) {
230 /* disable watchdog */
Prabhakar Kushwaha9f26fd72012-09-17 17:30:31 +0000231 QIXIS_WRITE(rcfg_ctl,
232 rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800233 QIXIS_WRITE(watch, ((i<<2) - 1));
234 QIXIS_WRITE(rcfg_ctl, rcfg);
235 return 0;
236 }
237 }
Shaveta Leekhac6cef922012-12-23 19:25:35 +0000238 } else if (strcmp(argv[1], "dump") == 0) {
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800239 qixis_dump_regs();
240 return 0;
Shaveta Leekhac6cef922012-12-23 19:25:35 +0000241 } else if (strcmp(argv[1], "switch") == 0) {
242 qixis_dump_switch();
243 return 0;
244 } else {
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800245 printf("Invalid option: %s\n", argv[1]);
246 return 1;
247 }
248
249 return 0;
250}
251
252U_BOOT_CMD(
253 qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
254 "Reset the board using the FPGA sequencer",
255 "- hard reset to default bank\n"
256 "qixis_reset altbank - reset to alternate bank\n"
Scott Wood548cf522015-03-20 19:28:29 -0700257 "qixis_reset nand - reset to nand\n"
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800258 "qixis watchdog <watchdog_period> - set the watchdog period\n"
259 " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800260 "qixis_reset dump - display the QIXIS registers\n"
Shaveta Leekhac6cef922012-12-23 19:25:35 +0000261 "qixis_reset switch - display switch\n"
Shengzhou Liuae6b03f2011-11-22 16:51:13 +0800262 );