blob: d22ea74136d3a3657cff5f3388593654dacba88a [file] [log] [blame]
huang linbe1d5e02015-11-17 14:20:27 +08001/*
2 * (C) Copyright 2015 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#ifndef __CONFIG_RK3036_COMMON_H
7#define __CONFIG_RK3036_COMMON_H
8
9#include <asm/arch/hardware.h>
10
11#define CONFIG_SYS_NO_FLASH
12#define CONFIG_NR_DRAM_BANKS 1
13#define CONFIG_ENV_IS_NOWHERE
14#define CONFIG_ENV_SIZE 0x2000
15#define CONFIG_SYS_MAXARGS 16
16#define CONFIG_BAUDRATE 115200
17#define CONFIG_SYS_MALLOC_LEN (32 << 20)
18#define CONFIG_SYS_CBSIZE 1024
19#define CONFIG_SKIP_LOWLEVEL_INIT
20#define CONFIG_SYS_THUMB_BUILD
21#define CONFIG_DISPLAY_BOARDINFO
22
23#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
24#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
25#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
26
Simon Glass9b205192015-12-13 21:37:00 -070027#define CONFIG_SPL_SERIAL_SUPPORT
28
huang linbe1d5e02015-11-17 14:20:27 +080029#define CONFIG_SYS_NS16550
30#define CONFIG_SYS_NS16550_MEM32
31
huang linbe1d5e02015-11-17 14:20:27 +080032#define CONFIG_SYS_TEXT_BASE 0x60000000
33#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
34#define CONFIG_SYS_LOAD_ADDR 0x60800800
35#define CONFIG_SPL_STACK 0x10081fff
36#define CONFIG_SPL_TEXT_BASE 0x10081004
37
38#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10)
39#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
40
41#define CONFIG_ROCKCHIP_COMMON
42
43/* MMC/SD IP block */
44#define CONFIG_MMC
45#define CONFIG_GENERIC_MMC
46#define CONFIG_CMD_MMC
47#define CONFIG_SDHCI
48#define CONFIG_DWMMC
49#define CONFIG_BOUNCE_BUFFER
50
51#define CONFIG_DOS_PARTITION
52#define CONFIG_CMD_FAT
53#define CONFIG_FAT_WRITE
54#define CONFIG_CMD_EXT2
55#define CONFIG_CMD_EXT4
56#define CONFIG_CMD_FS_GENERIC
57#define CONFIG_PARTITION_UUIDS
58#define CONFIG_CMD_PART
59
60#define CONFIG_CMD_CACHE
61#define CONFIG_CMD_TIME
62
63#define CONFIG_SYS_SDRAM_BASE 0x60000000
64#define CONFIG_NR_DRAM_BANKS 1
65#define SDRAM_BANK_SIZE (512UL << 20UL)
66
67#define CONFIG_SPI_FLASH
68#define CONFIG_SPI
69#define CONFIG_CMD_SF
70#define CONFIG_CMD_SPI
71#define CONFIG_SPI_FLASH_GIGADEVICE
72#define CONFIG_SF_DEFAULT_SPEED 20000000
73
74#define CONFIG_CMD_I2C
75
76#ifndef CONFIG_SPL_BUILD
77#include <config_distro_defaults.h>
78
79#define ENV_MEM_LAYOUT_SETTINGS \
80 "scriptaddr=0x60000000\0" \
81 "pxefile_addr_r=0x60100000\0" \
82 "fdt_addr_r=0x61f00000\0" \
83 "kernel_addr_r=0x62000000\0" \
84 "ramdisk_addr_r=0x64000000\0"
85
86/* First try to boot from SD (index 0), then eMMC (index 1 */
87#define BOOT_TARGET_DEVICES(func) \
88 func(MMC, mmc, 0) \
89 func(MMC, mmc, 1)
90
91#include <config_distro_bootcmd.h>
92
93/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
94 * so limit the fdt reallocation to that */
95#define CONFIG_EXTRA_ENV_SETTINGS \
96 "fdt_high=0x7fffffff\0" \
97 ENV_MEM_LAYOUT_SETTINGS \
98 BOOTENV
99#endif
100
101#endif