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wdenk5da627a2003-10-09 20:09:04 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk5da627a2003-10-09 20:09:04 +00006 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
wdenk5da627a2003-10-09 20:09:04 +000015#define CONFIG_DBAU1X00 1
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090016#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
wdenk5da627a2003-10-09 20:09:04 +000017
Daniel Schwierzeck74368692014-11-15 23:30:01 +010018#define CONFIG_DISPLAY_BOARDINFO
19
wdenka2663ea2003-12-07 18:32:37 +000020#ifdef CONFIG_DBAU1000
wdenk5da627a2003-10-09 20:09:04 +000021/* Also known as Merlot */
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090022#define CONFIG_SOC_AU1000 1
wdenka2663ea2003-12-07 18:32:37 +000023#else
24#ifdef CONFIG_DBAU1100
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090025#define CONFIG_SOC_AU1100 1
wdenka2663ea2003-12-07 18:32:37 +000026#else
27#ifdef CONFIG_DBAU1500
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090028#define CONFIG_SOC_AU1500 1
wdenkd4ca31c2004-01-02 14:00:00 +000029#else
wdenkff36fd82005-01-09 22:28:56 +000030#ifdef CONFIG_DBAU1550
31/* Cabernet */
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090032#define CONFIG_SOC_AU1550 1
wdenkff36fd82005-01-09 22:28:56 +000033#else
wdenka2663ea2003-12-07 18:32:37 +000034#error "No valid board set"
35#endif
36#endif
37#endif
wdenkff36fd82005-01-09 22:28:56 +000038#endif
wdenk5da627a2003-10-09 20:09:04 +000039
wdenk5da627a2003-10-09 20:09:04 +000040#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
41
42#define CONFIG_BAUDRATE 115200
43
44/* valid baudrates */
wdenk5da627a2003-10-09 20:09:04 +000045
46#define CONFIG_TIMESTAMP /* Print image info with timestamp */
47#undef CONFIG_BOOTARGS
48
49#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010050 "addmisc=setenv bootargs ${bootargs} " \
51 "console=ttyS0,${baudrate} " \
wdenk5da627a2003-10-09 20:09:04 +000052 "panic=1\0" \
53 "bootfile=/tftpboot/vmlinux.srec\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010054 "load=tftp 80500000 ${u-boot}\0" \
wdenk5da627a2003-10-09 20:09:04 +000055 ""
wdenkff36fd82005-01-09 22:28:56 +000056
57#ifdef CONFIG_DBAU1550
58/* Boot from flash by default, revert to bootp */
59#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
wdenkff36fd82005-01-09 22:28:56 +000060#else /* CONFIG_DBAU1550 */
Heiko Schocherad882972006-04-11 14:53:29 +020061#define CONFIG_BOOTCOMMAND "bootp;bootm"
wdenkff36fd82005-01-09 22:28:56 +000062#endif /* CONFIG_DBAU1550 */
63
Jon Loeligerab999ba2007-07-04 22:32:03 -050064
65/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050066 * BOOTP options
67 */
68#define CONFIG_BOOTP_BOOTFILESIZE
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72
73
74/*
Jon Loeligerab999ba2007-07-04 22:32:03 -050075 * Command line configuration.
76 */
77#include <config_cmd_default.h>
78
79#undef CONFIG_CMD_BDI
80#undef CONFIG_CMD_BEDBUG
81#undef CONFIG_CMD_ELF
Mike Frysingerbdab39d2009-01-28 19:08:14 -050082#undef CONFIG_CMD_SAVEENV
Jon Loeligerab999ba2007-07-04 22:32:03 -050083#undef CONFIG_CMD_FAT
84#undef CONFIG_CMD_FPGA
85#undef CONFIG_CMD_MII
86#undef CONFIG_CMD_RUN
87
88
89#ifdef CONFIG_DBAU1550
90
91#define CONFIG_CMD_FLASH
92#define CONFIG_CMD_LOADB
93#define CONFIG_CMD_NET
94
95#undef CONFIG_CMD_I2C
96#undef CONFIG_CMD_IDE
97#undef CONFIG_CMD_NFS
98#undef CONFIG_CMD_PCMCIA
99
100#else
101
102#define CONFIG_CMD_IDE
103#define CONFIG_CMD_DHCP
104
105#undef CONFIG_CMD_FLASH
106#undef CONFIG_CMD_LOADB
107#undef CONFIG_CMD_LOADS
108
109#endif
110
wdenk5da627a2003-10-09 20:09:04 +0000111
112/*
113 * Miscellaneous configurable options
114 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkff36fd82005-01-09 22:28:56 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
wdenkff36fd82005-01-09 22:28:56 +0000118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
120#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
121#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
wdenk5da627a2003-10-09 20:09:04 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_MALLOC_LEN 128*1024
wdenk5da627a2003-10-09 20:09:04 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
wdenk5da627a2003-10-09 20:09:04 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_MHZ 396
wdenkff36fd82005-01-09 22:28:56 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#if (CONFIG_SYS_MHZ % 12) != 0
wdenkff36fd82005-01-09 22:28:56 +0000130#error "Invalid CPU frequency - must be multiple of 12!"
131#endif
132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Shinya Kuribayashia55d4812008-06-05 22:29:00 +0900134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
wdenk5da627a2003-10-09 20:09:04 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
wdenk5da627a2003-10-09 20:09:04 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MEMTEST_START 0x80100000
140#define CONFIG_SYS_MEMTEST_END 0x80800000
wdenk5da627a2003-10-09 20:09:04 +0000141
142/*-----------------------------------------------------------------------
143 * FLASH and environment organization
144 */
wdenkff36fd82005-01-09 22:28:56 +0000145#ifdef CONFIG_DBAU1550
146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
148#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
wdenkff36fd82005-01-09 22:28:56 +0000149
150#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
151#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
152
wdenkff36fd82005-01-09 22:28:56 +0000153#else /* CONFIG_DBAU1550 */
154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
156#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
wdenk5da627a2003-10-09 20:09:04 +0000157
158#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
159#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
160
wdenkff36fd82005-01-09 22:28:56 +0000161#endif /* CONFIG_DBAU1550 */
162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
Heiko Schocherad882972006-04-11 14:53:29 +0200164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200166#define CONFIG_FLASH_CFI_DRIVER 1
wdenkff36fd82005-01-09 22:28:56 +0000167
wdenk5da627a2003-10-09 20:09:04 +0000168/* The following #defines are needed to get flash environment right */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200169#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_MONITOR_LEN (192 << 10)
wdenk5da627a2003-10-09 20:09:04 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
wdenk5da627a2003-10-09 20:09:04 +0000173
174/* We boot from this flash, selected with dip switch */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
wdenk5da627a2003-10-09 20:09:04 +0000176
177/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
179#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk5da627a2003-10-09 20:09:04 +0000180
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200181#define CONFIG_ENV_IS_NOWHERE 1
wdenk5da627a2003-10-09 20:09:04 +0000182
183/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200184#define CONFIG_ENV_ADDR 0xB0030000
185#define CONFIG_ENV_SIZE 0x10000
wdenk5da627a2003-10-09 20:09:04 +0000186
187#define CONFIG_FLASH_16BIT
188
189#define CONFIG_NR_DRAM_BANKS 2
190
wdenk5da627a2003-10-09 20:09:04 +0000191
wdenkff36fd82005-01-09 22:28:56 +0000192#ifdef CONFIG_DBAU1550
193#define MEM_SIZE 192
194#else
195#define MEM_SIZE 64
196#endif
197
wdenk5da627a2003-10-09 20:09:04 +0000198#define CONFIG_MEMSIZE_IN_BYTES
199
wdenkff36fd82005-01-09 22:28:56 +0000200#ifndef CONFIG_DBAU1550
wdenk5da627a2003-10-09 20:09:04 +0000201/*---ATA PCMCIA ------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
203#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
wdenk5da627a2003-10-09 20:09:04 +0000204#define CONFIG_PCMCIA_SLOT_A
205
206#define CONFIG_ATAPI 1
207#define CONFIG_MAC_PARTITION 1
208
209/* We run CF in "true ide" mode or a harddrive via pcmcia */
210#define CONFIG_IDE_PCMCIA 1
211
212/* We only support one slot for now */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
214#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk5da627a2003-10-09 20:09:04 +0000215
216#undef CONFIG_IDE_LED /* LED for ide not supported */
217#undef CONFIG_IDE_RESET /* reset for ide not supported */
218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk5da627a2003-10-09 20:09:04 +0000220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk5da627a2003-10-09 20:09:04 +0000222
wdenkd4ca31c2004-01-02 14:00:00 +0000223/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_ATA_DATA_OFFSET 8
wdenk5da627a2003-10-09 20:09:04 +0000225
226/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_ATA_REG_OFFSET 0
wdenk5da627a2003-10-09 20:09:04 +0000228
229/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkff36fd82005-01-09 22:28:56 +0000231#endif /* CONFIG_DBAU1550 */
wdenk5da627a2003-10-09 20:09:04 +0000232
233/*-----------------------------------------------------------------------
234 * Cache Configuration
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_DCACHE_SIZE 16384
237#define CONFIG_SYS_ICACHE_SIZE 16384
238#define CONFIG_SYS_CACHELINE_SIZE 32
wdenk5da627a2003-10-09 20:09:04 +0000239
wdenk5da627a2003-10-09 20:09:04 +0000240#endif /* __CONFIG_H */