blob: e0837452351ffdd60a5549a698969c3ff05afa22 [file] [log] [blame]
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +00001/*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +00006 */
7
8#include <common.h>
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +00009#include <dwmmc.h>
Amara082a2d2013-04-27 11:42:55 +053010#include <fdtdec.h>
11#include <libfdt.h>
12#include <malloc.h>
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000013#include <asm/arch/dwmmc.h>
14#include <asm/arch/clk.h>
Amara082a2d2013-04-27 11:42:55 +053015#include <asm/arch/pinmux.h>
Przemyslaw Marczak64029f72015-02-20 12:29:26 +010016#include <asm/arch/power.h>
Jaehoon Chung959198f2014-05-16 13:59:52 +090017#include <asm/gpio.h>
18#include <asm-generic/errno.h>
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000019
Amara082a2d2013-04-27 11:42:55 +053020#define DWMMC_MAX_CH_NUM 4
21#define DWMMC_MAX_FREQ 52000000
22#define DWMMC_MIN_FREQ 400000
Jaehoon Chung5dab81c2015-02-04 15:48:40 +090023#define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001
24#define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001
25
26/* Exynos implmentation specific drver private data */
27struct dwmci_exynos_priv_data {
28 u32 sdr_timing;
29};
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000030
Amara082a2d2013-04-27 11:42:55 +053031/*
32 * Function used as callback function to initialise the
33 * CLKSEL register for every mmc channel.
34 */
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000035static void exynos_dwmci_clksel(struct dwmci_host *host)
36{
Jaehoon Chung5dab81c2015-02-04 15:48:40 +090037 struct dwmci_exynos_priv_data *priv = host->priv;
38
39 dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000040}
41
Rajeshwari S Shinded3e016c2014-02-05 10:48:15 +053042unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
Amara082a2d2013-04-27 11:42:55 +053043{
Rajeshwari S Shinded3e016c2014-02-05 10:48:15 +053044 unsigned long sclk;
45 int8_t clk_div;
46
47 /*
48 * Since SDCLKIN is divided inside controller by the DIVRATIO
49 * value set in the CLKSEL register, we need to use the same output
50 * clock value to calculate the CLKDIV value.
51 * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
52 */
53 clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
54 & DWMCI_DIVRATIO_MASK) + 1;
55 sclk = get_mmc_clk(host->dev_index);
56
Jaehoon Chung959198f2014-05-16 13:59:52 +090057 /*
58 * Assume to know divider value.
59 * When clock unit is broken, need to set "host->div"
60 */
61 return sclk / clk_div / (host->div + 1);
Amara082a2d2013-04-27 11:42:55 +053062}
63
Jaehoon Chung18ab6752013-11-29 20:08:57 +090064static void exynos_dwmci_board_init(struct dwmci_host *host)
65{
Jaehoon Chung5dab81c2015-02-04 15:48:40 +090066 struct dwmci_exynos_priv_data *priv = host->priv;
67
Jaehoon Chung18ab6752013-11-29 20:08:57 +090068 if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
69 dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
70 dwmci_writel(host, EMMCP_SEND0, 0);
71 dwmci_writel(host, EMMCP_CTRL0,
72 MPSCTRL_SECURE_READ_BIT |
73 MPSCTRL_SECURE_WRITE_BIT |
74 MPSCTRL_NON_SECURE_READ_BIT |
75 MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
76 }
Jaehoon Chung3a33bb12015-02-04 15:48:39 +090077
Jaehoon Chung5dab81c2015-02-04 15:48:40 +090078 /* Set to timing value at initial time */
79 if (priv->sdr_timing)
Jaehoon Chung3a33bb12015-02-04 15:48:39 +090080 exynos_dwmci_clksel(host);
Jaehoon Chung18ab6752013-11-29 20:08:57 +090081}
82
Jaehoon Chung959198f2014-05-16 13:59:52 +090083static int exynos_dwmci_core_init(struct dwmci_host *host, int index)
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000084{
Amara082a2d2013-04-27 11:42:55 +053085 unsigned int div;
86 unsigned long freq, sclk;
Jaehoon Chung5dab81c2015-02-04 15:48:40 +090087 struct dwmci_exynos_priv_data *priv = host->priv;
Jaehoon Chung959198f2014-05-16 13:59:52 +090088
89 if (host->bus_hz)
90 freq = host->bus_hz;
91 else
92 freq = DWMMC_MAX_FREQ;
93
Amara082a2d2013-04-27 11:42:55 +053094 /* request mmc clock vlaue of 52MHz. */
Amara082a2d2013-04-27 11:42:55 +053095 sclk = get_mmc_clk(index);
96 div = DIV_ROUND_UP(sclk, freq);
97 /* set the clock divisor for mmc */
98 set_mmc_clk(index, div);
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +000099
Amara082a2d2013-04-27 11:42:55 +0530100 host->name = "EXYNOS DWMMC";
Rajeshwari Shinde6f0b7ca2013-10-29 12:53:13 +0530101#ifdef CONFIG_EXYNOS5420
102 host->quirks = DWMCI_QUIRK_DISABLE_SMU;
103#endif
Jaehoon Chung18ab6752013-11-29 20:08:57 +0900104 host->board_init = exynos_dwmci_board_init;
Amara082a2d2013-04-27 11:42:55 +0530105
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900106 if (!priv->sdr_timing) {
Jaehoon Chung959198f2014-05-16 13:59:52 +0900107 if (index == 0)
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900108 priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
Jaehoon Chung959198f2014-05-16 13:59:52 +0900109 else if (index == 2)
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900110 priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
Amara082a2d2013-04-27 11:42:55 +0530111 }
112
Jaehoon Chunge09bd852014-05-16 13:59:57 +0900113 host->caps = MMC_MODE_DDR_52MHz;
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +0000114 host->clksel = exynos_dwmci_clksel;
115 host->dev_index = index;
Jaehoon Chungb44fe832013-10-06 18:59:31 +0900116 host->get_mmc_clk = exynos_dwmci_get_clk;
Amara082a2d2013-04-27 11:42:55 +0530117 /* Add the mmc channel to be registered with mmc core */
118 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
Jaehoon Chungdfcb6832014-11-28 20:42:33 +0900119 printf("DWMMC%d registration failed\n", index);
Amara082a2d2013-04-27 11:42:55 +0530120 return -1;
121 }
Jaehoon Chungd0ebbb82012-10-15 19:10:31 +0000122 return 0;
123}
124
Jaehoon Chung959198f2014-05-16 13:59:52 +0900125/*
126 * This function adds the mmc channel to be registered with mmc core.
127 * index - mmc channel number.
128 * regbase - register base address of mmc channel specified in 'index'.
129 * bus_width - operating bus width of mmc channel specified in 'index'.
130 * clksel - value to be written into CLKSEL register in case of FDT.
131 * NULL in case od non-FDT.
132 */
133int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel)
Amara082a2d2013-04-27 11:42:55 +0530134{
Jaehoon Chung959198f2014-05-16 13:59:52 +0900135 struct dwmci_host *host = NULL;
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900136 struct dwmci_exynos_priv_data *priv;
Amara082a2d2013-04-27 11:42:55 +0530137
Jaehoon Chung959198f2014-05-16 13:59:52 +0900138 host = malloc(sizeof(struct dwmci_host));
139 if (!host) {
140 error("dwmci_host malloc fail!\n");
141 return -ENOMEM;
142 }
143
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900144 priv = malloc(sizeof(struct dwmci_exynos_priv_data));
145 if (!priv) {
146 error("dwmci_exynos_priv_data malloc fail!\n");
147 return -ENOMEM;
148 }
149
Jaehoon Chung959198f2014-05-16 13:59:52 +0900150 host->ioaddr = (void *)regbase;
151 host->buswidth = bus_width;
152
153 if (clksel)
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900154 priv->sdr_timing = clksel;
155
156 host->priv = priv;
Jaehoon Chung959198f2014-05-16 13:59:52 +0900157
158 return exynos_dwmci_core_init(host, index);
159}
160
161#ifdef CONFIG_OF_CONTROL
162static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
163
164static int do_dwmci_init(struct dwmci_host *host)
165{
166 int index, flag, err;
167
168 index = host->dev_index;
169
170 flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
171 err = exynos_pinmux_config(host->dev_id, flag);
172 if (err) {
Jaehoon Chungdfcb6832014-11-28 20:42:33 +0900173 printf("DWMMC%d not configure\n", index);
Jaehoon Chung959198f2014-05-16 13:59:52 +0900174 return err;
175 }
176
177 return exynos_dwmci_core_init(host, index);
178}
179
180static int exynos_dwmci_get_config(const void *blob, int node,
181 struct dwmci_host *host)
182{
183 int err = 0;
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900184 u32 base, timing[3];
185 struct dwmci_exynos_priv_data *priv;
186
187 priv = malloc(sizeof(struct dwmci_exynos_priv_data));
188 if (!priv) {
189 error("dwmci_exynos_priv_data malloc fail!\n");
190 return -ENOMEM;
191 }
Jaehoon Chung959198f2014-05-16 13:59:52 +0900192
193 /* Extract device id for each mmc channel */
194 host->dev_id = pinmux_decode_periph_id(blob, node);
195
Jaehoon Chung959198f2014-05-16 13:59:52 +0900196 host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
197 if (host->dev_index == host->dev_id)
198 host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
199
Jaehoon Chungdfcb6832014-11-28 20:42:33 +0900200 /* Get the bus width from the device node */
201 host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
202 if (host->buswidth <= 0) {
203 printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
204 return -EINVAL;
205 }
206
Jaehoon Chung959198f2014-05-16 13:59:52 +0900207 /* Set the base address from the device node */
208 base = fdtdec_get_addr(blob, node, "reg");
209 if (!base) {
Jaehoon Chungdfcb6832014-11-28 20:42:33 +0900210 printf("DWMMC%d: Can't get base address\n", host->dev_index);
Jaehoon Chung959198f2014-05-16 13:59:52 +0900211 return -EINVAL;
212 }
213 host->ioaddr = (void *)base;
214
215 /* Extract the timing info from the node */
216 err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
217 if (err) {
Jaehoon Chungdfcb6832014-11-28 20:42:33 +0900218 printf("DWMMC%d: Can't get sdr-timings for devider\n",
219 host->dev_index);
Jaehoon Chung959198f2014-05-16 13:59:52 +0900220 return -EINVAL;
221 }
222
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900223 priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
Jaehoon Chung959198f2014-05-16 13:59:52 +0900224 DWMCI_SET_DRV_CLK(timing[1]) |
225 DWMCI_SET_DIV_RATIO(timing[2]));
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900226
227 /* sdr_timing didn't assigned anything, use the default value */
228 if (!priv->sdr_timing) {
229 if (host->dev_index == 0)
230 priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
231 else if (host->dev_index == 2)
232 priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
233 }
Jaehoon Chung959198f2014-05-16 13:59:52 +0900234
235 host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
236 host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
237 host->div = fdtdec_get_int(blob, node, "div", 0);
238
Jaehoon Chung5dab81c2015-02-04 15:48:40 +0900239 host->priv = priv;
240
Jaehoon Chung959198f2014-05-16 13:59:52 +0900241 return 0;
242}
243
244static int exynos_dwmci_process_node(const void *blob,
245 int node_list[], int count)
246{
247 struct dwmci_host *host;
248 int i, node, err;
Amara082a2d2013-04-27 11:42:55 +0530249
250 for (i = 0; i < count; i++) {
Jaehoon Chung959198f2014-05-16 13:59:52 +0900251 node = node_list[i];
Amara082a2d2013-04-27 11:42:55 +0530252 if (node <= 0)
253 continue;
Jaehoon Chung959198f2014-05-16 13:59:52 +0900254 host = &dwmci_host[i];
255 err = exynos_dwmci_get_config(blob, node, host);
Amara082a2d2013-04-27 11:42:55 +0530256 if (err) {
Jaehoon Chungdfcb6832014-11-28 20:42:33 +0900257 printf("%s: failed to decode dev %d\n", __func__, i);
Amara082a2d2013-04-27 11:42:55 +0530258 return err;
259 }
260
Jaehoon Chung959198f2014-05-16 13:59:52 +0900261 do_dwmci_init(host);
Amara082a2d2013-04-27 11:42:55 +0530262 }
263 return 0;
264}
Jaehoon Chung959198f2014-05-16 13:59:52 +0900265
266int exynos_dwmmc_init(const void *blob)
267{
268 int compat_id;
269 int node_list[DWMMC_MAX_CH_NUM];
Przemyslaw Marczak64029f72015-02-20 12:29:26 +0100270 int boot_dev_node;
Jaehoon Chung959198f2014-05-16 13:59:52 +0900271 int err = 0, count;
272
273 compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC;
274
275 count = fdtdec_find_aliases_for_id(blob, "mmc",
276 compat_id, node_list, DWMMC_MAX_CH_NUM);
Przemyslaw Marczak64029f72015-02-20 12:29:26 +0100277
278 /* For DWMMC always set boot device as mmc 0 */
279 if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) {
280 boot_dev_node = node_list[2];
281 node_list[2] = node_list[0];
282 node_list[0] = boot_dev_node;
283 }
284
Jaehoon Chung959198f2014-05-16 13:59:52 +0900285 err = exynos_dwmci_process_node(blob, node_list, count);
286
287 return err;
288}
Amara082a2d2013-04-27 11:42:55 +0530289#endif