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wdenkf4675562002-10-02 14:20:15 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42
43#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44
wdenkae3af052003-08-07 22:18:11 +000045#define CONFIG_BOOTCOUNT_LIMIT
wdenkf4675562002-10-02 14:20:15 +000046
wdenkae3af052003-08-07 22:18:11 +000047#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000048
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
51#define CONFIG_PREBOOT "echo;" \
wdenk6aff3112002-12-17 01:51:00 +000052 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
53 "echo"
wdenkf4675562002-10-02 14:20:15 +000054
55#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000056
57#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000058 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000059 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000061 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000065 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000067 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010068 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000070 "rootpath=/opt/eldk/ppc_8xx\0" \
wdenk3bac3512003-03-12 10:41:04 +000071 "bootfile=/tftpboot/TQM860L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020072 "fdt_addr=40040000\0" \
73 "kernel_addr=40060000\0" \
74 "ramdisk_addr=40200000\0" \
wdenk6aff3112002-12-17 01:51:00 +000075 ""
76#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000077
78#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
79#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
80
81#undef CONFIG_WATCHDOG /* watchdog disabled */
82
83#define CONFIG_STATUS_LED 1 /* Status LED enabled */
84
85#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
86
Jon Loeliger37d4bb72007-07-09 21:38:02 -050087/*
88 * BOOTP options
89 */
90#define CONFIG_BOOTP_SUBNETMASK
91#define CONFIG_BOOTP_GATEWAY
92#define CONFIG_BOOTP_HOSTNAME
93#define CONFIG_BOOTP_BOOTPATH
94#define CONFIG_BOOTP_BOOTFILESIZE
95
wdenkf4675562002-10-02 14:20:15 +000096
97#define CONFIG_MAC_PARTITION
98#define CONFIG_DOS_PARTITION
99
100#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
101
Jon Loeliger26946902007-07-04 22:30:50 -0500102
103/*
104 * Command line configuration.
105 */
106#include <config_cmd_default.h>
107
108#define CONFIG_CMD_ASKENV
109#define CONFIG_CMD_DATE
110#define CONFIG_CMD_DHCP
111#define CONFIG_CMD_ELF
112#define CONFIG_CMD_IDE
113#define CONFIG_CMD_NFS
114#define CONFIG_CMD_SNTP
115
wdenkf4675562002-10-02 14:20:15 +0000116
wdenk68ceb292004-08-02 21:11:11 +0000117#define CONFIG_NETCONSOLE
118
wdenkf4675562002-10-02 14:20:15 +0000119/*
120 * Miscellaneous configurable options
121 */
122#define CFG_LONGHELP /* undef to save memory */
123#define CFG_PROMPT "=> " /* Monitor Command Prompt */
124
Wolfgang Denk2751a952006-10-28 02:29:14 +0200125#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
126#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf4675562002-10-02 14:20:15 +0000127#ifdef CFG_HUSH_PARSER
128#define CFG_PROMPT_HUSH_PS2 "> "
129#endif
130
Jon Loeliger26946902007-07-04 22:30:50 -0500131#if defined(CONFIG_CMD_KGDB)
wdenkf4675562002-10-02 14:20:15 +0000132#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
133#else
134#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
135#endif
136#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
137#define CFG_MAXARGS 16 /* max number of command args */
138#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
139
140#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
141#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
142
143#define CFG_LOAD_ADDR 0x100000 /* default load address */
144
145#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
146
147#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
148
149/*
150 * Low Level Configuration Settings
151 * (address mappings, register initial values, etc.)
152 * You should know what you are doing if you make changes here.
153 */
154/*-----------------------------------------------------------------------
155 * Internal Memory Mapped Register
156 */
157#define CFG_IMMR 0xFFF00000
158
159/*-----------------------------------------------------------------------
160 * Definitions for initial stack pointer and data area (in DPRAM)
161 */
162#define CFG_INIT_RAM_ADDR CFG_IMMR
163#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
164#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
165#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
166#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
167
168/*-----------------------------------------------------------------------
169 * Start addresses for the final memory configuration
170 * (Set up by the startup code)
171 * Please note that CFG_SDRAM_BASE _must_ start at 0
172 */
173#define CFG_SDRAM_BASE 0x00000000
174#define CFG_FLASH_BASE 0x40000000
175#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
176#define CFG_MONITOR_BASE CFG_FLASH_BASE
177#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
178
179/*
180 * For booting Linux, the board info and command line data
181 * have to be in the first 8 MB of memory, since this is
182 * the maximum mapped by the Linux kernel during initialization.
183 */
184#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
185
186/*-----------------------------------------------------------------------
187 * FLASH organization
188 */
wdenkf4675562002-10-02 14:20:15 +0000189
Martin Krausee318d9e2007-09-27 11:10:08 +0200190/* use CFI flash driver */
191#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
192#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
193#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
194#define CFG_FLASH_EMPTY_INFO
195#define CFG_FLASH_USE_BUFFER_WRITE 1
196#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
197#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000198
199#define CFG_ENV_IS_IN_FLASH 1
200#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
201#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
202
203/* Address and size of Redundant Environment Sector */
204#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
205#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
206
Wolfgang Denk67c31032007-09-16 17:10:04 +0200207#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
208
wdenkf4675562002-10-02 14:20:15 +0000209/*-----------------------------------------------------------------------
210 * Hardware Information Block
211 */
212#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
213#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
214#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
215
216/*-----------------------------------------------------------------------
217 * Cache Configuration
218 */
219#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500220#if defined(CONFIG_CMD_KGDB)
wdenkf4675562002-10-02 14:20:15 +0000221#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
222#endif
223
224/*-----------------------------------------------------------------------
225 * SYPCR - System Protection Control 11-9
226 * SYPCR can only be written once after reset!
227 *-----------------------------------------------------------------------
228 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
229 */
230#if defined(CONFIG_WATCHDOG)
231#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
232 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
233#else
234#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
235#endif
236
237/*-----------------------------------------------------------------------
238 * SIUMCR - SIU Module Configuration 11-6
239 *-----------------------------------------------------------------------
240 * PCMCIA config., multi-function pin tri-state
241 */
242#ifndef CONFIG_CAN_DRIVER
243#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
244#else /* we must activate GPL5 in the SIUMCR for CAN */
245#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
246#endif /* CONFIG_CAN_DRIVER */
247
248/*-----------------------------------------------------------------------
249 * TBSCR - Time Base Status and Control 11-26
250 *-----------------------------------------------------------------------
251 * Clear Reference Interrupt Status, Timebase freezing enabled
252 */
253#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
254
255/*-----------------------------------------------------------------------
256 * RTCSC - Real-Time Clock Status and Control Register 11-27
257 *-----------------------------------------------------------------------
258 */
259#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
260
261/*-----------------------------------------------------------------------
262 * PISCR - Periodic Interrupt Status and Control 11-31
263 *-----------------------------------------------------------------------
264 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
265 */
266#define CFG_PISCR (PISCR_PS | PISCR_PITF)
267
268/*-----------------------------------------------------------------------
269 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
270 *-----------------------------------------------------------------------
271 * Reset PLL lock status sticky bit, timer expired status bit and timer
272 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000273 */
wdenkf4675562002-10-02 14:20:15 +0000274#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000275
276/*-----------------------------------------------------------------------
277 * SCCR - System Clock and reset Control Register 15-27
278 *-----------------------------------------------------------------------
279 * Set clock output, timebase and RTC source and divider,
280 * power management and some other internal clocks
281 */
282#define SCCR_MASK SCCR_EBDF11
wdenke9132ea2004-04-24 23:23:30 +0000283#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000284 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
285 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000286
287/*-----------------------------------------------------------------------
288 * PCMCIA stuff
289 *-----------------------------------------------------------------------
290 *
291 */
292#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
293#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
294#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
295#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
296#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
297#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
298#define CFG_PCMCIA_IO_ADDR (0xEC000000)
299#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
300
301/*-----------------------------------------------------------------------
302 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
303 *-----------------------------------------------------------------------
304 */
305
306#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
307
308#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
309#undef CONFIG_IDE_LED /* LED for ide not supported */
310#undef CONFIG_IDE_RESET /* reset for ide not supported */
311
312#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
313#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
314
315#define CFG_ATA_IDE0_OFFSET 0x0000
316
317#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
318
319/* Offset for data I/O */
320#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
321
322/* Offset for normal register accesses */
323#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
324
325/* Offset for alternate registers */
326#define CFG_ATA_ALT_OFFSET 0x0100
327
328/*-----------------------------------------------------------------------
329 *
330 *-----------------------------------------------------------------------
331 *
332 */
wdenkf4675562002-10-02 14:20:15 +0000333#define CFG_DER 0
334
335/*
336 * Init Memory Controller:
337 *
338 * BR0/1 and OR0/1 (FLASH)
339 */
340
341#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
342#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
343
344/* used to re-map FLASH both when starting from SRAM or FLASH:
345 * restrict access enough to keep SRAM working (if any)
346 * but not too much to meddle with FLASH accesses
347 */
348#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
349#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
350
351/*
352 * FLASH timing:
353 */
wdenkf4675562002-10-02 14:20:15 +0000354#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
355 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000356
357#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
358#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
359#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
360
361#define CFG_OR1_REMAP CFG_OR0_REMAP
362#define CFG_OR1_PRELIM CFG_OR0_PRELIM
363#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
364
365/*
366 * BR2/3 and OR2/3 (SDRAM)
367 *
368 */
369#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
370#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
371#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
372
373/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
374#define CFG_OR_TIMING_SDRAM 0x00000A00
375
376#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
377#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
378
379#ifndef CONFIG_CAN_DRIVER
380#define CFG_OR3_PRELIM CFG_OR2_PRELIM
381#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
382#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
383#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
384#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
385#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
386#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
387 BR_PS_8 | BR_MS_UPMB | BR_V )
388#endif /* CONFIG_CAN_DRIVER */
389
390/*
391 * Memory Periodic Timer Prescaler
392 *
393 * The Divider for PTA (refresh timer) configuration is based on an
394 * example SDRAM configuration (64 MBit, one bank). The adjustment to
395 * the number of chip selects (NCS) and the actually needed refresh
396 * rate is done by setting MPTPR.
397 *
398 * PTA is calculated from
399 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
400 *
401 * gclk CPU clock (not bus clock!)
402 * Trefresh Refresh cycle * 4 (four word bursts used)
403 *
404 * 4096 Rows from SDRAM example configuration
405 * 1000 factor s -> ms
406 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
407 * 4 Number of refresh cycles per period
408 * 64 Refresh cycle in ms per number of rows
409 * --------------------------------------------
410 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
411 *
412 * 50 MHz => 50.000.000 / Divider = 98
413 * 66 Mhz => 66.000.000 / Divider = 129
414 * 80 Mhz => 80.000.000 / Divider = 156
415 */
wdenke9132ea2004-04-24 23:23:30 +0000416
417#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
418#define CFG_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000419
420/*
421 * For 16 MBit, refresh rates could be 31.3 us
422 * (= 64 ms / 2K = 125 / quad bursts).
423 * For a simpler initialization, 15.6 us is used instead.
424 *
425 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
426 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
427 */
428#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
429#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
430
431/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
432#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
433#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
434
435/*
436 * MAMR settings for SDRAM
437 */
438
439/* 8 column SDRAM */
440#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
441 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
442 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
443/* 9 column SDRAM */
444#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
445 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
446 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
447
448
449/*
450 * Internal Definitions
451 *
452 * Boot Flags
453 */
454#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
455#define BOOTFLAG_WARM 0x02 /* Software reboot */
456
457#define CONFIG_SCC1_ENET
458#define CONFIG_FEC_ENET
459#define CONFIG_ETHPRIME "SCC ETHERNET"
460
461#endif /* __CONFIG_H */