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wdenk2262cfe2002-11-18 00:14:45 +00001/*
wdenk8bde7f72003-06-27 21:31:46 +00002 *
wdenk2262cfe2002-11-18 00:14:45 +00003 * (C) Copyright 2002
4 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <pci.h>
27#include <asm/io.h>
wdenk7a8e9bed2003-05-31 18:35:21 +000028#include <asm/pci.h>
wdenk2262cfe2002-11-18 00:14:45 +000029#include <asm/ic/sc520.h>
30#include <asm/ic/ali512x.h>
wdenkbdccc4f2003-08-05 17:43:17 +000031#include <spi.h>
Ben Warrene3090532008-08-31 10:08:43 -070032#include <netdev.h>
wdenk7a8e9bed2003-05-31 18:35:21 +000033
Wolfgang Denkd87080b2006-03-31 18:32:53 +020034DECLARE_GLOBAL_DATA_PTR;
35
wdenk7a8e9bed2003-05-31 18:35:21 +000036#undef SC520_CDP_DEBUG
37
38#ifdef SC520_CDP_DEBUG
39#define PRINTF(fmt,args...) printf (fmt ,##args)
40#else
41#define PRINTF(fmt,args...)
42#endif
wdenk2262cfe2002-11-18 00:14:45 +000043
44/* ------------------------------------------------------------------------- */
45
wdenk8bde7f72003-06-27 21:31:46 +000046
47/*
wdenk7a8e9bed2003-05-31 18:35:21 +000048 * Theory:
49 * We first set up all IRQs to be non-pci, edge triggered,
wdenk8bde7f72003-06-27 21:31:46 +000050 * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
wdenk7a8e9bed2003-05-31 18:35:21 +000051 * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
52 * as needed. Whe choose the irqs to gram from a configurable list
53 * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
54 * such as 0 thngas will not work)
55 */
56
wdenk2262cfe2002-11-18 00:14:45 +000057static void irq_init(void)
58{
wdenk2262cfe2002-11-18 00:14:45 +000059 /* disable global interrupt mode */
wdenk8bde7f72003-06-27 21:31:46 +000060 write_mmcr_byte(SC520_PICICR, 0x40);
61
wdenk7a8e9bed2003-05-31 18:35:21 +000062 /* set all irqs to edge */
wdenk2262cfe2002-11-18 00:14:45 +000063 write_mmcr_byte(SC520_MPICMODE, 0x00);
wdenk7a8e9bed2003-05-31 18:35:21 +000064 write_mmcr_byte(SC520_SL1PICMODE, 0x00);
65 write_mmcr_byte(SC520_SL2PICMODE, 0x00);
wdenk8bde7f72003-06-27 21:31:46 +000066
67 /* active low polarity on PIC interrupt pins,
wdenk7a8e9bed2003-05-31 18:35:21 +000068 * active high polarity on all other irq pins */
69 write_mmcr_word(SC520_INTPINPOL, 0x0000);
wdenk2262cfe2002-11-18 00:14:45 +000070
71 /* set irq number mapping */
wdenk8bde7f72003-06-27 21:31:46 +000072 write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED); /* disable GP timer 0 INT */
wdenk7a8e9bed2003-05-31 18:35:21 +000073 write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED); /* disable GP timer 1 INT */
74 write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED); /* disable GP timer 2 INT */
wdenk8bde7f72003-06-27 21:31:46 +000075 write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0); /* Set PIT timer 0 INT to IRQ0 */
wdenk7a8e9bed2003-05-31 18:35:21 +000076 write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED); /* disable PIT timer 1 INT */
77 write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED); /* disable PIT timer 2 INT */
78 write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED); /* disable PCI INT A */
79 write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED); /* disable PCI INT B */
80 write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED); /* disable PCI INT C */
81 write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED); /* disable PCI INT D */
wdenk8bde7f72003-06-27 21:31:46 +000082 write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
wdenk7a8e9bed2003-05-31 18:35:21 +000083 write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED); /* disable Synchronius serial INT */
84 write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED); /* disable Watchdog INT */
85 write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8); /* Set RTC int to 8 */
86 write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED); /* disable write protect INT */
87 write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */
88 write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */
wdenk8bde7f72003-06-27 21:31:46 +000089
wdenk2262cfe2002-11-18 00:14:45 +000090 if (CFG_USE_SIO_UART) {
wdenk7a8e9bed2003-05-31 18:35:21 +000091 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
92 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
wdenk8bde7f72003-06-27 21:31:46 +000093 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
wdenk7a8e9bed2003-05-31 18:35:21 +000094 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4); /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
wdenk2262cfe2002-11-18 00:14:45 +000095 } else {
wdenk7a8e9bed2003-05-31 18:35:21 +000096 write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4); /* Set internal UART2 INT to IRQ4 */
97 write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3); /* Set internal UART2 INT to IRQ3 */
wdenk8bde7f72003-06-27 21:31:46 +000098 write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ3 (ISA IRQ3) */
wdenk7a8e9bed2003-05-31 18:35:21 +000099 write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED); /* disable GPIRQ4 (ISA IRQ4) */
wdenk2262cfe2002-11-18 00:14:45 +0000100 }
wdenk8bde7f72003-06-27 21:31:46 +0000101
wdenk7a8e9bed2003-05-31 18:35:21 +0000102 write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1); /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
103 write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5); /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
104 write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6); /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
105 write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7); /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
106 write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8); /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
107 write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9); /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
108 write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11); /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
109 write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12); /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
wdenk8bde7f72003-06-27 21:31:46 +0000110 write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14); /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
111
wdenk7a8e9bed2003-05-31 18:35:21 +0000112 write_mmcr_word(SC520_PCIHOSTMAP, 0x11f); /* Map PCI hostbridge INT to NMI */
113 write_mmcr_word(SC520_ECCMAP, 0x100); /* Map SDRAM ECC failure INT to NMI */
wdenk8bde7f72003-06-27 21:31:46 +0000114
wdenk2262cfe2002-11-18 00:14:45 +0000115}
116
wdenk8bde7f72003-06-27 21:31:46 +0000117
wdenk2262cfe2002-11-18 00:14:45 +0000118/* PCI stuff */
119static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
120{
wdenk7a8e9bed2003-05-31 18:35:21 +0000121 /* a configurable lists of irqs to steal
122 * when we need one (a board with more pci interrupt pins
123 * would use a larger table */
124 static int irq_list[] = {
125 CFG_FIRST_PCI_IRQ,
126 CFG_SECOND_PCI_IRQ,
127 CFG_THIRD_PCI_IRQ,
128 CFG_FORTH_PCI_IRQ
129 };
130 static int next_irq_index=0;
wdenk8bde7f72003-06-27 21:31:46 +0000131
132 char tmp_pin;
wdenk7a8e9bed2003-05-31 18:35:21 +0000133 int pin;
wdenk8bde7f72003-06-27 21:31:46 +0000134
wdenk7a8e9bed2003-05-31 18:35:21 +0000135 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
136 pin = tmp_pin;
wdenk8bde7f72003-06-27 21:31:46 +0000137
wdenk7a8e9bed2003-05-31 18:35:21 +0000138 pin-=1; /* pci config space use 1-based numbering */
139 if (-1 == pin) {
140 return; /* device use no irq */
141 }
wdenk8bde7f72003-06-27 21:31:46 +0000142
143
wdenk7a8e9bed2003-05-31 18:35:21 +0000144 /* map device number + pin to a pin on the sc520 */
wdenk2262cfe2002-11-18 00:14:45 +0000145 switch (PCI_DEV(dev)) {
146 case 20:
wdenk7a8e9bed2003-05-31 18:35:21 +0000147 pin+=SC520_PCI_INTA;
wdenk2262cfe2002-11-18 00:14:45 +0000148 break;
wdenk8bde7f72003-06-27 21:31:46 +0000149
wdenk2262cfe2002-11-18 00:14:45 +0000150 case 19:
wdenk7a8e9bed2003-05-31 18:35:21 +0000151 pin+=SC520_PCI_INTB;
wdenk2262cfe2002-11-18 00:14:45 +0000152 break;
wdenk8bde7f72003-06-27 21:31:46 +0000153
wdenk2262cfe2002-11-18 00:14:45 +0000154 case 18:
wdenk7a8e9bed2003-05-31 18:35:21 +0000155 pin+=SC520_PCI_INTC;
wdenk2262cfe2002-11-18 00:14:45 +0000156 break;
wdenk8bde7f72003-06-27 21:31:46 +0000157
wdenk2262cfe2002-11-18 00:14:45 +0000158 case 17:
wdenk7a8e9bed2003-05-31 18:35:21 +0000159 pin+=SC520_PCI_INTD;
wdenk2262cfe2002-11-18 00:14:45 +0000160 break;
wdenk8bde7f72003-06-27 21:31:46 +0000161
162 default:
wdenk2262cfe2002-11-18 00:14:45 +0000163 return;
164 }
wdenk8bde7f72003-06-27 21:31:46 +0000165
wdenk7a8e9bed2003-05-31 18:35:21 +0000166 pin&=3; /* wrap around */
wdenk8bde7f72003-06-27 21:31:46 +0000167
wdenk7a8e9bed2003-05-31 18:35:21 +0000168 if (sc520_pci_ints[pin] == -1) {
wdenk8bde7f72003-06-27 21:31:46 +0000169 /* re-route one interrupt for us */
wdenk7a8e9bed2003-05-31 18:35:21 +0000170 if (next_irq_index > 3) {
171 return;
172 }
wdenk8bde7f72003-06-27 21:31:46 +0000173 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
wdenk7a8e9bed2003-05-31 18:35:21 +0000174 return;
175 }
176 next_irq_index++;
177 }
178
wdenk8bde7f72003-06-27 21:31:46 +0000179
wdenk7a8e9bed2003-05-31 18:35:21 +0000180 if (-1 != sc520_pci_ints[pin]) {
wdenk8bde7f72003-06-27 21:31:46 +0000181 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
wdenk7a8e9bed2003-05-31 18:35:21 +0000182 sc520_pci_ints[pin]);
183 }
wdenk8bde7f72003-06-27 21:31:46 +0000184 PRINTF("fixup_irq: device %d pin %c irq %d\n",
wdenk7a8e9bed2003-05-31 18:35:21 +0000185 PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
wdenk2262cfe2002-11-18 00:14:45 +0000186}
wdenk8bde7f72003-06-27 21:31:46 +0000187
wdenk2262cfe2002-11-18 00:14:45 +0000188static struct pci_controller sc520_cdp_hose = {
189 fixup_irq: pci_sc520_cdp_fixup_irq,
190};
191
stroesead10dd92003-02-14 11:21:23 +0000192void pci_init_board(void)
wdenk2262cfe2002-11-18 00:14:45 +0000193{
194 pci_sc520_init(&sc520_cdp_hose);
195}
196
197
198static void silence_uart(int port)
199{
200 outb(0, port+1);
201}
202
203void setup_ali_sio(int uart_primary)
204{
205 ali512x_init();
wdenk8bde7f72003-06-27 21:31:46 +0000206
wdenk2262cfe2002-11-18 00:14:45 +0000207 ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0);
208 ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3);
209 ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4);
210 ali512x_set_uart(ALI_ENABLED, ALI_UART2, uart_primary?0x2f8:0x2e8, 3);
211 ali512x_set_rtc(ALI_DISABLED, 0, 0);
212 ali512x_set_kbc(ALI_ENABLED, 1, 12);
213 ali512x_set_cio(ALI_ENABLED);
wdenk8bde7f72003-06-27 21:31:46 +0000214
wdenk2262cfe2002-11-18 00:14:45 +0000215 /* IrDa pins */
216 ali512x_cio_function(12, 1, 0, 0);
217 ali512x_cio_function(13, 1, 0, 0);
wdenk8bde7f72003-06-27 21:31:46 +0000218
wdenk2262cfe2002-11-18 00:14:45 +0000219 /* SSI chip select pins */
220 ali512x_cio_function(14, 0, 0, 0); /* SSI_CS */
wdenk8bde7f72003-06-27 21:31:46 +0000221 ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */
wdenk7a8e9bed2003-05-31 18:35:21 +0000222 ali512x_cio_function(16, 0, 0, 0); /* SSI_SPI# */
wdenk2262cfe2002-11-18 00:14:45 +0000223
224 /* Board REV pins */
225 ali512x_cio_function(20, 0, 0, 1);
226 ali512x_cio_function(21, 0, 0, 1);
227 ali512x_cio_function(22, 0, 0, 1);
wdenk8bde7f72003-06-27 21:31:46 +0000228 ali512x_cio_function(23, 0, 0, 1);
wdenk2262cfe2002-11-18 00:14:45 +0000229}
230
231
232/* set up the ISA bus timing and system address mappings */
233static void bus_init(void)
234{
235
236 /* set up the GP IO pins */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200237 write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff); /* set the GPIO pin function 31-16 reg */
238 write_mmcr_word(SC520_PIOPFS15_0, 0xffff); /* set the GPIO pin function 15-0 reg */
239 write_mmcr_byte(SC520_CSPFS, 0xf8); /* set the CS pin function reg */
wdenk2262cfe2002-11-18 00:14:45 +0000240 write_mmcr_byte(SC520_CLKSEL, 0x70);
241
wdenk8bde7f72003-06-27 21:31:46 +0000242
243 write_mmcr_byte(SC520_GPCSRT, 1); /* set the GP CS offset */
wdenk2262cfe2002-11-18 00:14:45 +0000244 write_mmcr_byte(SC520_GPCSPW, 3); /* set the GP CS pulse width */
245 write_mmcr_byte(SC520_GPCSOFF, 1); /* set the GP CS offset */
246 write_mmcr_byte(SC520_GPRDW, 3); /* set the RD pulse width */
247 write_mmcr_byte(SC520_GPRDOFF, 1); /* set the GP RD offset */
wdenk8bde7f72003-06-27 21:31:46 +0000248 write_mmcr_byte(SC520_GPWRW, 3); /* set the GP WR pulse width */
wdenk2262cfe2002-11-18 00:14:45 +0000249 write_mmcr_byte(SC520_GPWROFF, 1); /* set the GP WR offset */
250
wdenk8bde7f72003-06-27 21:31:46 +0000251 write_mmcr_word(SC520_BOOTCSCTL, 0x1823); /* set up timing of BOOTCS */
wdenk2262cfe2002-11-18 00:14:45 +0000252 write_mmcr_word(SC520_ROMCS1CTL, 0x1823); /* set up timing of ROMCS1 */
wdenk8bde7f72003-06-27 21:31:46 +0000253 write_mmcr_word(SC520_ROMCS2CTL, 0x1823); /* set up timing of ROMCS2 */
254
wdenk2262cfe2002-11-18 00:14:45 +0000255 /* adjust the memory map:
256 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
257 * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio
wdenk8bde7f72003-06-27 21:31:46 +0000258 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
259
260
wdenk2262cfe2002-11-18 00:14:45 +0000261 /* SRAM = GPCS3 128k @ d0000-effff*/
wdenk8bde7f72003-06-27 21:31:46 +0000262 write_mmcr_long(SC520_PAR2, 0x4e00400d);
263
wdenk2262cfe2002-11-18 00:14:45 +0000264 /* IDE0 = GPCS6 1f0-1f7 */
wdenk8bde7f72003-06-27 21:31:46 +0000265 write_mmcr_long(SC520_PAR3, 0x380801f0);
wdenk2262cfe2002-11-18 00:14:45 +0000266
267 /* IDE1 = GPCS7 3f6 */
wdenk8bde7f72003-06-27 21:31:46 +0000268 write_mmcr_long(SC520_PAR4, 0x3c0003f6);
wdenk2262cfe2002-11-18 00:14:45 +0000269 /* bootcs */
wdenk8bde7f72003-06-27 21:31:46 +0000270 write_mmcr_long(SC520_PAR12, 0x8bffe800);
wdenk2262cfe2002-11-18 00:14:45 +0000271 /* romcs2 */
wdenk8bde7f72003-06-27 21:31:46 +0000272 write_mmcr_long(SC520_PAR13, 0xcbfff000);
wdenk2262cfe2002-11-18 00:14:45 +0000273 /* romcs1 */
wdenk8bde7f72003-06-27 21:31:46 +0000274 write_mmcr_long(SC520_PAR14, 0xabfff800);
wdenk2262cfe2002-11-18 00:14:45 +0000275 /* 680 LEDS */
wdenk8bde7f72003-06-27 21:31:46 +0000276 write_mmcr_long(SC520_PAR15, 0x30000640);
277
wdenk7a8e9bed2003-05-31 18:35:21 +0000278 write_mmcr_byte(SC520_ADDDECCTL, 0);
wdenk8bde7f72003-06-27 21:31:46 +0000279
280 asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
wdenk2262cfe2002-11-18 00:14:45 +0000281
282 if (CFG_USE_SIO_UART) {
wdenk8bde7f72003-06-27 21:31:46 +0000283 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
wdenk2262cfe2002-11-18 00:14:45 +0000284 setup_ali_sio(1);
285 } else {
wdenk7a8e9bed2003-05-31 18:35:21 +0000286 write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
wdenk2262cfe2002-11-18 00:14:45 +0000287 setup_ali_sio(0);
288 silence_uart(0x3e8);
289 silence_uart(0x2e8);
290 }
291
292}
293
wdenk7a8e9bed2003-05-31 18:35:21 +0000294/* GPCS usage
295 * GPCS0 PIO27 (NMI)
296 * GPCS1 ROMCS1
297 * GPCS2 ROMCS2
298 * GPCS3 SRAMCS PAR2
299 * GPCS4 unused PAR3
300 * GPCS5 unused PAR4
301 * GPCS6 IDE
302 * GPCS7 IDE
303 */
wdenk2262cfe2002-11-18 00:14:45 +0000304
305
wdenk7a8e9bed2003-05-31 18:35:21 +0000306/* par usage:
307 * PAR0 legacy_video
308 * PAR1 PCI ROM mapping
309 * PAR2 SRAM
310 * PAR3 IDE
311 * PAR4 IDE
312 * PAR5 legacy_video
313 * PAR6 legacy_video
314 * PAR7 legacy_video
315 * PAR8 legacy_video
316 * PAR9 legacy_video
317 * PAR10 legacy_video
318 * PAR11 ISAROM
319 * PAR12 BOOTCS
320 * PAR13 ROMCS1
321 * PAR14 ROMCS2
322 * PAR15 Port 0x680 LED display
323 */
324
wdenk8bde7f72003-06-27 21:31:46 +0000325/*
wdenk7a8e9bed2003-05-31 18:35:21 +0000326 * This function should map a chunk of size bytes
327 * of the system address space to the ISA bus
wdenk8bde7f72003-06-27 21:31:46 +0000328 *
wdenk7a8e9bed2003-05-31 18:35:21 +0000329 * The function will return the memory address
330 * as seen by the host (which may very will be the
331 * same as the bus address)
332 */
wdenk8bde7f72003-06-27 21:31:46 +0000333u32 isa_map_rom(u32 bus_addr, int size)
wdenk7a8e9bed2003-05-31 18:35:21 +0000334{
335 u32 par;
wdenk8bde7f72003-06-27 21:31:46 +0000336
337 PRINTF("isa_map_rom asked to map %d bytes at %x\n",
wdenk7a8e9bed2003-05-31 18:35:21 +0000338 size, bus_addr);
wdenk8bde7f72003-06-27 21:31:46 +0000339
wdenk7a8e9bed2003-05-31 18:35:21 +0000340 par = size;
341 if (par < 0x80000) {
342 par = 0x80000;
343 }
344 par >>= 12;
345 par--;
346 par&=0x7f;
347 par <<= 18;
348 par |= (bus_addr>>12);
349 par |= 0x50000000;
wdenk8bde7f72003-06-27 21:31:46 +0000350
wdenk7a8e9bed2003-05-31 18:35:21 +0000351 PRINTF ("setting PAR11 to %x\n", par);
wdenk8bde7f72003-06-27 21:31:46 +0000352
wdenk7a8e9bed2003-05-31 18:35:21 +0000353 /* Map rom 0x10000 with PAR1 */
354 write_mmcr_long(SC520_PAR11, par);
wdenk8bde7f72003-06-27 21:31:46 +0000355
wdenk7a8e9bed2003-05-31 18:35:21 +0000356 return bus_addr;
357}
358
359/*
360 * this function removed any mapping created
361 * with pci_get_rom_window()
362 */
363void isa_unmap_rom(u32 addr)
364{
365 PRINTF("isa_unmap_rom asked to unmap %x", addr);
366 if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
367 write_mmcr_long(SC520_PAR11, 0);
368 PRINTF(" done\n");
369 return;
370 }
371 PRINTF(" not ours\n");
372}
373
374#ifdef CONFIG_PCI
375#define PCI_ROM_TEMP_SPACE 0x10000
wdenk8bde7f72003-06-27 21:31:46 +0000376/*
wdenk7a8e9bed2003-05-31 18:35:21 +0000377 * This function should map a chunk of size bytes
378 * of the system address space to the PCI bus,
379 * suitable to map PCI ROMS (bus address < 16M)
380 * the function will return the host memory address
381 * which should be converted into a bus address
wdenk8bde7f72003-06-27 21:31:46 +0000382 * before used to configure the PCI rom address
wdenk7a8e9bed2003-05-31 18:35:21 +0000383 * decoder
384 */
wdenk8bde7f72003-06-27 21:31:46 +0000385u32 pci_get_rom_window(struct pci_controller *hose, int size)
wdenk7a8e9bed2003-05-31 18:35:21 +0000386{
387 u32 par;
wdenk8bde7f72003-06-27 21:31:46 +0000388
wdenk7a8e9bed2003-05-31 18:35:21 +0000389 par = size;
390 if (par < 0x80000) {
391 par = 0x80000;
392 }
393 par >>= 16;
394 par--;
395 par&=0x7ff;
396 par <<= 14;
397 par |= (PCI_ROM_TEMP_SPACE>>16);
398 par |= 0x72000000;
wdenk8bde7f72003-06-27 21:31:46 +0000399
wdenk7a8e9bed2003-05-31 18:35:21 +0000400 PRINTF ("setting PAR1 to %x\n", par);
wdenk8bde7f72003-06-27 21:31:46 +0000401
wdenk7a8e9bed2003-05-31 18:35:21 +0000402 /* Map rom 0x10000 with PAR1 */
403 write_mmcr_long(SC520_PAR1, par);
wdenk8bde7f72003-06-27 21:31:46 +0000404
wdenk7a8e9bed2003-05-31 18:35:21 +0000405 return PCI_ROM_TEMP_SPACE;
406}
407
408/*
409 * this function removed any mapping created
410 * with pci_get_rom_window()
411 */
412void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
413{
414 PRINTF("pci_remove_rom_window: %x", addr);
415 if (addr == PCI_ROM_TEMP_SPACE) {
416 write_mmcr_long(SC520_PAR1, 0);
417 PRINTF(" done\n");
418 return;
419 }
420 PRINTF(" not ours\n");
wdenk8bde7f72003-06-27 21:31:46 +0000421
wdenk7a8e9bed2003-05-31 18:35:21 +0000422}
423
424/*
425 * This function is called in order to provide acces to the
wdenk8bde7f72003-06-27 21:31:46 +0000426 * legacy video I/O ports on the PCI bus.
427 * After this function accesses to I/O ports 0x3b0-0x3bb and
wdenk7a8e9bed2003-05-31 18:35:21 +0000428 * 0x3c0-0x3df shuld result in transactions on the PCI bus.
wdenk8bde7f72003-06-27 21:31:46 +0000429 *
wdenk7a8e9bed2003-05-31 18:35:21 +0000430 */
431int pci_enable_legacy_video_ports(struct pci_controller *hose)
432{
433 /* Map video memory to 0xa0000*/
434 write_mmcr_long(SC520_PAR0, 0x7200400a);
wdenk8bde7f72003-06-27 21:31:46 +0000435
wdenk7a8e9bed2003-05-31 18:35:21 +0000436 /* forward all I/O accesses to PCI */
wdenk8bde7f72003-06-27 21:31:46 +0000437 write_mmcr_byte(SC520_ADDDECCTL,
438 read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
439
440
wdenk7a8e9bed2003-05-31 18:35:21 +0000441 /* so we map away all io ports to pci (only way to access pci io
442 * below 0x400. But then we have to map back the portions that we dont
443 * use so that the generate cycles on the GPIO bus where the sio and
wdenk8bde7f72003-06-27 21:31:46 +0000444 * ISA slots are connected, this requre the use of several PAR registers
wdenk7a8e9bed2003-05-31 18:35:21 +0000445 */
wdenk8bde7f72003-06-27 21:31:46 +0000446
wdenk7a8e9bed2003-05-31 18:35:21 +0000447 /* bring 0x100 - 0x1ef back to ISA using PAR5 */
wdenk8bde7f72003-06-27 21:31:46 +0000448 write_mmcr_long(SC520_PAR5, 0x30ef0100);
449
wdenk7a8e9bed2003-05-31 18:35:21 +0000450 /* IDE use 1f0-1f7 */
wdenk8bde7f72003-06-27 21:31:46 +0000451
wdenk7a8e9bed2003-05-31 18:35:21 +0000452 /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
wdenk8bde7f72003-06-27 21:31:46 +0000453 write_mmcr_long(SC520_PAR6, 0x30ff01f8);
454
wdenk7a8e9bed2003-05-31 18:35:21 +0000455 /* com2 use 2f8-2ff */
wdenk8bde7f72003-06-27 21:31:46 +0000456
wdenk7a8e9bed2003-05-31 18:35:21 +0000457 /* bring 0x300 - 0x3af back to ISA using PAR7 */
wdenk8bde7f72003-06-27 21:31:46 +0000458 write_mmcr_long(SC520_PAR7, 0x30af0300);
459
wdenk7a8e9bed2003-05-31 18:35:21 +0000460 /* vga use 3b0-3bb */
wdenk8bde7f72003-06-27 21:31:46 +0000461
wdenk7a8e9bed2003-05-31 18:35:21 +0000462 /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
wdenk8bde7f72003-06-27 21:31:46 +0000463 write_mmcr_long(SC520_PAR8, 0x300303bc);
464
wdenk7a8e9bed2003-05-31 18:35:21 +0000465 /* vga use 3c0-3df */
wdenk8bde7f72003-06-27 21:31:46 +0000466
wdenk7a8e9bed2003-05-31 18:35:21 +0000467 /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
wdenk8bde7f72003-06-27 21:31:46 +0000468 write_mmcr_long(SC520_PAR9, 0x301503e0);
469
wdenk7a8e9bed2003-05-31 18:35:21 +0000470 /* ide use 3f6 */
wdenk8bde7f72003-06-27 21:31:46 +0000471
wdenk7a8e9bed2003-05-31 18:35:21 +0000472 /* bring 0x3f7 back to ISA using PAR10 */
wdenk8bde7f72003-06-27 21:31:46 +0000473 write_mmcr_long(SC520_PAR10, 0x300003f7);
474
475 /* com1 use 3f8-3ff */
wdenk7a8e9bed2003-05-31 18:35:21 +0000476
477 return 0;
478}
479#endif
480
wdenk2262cfe2002-11-18 00:14:45 +0000481/*
482 * Miscelaneous platform dependent initialisations
483 */
484
485int board_init(void)
486{
wdenk8bde7f72003-06-27 21:31:46 +0000487 init_sc520();
wdenk2262cfe2002-11-18 00:14:45 +0000488 bus_init();
489 irq_init();
wdenk8bde7f72003-06-27 21:31:46 +0000490
wdenk2262cfe2002-11-18 00:14:45 +0000491 /* max drive current on SDRAM */
492 write_mmcr_word(SC520_DSCTL, 0x0100);
wdenk8bde7f72003-06-27 21:31:46 +0000493
wdenk2262cfe2002-11-18 00:14:45 +0000494 /* enter debug mode after next reset (only if jumper is also set) */
495 write_mmcr_byte(SC520_RESCFG, 0x08);
wdenk2262cfe2002-11-18 00:14:45 +0000496 /* configure the software timer to 33.333MHz */
497 write_mmcr_byte(SC520_SWTMRCFG, 0);
498 gd->bus_clk = 33333000;
wdenk8bde7f72003-06-27 21:31:46 +0000499
wdenk2262cfe2002-11-18 00:14:45 +0000500 return 0;
501}
502
503int dram_init(void)
504{
505 init_sc520_dram();
506 return 0;
507}
508
509void show_boot_progress(int val)
510{
Heiko Schocher566a4942007-06-22 19:11:54 +0200511 if (val < -32) val = -1; /* let things compatible */
wdenk2262cfe2002-11-18 00:14:45 +0000512 outb(val&0xff, 0x80);
513 outb((val&0xff00)>>8, 0x680);
514}
515
516
517int last_stage_init(void)
518{
519 int minor;
520 int major;
wdenk8bde7f72003-06-27 21:31:46 +0000521
wdenk2262cfe2002-11-18 00:14:45 +0000522 major = minor = 0;
523 major |= ali512x_cio_in(23)?2:0;
524 major |= ali512x_cio_in(22)?1:0;
525 minor |= ali512x_cio_in(21)?2:0;
526 minor |= ali512x_cio_in(20)?1:0;
wdenk8bde7f72003-06-27 21:31:46 +0000527
wdenk2262cfe2002-11-18 00:14:45 +0000528 printf("AMD SC520 CDP revision %d.%d\n", major, minor);
wdenk8bde7f72003-06-27 21:31:46 +0000529
wdenkea909b72002-11-21 23:11:29 +0000530 return 0;
wdenk2262cfe2002-11-18 00:14:45 +0000531}
wdenk7a8e9bed2003-05-31 18:35:21 +0000532
533
wdenk8bde7f72003-06-27 21:31:46 +0000534void ssi_chip_select(int dev)
wdenk7a8e9bed2003-05-31 18:35:21 +0000535{
wdenk8bde7f72003-06-27 21:31:46 +0000536
wdenk7a8e9bed2003-05-31 18:35:21 +0000537 /* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */
538 switch (dev) {
539 case 1: /* SPI EEPROM */
540 ali512x_cio_out(16, 0);
541 break;
wdenk8bde7f72003-06-27 21:31:46 +0000542
wdenk7a8e9bed2003-05-31 18:35:21 +0000543 case 2: /* MW EEPROM */
544 ali512x_cio_out(15, 1);
545 break;
wdenk8bde7f72003-06-27 21:31:46 +0000546
547 case 3: /* AUX */
wdenk7a8e9bed2003-05-31 18:35:21 +0000548 ali512x_cio_out(14, 1);
549 break;
wdenk8bde7f72003-06-27 21:31:46 +0000550
wdenk7a8e9bed2003-05-31 18:35:21 +0000551 case 0:
552 ali512x_cio_out(16, 1);
553 ali512x_cio_out(15, 0);
554 ali512x_cio_out(14, 0);
555 break;
wdenk8bde7f72003-06-27 21:31:46 +0000556
wdenk7a8e9bed2003-05-31 18:35:21 +0000557 default:
558 printf("Illegal SSI device requested: %d\n", dev);
559 }
560}
561
wdenkbdccc4f2003-08-05 17:43:17 +0000562void spi_eeprom_probe(int x)
563{
564}
565
566int spi_eeprom_read(int x, int offset, char *buffer, int len)
567{
568 return 0;
569}
570
571int spi_eeprom_write(int x, int offset, char *buffer, int len)
572{
573 return 0;
574}
wdenk7a8e9bed2003-05-31 18:35:21 +0000575
wdenk8bde7f72003-06-27 21:31:46 +0000576void spi_init_f(void)
wdenk7a8e9bed2003-05-31 18:35:21 +0000577{
578#ifdef CONFIG_SC520_CDP_USE_SPI
wdenk8bde7f72003-06-27 21:31:46 +0000579 spi_eeprom_probe(1);
580#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000581#ifdef CONFIG_SC520_CDP_USE_MW
582 mw_eeprom_probe(2);
wdenk8bde7f72003-06-27 21:31:46 +0000583#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000584}
585
wdenk8bde7f72003-06-27 21:31:46 +0000586ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
wdenk7a8e9bed2003-05-31 18:35:21 +0000587{
588 int offset;
589 int i;
590 ssize_t res;
wdenk8bde7f72003-06-27 21:31:46 +0000591
wdenk7a8e9bed2003-05-31 18:35:21 +0000592 offset = 0;
593 for (i=0;i<alen;i++) {
594 offset <<= 8;
595 offset |= addr[i];
596 }
wdenk8bde7f72003-06-27 21:31:46 +0000597
wdenk7a8e9bed2003-05-31 18:35:21 +0000598#ifdef CONFIG_SC520_CDP_USE_SPI
wdenk8bde7f72003-06-27 21:31:46 +0000599 res = spi_eeprom_read(1, offset, buffer, len);
600#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000601#ifdef CONFIG_SC520_CDP_USE_MW
602 res = mw_eeprom_read(2, offset, buffer, len);
wdenk8bde7f72003-06-27 21:31:46 +0000603#endif
wdenkbdccc4f2003-08-05 17:43:17 +0000604#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
605 res = 0;
606#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000607 return res;
608}
609
wdenk8bde7f72003-06-27 21:31:46 +0000610ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
wdenk7a8e9bed2003-05-31 18:35:21 +0000611{
612 int offset;
613 int i;
614 ssize_t res;
wdenk8bde7f72003-06-27 21:31:46 +0000615
wdenk7a8e9bed2003-05-31 18:35:21 +0000616 offset = 0;
617 for (i=0;i<alen;i++) {
618 offset <<= 8;
619 offset |= addr[i];
620 }
wdenk8bde7f72003-06-27 21:31:46 +0000621
wdenk7a8e9bed2003-05-31 18:35:21 +0000622#ifdef CONFIG_SC520_CDP_USE_SPI
623 res = spi_eeprom_write(1, offset, buffer, len);
wdenk8bde7f72003-06-27 21:31:46 +0000624#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000625#ifdef CONFIG_SC520_CDP_USE_MW
626 res = mw_eeprom_write(2, offset, buffer, len);
wdenk8bde7f72003-06-27 21:31:46 +0000627#endif
wdenkbdccc4f2003-08-05 17:43:17 +0000628#if !defined(CONFIG_SC520_CDP_USE_SPI) && !defined(CONFIG_SC520_CDP_USE_MW)
629 res = 0;
630#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000631 return res;
632}
Ben Warrene3090532008-08-31 10:08:43 -0700633
634int board_eth_init(bd_t *bis)
635{
636 return pci_eth_init(bis);
637}