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wdenk3a473b22004-01-03 00:43:19 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28/*************************************************************************
29 * (c) 2002 Datentechnik AG - Project: Dino
30 *
31 *
32 * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $
33 *
34 ************************************************************************/
35
36/*************************************************************************
37 *
38 * History:
39 *
40 * $Log: DB64360.h,v $
41 * Revision 1.3 2003/04/26 04:58:13 brad
42 * Cosmetic changes and compiler warning cleanups
43 *
44 * Revision 1.2 2003/04/23 15:48:15 ingo
45 * mem. map output added
46 *
47 * Revision 1.1 2003/04/17 09:31:42 ias
48 * keymile changes 17_04_2003
49 *
50 * Revision 1.10 2003/03/06 12:25:04 ias
51 * 750 FX CPU HID settings updated
52 *
53 * Revision 1.9 2003/03/03 16:14:36 ias
54 * cleanup compiler warnings of printf fuctions
55 *
56 * Revision 1.8 2003/03/03 15:11:44 ias
57 * Marvell MPSC-UART is working
58 *
59 * Revision 1.7 2003/02/26 12:15:45 ssu
60 * adapted default parameters to new board flash address
61 *
62 * Revision 1.6 2003/02/25 14:55:42 ssu
63 * changed default environment parameters
64 *
65 * Revision 1.5 2003/02/21 17:14:23 ias
66 * added extended SPD handling
67 *
68 * Revision 1.4 2003/01/14 09:16:08 ias
69 * PPCBoot for Marvel Beta 0.9
70 *
71 * Revision 1.3 2002/12/03 13:56:26 ias
72 * Environment in flash support added
73 *
74 * Revision 1.2 2002/11/29 16:53:29 ias
75 * Flash support for STM added
76 *
77 * Revision 1.1 2002/11/29 13:36:31 ias
78 * Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board
79 * - working DDRRAM (only 32MByte of 128MB Modul)
80 * - working I2C Driver for SPD EEPROM read
81 * - working DUART 16650 for Serial Console
82 * - working "console"
83 *
84 *
85 *
86 ************************************************************************/
87
88#ifndef __CONFIG_H
89#define __CONFIG_H
90
91#include <asm/processor.h>
92
93/* This define must be before the core.h include */
94#define CONFIG_DB64360 1 /* this is an DB64360 board */
95
96#ifndef __ASSEMBLY__
97#include "../board/Marvell/include/core.h"
98#endif
99
100/*-----------------------------------------------------*/
101/* #include "../board/db64360/local.h" */
102#ifndef __LOCAL_H
103#define __LOCAL_H
104
105/* first ethernet */
106#define CONFIG_ETHADDR 64:36:00:00:00:01
107 /* next two ethernet hwaddrs */
wdenke2ffd592004-12-31 09:32:47 +0000108#define CONFIG_HAS_ETH1
wdenk3a473b22004-01-03 00:43:19 +0000109#define CONFIG_ETH1ADDR 64:36:00:00:00:02
110/* in the atlantis 64360 we have only 2 ETH port on the board,
111if we use PCI it has its own MAC addr */
112
113#define CONFIG_ENV_OVERWRITE
114#endif /* __CONFIG_H */
115
116/*
117 * High Level Configuration Options
118 * (easy to change)
119 */
120
121#define CONFIG_74xx /* we have a 750FX (override local.h) */
122
123#define CONFIG_DB64360 1 /* this is an DB64360 board */
124
125#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
126/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
127 DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
128 so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
129 see sdram_init.c */
130#undef CONFIG_ECC /* enable ECC support */
131#define CONFIG_MV64360_ECC
132
133/* which initialization functions to call for this board */
134#define CONFIG_MISC_INIT_R /* initialize the icache L1 */
wdenkc837dcb2004-01-20 23:12:12 +0000135#define CONFIG_BOARD_EARLY_INIT_F
wdenk3a473b22004-01-03 00:43:19 +0000136
137#define CFG_BOARD_NAME "DB64360"
138#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)"
139
140/*#define CFG_HUSH_PARSER */
141#undef CFG_HUSH_PARSER
142
143#define CFG_PROMPT_HUSH_PS2 "> "
144
145/*
146 * The following defines let you select what serial you want to use
147 * for your console driver.
148 *
149 * what to do:
150 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
151 * cable onto the second DUART channel, change the CFG_DUART port from 1
152 * to 0 below.
153 *
154 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
155 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
156 */
157
158#define CONFIG_MPSC_PORT 0
159
160/* to change the default ethernet port, use this define (options: 0, 1, 2) */
161#define CONFIG_NET_MULTI
162#define MV_ETH_DEVS 2
163
164/* #undef CONFIG_ETHER_PORT_MII */
165#if 0
166#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
167#else
168#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
169#endif
170#define CONFIG_ZERO_BOOTDELAY_CHECK
171
172
173#undef CONFIG_BOOTARGS
174/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
175
176/* ronen - autoboot using tftp */
177#if (CONFIG_BOOTDELAY >= 0)
178#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
179 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
180 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
181
182#define CONFIG_BOOTARGS "console=ttyS0,115200"
183
184#endif
185
186/* ronen - the u-boot.bin should be ~0x30000 bytes */
187#define CONFIG_EXTRA_ENV_SETTINGS \
188 "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
189cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
190 "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
191cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
192 "bootargs_root=root=/dev/nfs rw\0" \
193 "bootargs_end=:::DB64360:eth0:none \0"\
194 "ethprime=mv_enet0\0"\
195 "standalone=fsload 0x400000 uImage;setenv bootargs $(bootargs) root=/dev/mtdblock/0 rw \
196ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000;\0"
197
198/* --------------------------------------------------------------------------------------------------------------- */
199/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
200
201#define CONFIG_IPADDR 10.2.40.90
202
203#define CONFIG_SERIAL "No. 1"
204#define CONFIG_SERVERIP 10.2.1.126
205#define CONFIG_ROOTPATH /mnt/yellow_dog_mini
206
207
208#define CONFIG_TESTDRAMDATA y
209#define CONFIG_TESTDRAMADDRESS n
210#define CONFIG_TESETDRAMWALK n
211
212/* --------------------------------------------------------------------------------------------------------------- */
213
214#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
215#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
216
217#undef CONFIG_WATCHDOG /* watchdog disabled */
218#undef CONFIG_ALTIVEC /* undef to disable */
219
220#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
221 CONFIG_BOOTP_BOOTFILESIZE)
222
223/* Flash banks JFFS2 should use */
224#define CFG_JFFS2_FIRST_BANK 1
225#define CFG_JFFS2_NUM_BANKS 1
226
227#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
228 | CFG_CMD_ASKENV \
229 | CFG_CMD_I2C \
230 | CFG_CMD_EEPROM \
231 | CFG_CMD_CACHE \
232 | CFG_CMD_JFFS2 \
233 | CFG_CMD_PCI \
234 | CFG_CMD_NET )
235
236/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
237#include <cmd_confdefs.h>
238
239/*
240 * Miscellaneous configurable options
241 */
242#define CFG_I2C_EEPROM_ADDR_LEN 1
243#define CFG_I2C_MULTI_EEPROMS
244#define CFG_I2C_SPEED 40000 /* I2C speed default */
245
246/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
247#define CFG_LONGHELP /* undef to save memory */
248#define CFG_PROMPT "=> " /* Monitor Command Prompt */
249#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
250#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
251#else
252#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
253#endif
254#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
255#define CFG_MAXARGS 16 /* max number of command args */
256#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
257
258/*#define CFG_MEMTEST_START 0x00400000 memtest works on */
259/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
260/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
261
262/*
263#define CFG_DRAM_TEST
264 * DRAM tests
265 * CFG_DRAM_TEST - enables the following tests.
266 *
267 * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
268 * Environment variable 'test_dram_data' must be
269 * set to 'y'.
270 * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
271 * addressable. Environment variable
272 * 'test_dram_address' must be set to 'y'.
273 * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
274 * This test takes about 6 minutes to test 64 MB.
275 * Environment variable 'test_dram_walk' must be
276 * set to 'y'.
277 */
278#define CFG_DRAM_TEST
279#if defined(CFG_DRAM_TEST)
280#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
281/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
282#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
283#define CFG_DRAM_TEST_DATA
284#define CFG_DRAM_TEST_ADDRESS
285#define CFG_DRAM_TEST_WALK
286#endif /* CFG_DRAM_TEST */
287
288#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
289#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
290
291#define CFG_LOAD_ADDR 0x00400000 /* default load address */
292
293#define CFG_HZ 1000 /* decr freq: 1ms ticks */
294/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
295#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
296#define CFG_BUS_CLK CFG_BUS_HZ
297
298#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
299#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
300
301/*ronen - this is the Tclk (MV64360 core) */
302#define CFG_TCLK 133000000
303
304
305#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
306
307#define CFG_750FX_HID0 0x8000c084
308#define CFG_750FX_HID1 0x54800000
309#define CFG_750FX_HID2 0x00000000
310
311/*
312 * Low Level Configuration Settings
313 * (address mappings, register initial values, etc.)
314 * You should know what you are doing if you make changes here.
315 */
316
317/*-----------------------------------------------------------------------
318 * Definitions for initial stack pointer and data area
319 */
320
321/*
322 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
323 * To an unused memory region. The stack will remain in cache until RAM
324 * is initialized
325*/
326#define CFG_INIT_RAM_LOCK
327#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */
328#define CFG_INIT_RAM_END 0x1000
329#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
330#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
331
332#define RELOCATE_INTERNAL_RAM_ADDR
333#ifdef RELOCATE_INTERNAL_RAM_ADDR
334 #define CFG_INTERNAL_RAM_ADDR 0xf8000000
335#endif
336
337/*-----------------------------------------------------------------------
338 * Start addresses for the final memory configuration
339 * (Set up by the startup code)
340 * Please note that CFG_SDRAM_BASE _must_ start at 0
341 */
342#define CFG_SDRAM_BASE 0x00000000
343/* Dummies for BAT 4-7 */
344#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
345#define CFG_SDRAM2_BASE 0x20000000
346#define CFG_SDRAM3_BASE 0x30000000
347#define CFG_SDRAM4_BASE 0x40000000
348#define CFG_FLASH_BASE 0xfff00000
349
350#define CFG_DFL_BOOTCS_BASE 0xff800000
351#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
352
353#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
354#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
355#define PCI0_IO_BASE_BOOTM 0xfd000000
356
357#define CFG_RESET_ADDRESS 0xfff00100
358#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
359#define CFG_MONITOR_BASE CFG_FLASH_BASE
360#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
361
362/* areas to map different things with the GT in physical space */
363#define CFG_DRAM_BANKS 4
364
365/* What to put in the bats. */
366#define CFG_MISC_REGION_BASE 0xf0000000
367
368/* Peripheral Device section */
369
370/*******************************************************/
371/* We have on the db64360 Board : */
372/* GT-Chipset Register Area */
373/* GT-Chipset internal SRAM 256k */
374/* SRAM on external device module */
375/* Real time clock on external device module */
376/* dobble UART on external device module */
377/* Data flash on external device module */
378/* Boot flash on external device module */
379/*******************************************************/
380#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
381#define CFG_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */
382
383/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
384#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
385#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */
386
387#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */
388#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
389#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
390#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */
391
392#define CFG_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */
393#define CFG_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */
394#define CFG_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */
395#define CFG_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */
396/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
397
398/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
399#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
400#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
401#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
402#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
403#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
404
405 /* c 4 a 8 2 4 1 c */
406 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
407 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
408 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
409 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
410
411
412/* ronen - update MPP Control MV64360*/
413#define CFG_MPP_CONTROL_0 0x02222222
414#define CFG_MPP_CONTROL_1 0x11333011
415#define CFG_MPP_CONTROL_2 0x40431111
416#define CFG_MPP_CONTROL_3 0x00000044
417
418/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
419
420
421# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
422 /* gpp[31] gpp[30] gpp[29] gpp[28] */
423 /* gpp[27] gpp[24]*/
424 /* gpp[19:14] */
425
426/* setup new config_value for MV64360 DDR-RAM !! */
427# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
428
429#define CFG_DUART_IO CFG_DEV2_SPACE
430#define CFG_DUART_CHAN 1 /* channel to use for console */
431#define CFG_INIT_CHAN1
432#define CFG_INIT_CHAN2
433
434#define SRAM_BASE CFG_DEV0_SPACE
435#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
436
437
438/*-----------------------------------------------------------------------
439 * PCI stuff
440 *-----------------------------------------------------------------------
441 */
442
443#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
444#define PCI_HOST_FORCE 1 /* configure as pci host */
445#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
446
447#define CONFIG_PCI /* include pci support */
448#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
449#define CONFIG_PCI_PNP /* do pci plug-and-play */
450#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
451
452/* PCI MEMORY MAP section */
453#define CFG_PCI0_MEM_BASE 0x80000000
454#define CFG_PCI0_MEM_SIZE _128M
455#define CFG_PCI1_MEM_BASE 0x88000000
456#define CFG_PCI1_MEM_SIZE _128M
457
458#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
459#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
460
461/* PCI I/O MAP section */
462#define CFG_PCI0_IO_BASE 0xfa000000
463#define CFG_PCI0_IO_SIZE _16M
464#define CFG_PCI1_IO_BASE 0xfb000000
465#define CFG_PCI1_IO_SIZE _16M
466
467#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
468#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
469#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
470#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
471
472#if defined (CONFIG_750CX)
473#define CFG_PCI_IDSEL 0x0
474#else
475#define CFG_PCI_IDSEL 0x30
476#endif
477/*----------------------------------------------------------------------
478 * Initial BAT mappings
479 */
480
481/* NOTES:
482 * 1) GUARDED and WRITE_THRU not allowed in IBATS
483 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
484 */
485
486/* SDRAM */
487#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
488#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
489#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
490#define CFG_DBAT0U CFG_IBAT0U
491
492/* init ram */
493#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
494#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
495#define CFG_DBAT1L CFG_IBAT1L
496#define CFG_DBAT1U CFG_IBAT1U
497
498/* PCI0, PCI1 in one BAT */
499#define CFG_IBAT2L BATL_NO_ACCESS
500#define CFG_IBAT2U CFG_DBAT2U
501#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
502#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
503
504/* GT regs, bootrom, all the devices, PCI I/O */
505#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
506#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
507#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
508#define CFG_DBAT3U CFG_IBAT3U
509
510/* I2C addresses for the two DIMM SPD chips */
511#define DIMM0_I2C_ADDR 0x56
512#define DIMM1_I2C_ADDR 0x54
513
514/*
515 * For booting Linux, the board info and command line data
516 * have to be in the first 8 MB of memory, since this is
517 * the maximum mapped by the Linux kernel during initialization.
518 */
519#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
520
521/*-----------------------------------------------------------------------
522 * FLASH organization
523 */
524#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
525#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
526
527#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
528#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */
529#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */
530
531#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
532#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
533#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
534#define CFG_FLASH_CFI 1
535
536#define CFG_ENV_IS_IN_FLASH 1
537#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
538#define CFG_ENV_SECT_SIZE 0x10000
539#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
540/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
541
542/*-----------------------------------------------------------------------
543 * Cache Configuration
544 */
545#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
546#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
547#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
548#endif
549
550/*-----------------------------------------------------------------------
551 * L2CR setup -- make sure this is right for your board!
552 * look in include/mpc74xx.h for the defines used here
553 */
554
555#define CFG_L2
556
557
558#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
559#define L2_INIT 0
560#else
561
562#define L2_INIT 0
563/*
564#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
565 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
566*/
567#endif
568
569#define L2_ENABLE (L2_INIT | L2CR_L2E)
570
571/*
572 * Internal Definitions
573 *
574 * Boot Flags
575 */
576#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
577#define BOOTFLAG_WARM 0x02 /* Software reboot */
578
579#define CFG_BOARD_ASM_INIT 1
580
581#endif /* __CONFIG_H */