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wdenkfabd46a2004-07-10 23:11:10 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the CERF250 board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenkfabd46a2004-07-10 23:11:10 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
38#define CONFIG_CERF250 1 /* on Cerf PXA Board */
39#define BOARD_LATE_INIT 1
40#define CONFIG_BAUDRATE 38400
Marek Vasutcaeb8c02010-10-20 18:56:41 +020041#define CONFIG_SYS_TEXT_BASE 0x0
wdenkfabd46a2004-07-10 23:11:10 +000042
Wolfgang Denk53677ef2008-05-20 16:00:29 +020043#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
wdenkfabd46a2004-07-10 23:11:10 +000044
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020045/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000046#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020047
wdenkfabd46a2004-07-10 23:11:10 +000048/*
49 * Size of malloc() pool
50 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenkfabd46a2004-07-10 23:11:10 +000052
53/*
54 * Hardware drivers
55 */
Ben Warren7194ab82009-10-04 22:37:03 -070056#define CONFIG_SMC91111
wdenkfabd46a2004-07-10 23:11:10 +000057#define CONFIG_SMC91111_BASE 0x04000300
58#define CONFIG_SMC_USE_32_BIT
59
60/*
61 * select serial console configuration
62 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020063#define CONFIG_PXA_SERIAL
wdenkfabd46a2004-07-10 23:11:10 +000064#define CONFIG_FFUART 1 /* we use FFUART on CERF PXA */
65
66/* allow to overwrite serial and ethaddr */
67#define CONFIG_ENV_OVERWRITE
wdenkfabd46a2004-07-10 23:11:10 +000068
Jon Loeliger37e4f242007-07-04 22:31:56 -050069/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050070 * BOOTP options
71 */
72#define CONFIG_BOOTP_BOOTFILESIZE
73#define CONFIG_BOOTP_BOOTPATH
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76
77
78/*
Jon Loeliger37e4f242007-07-04 22:31:56 -050079 * Command line configuration.
80 */
81#include <config_cmd_default.h>
82
wdenkfabd46a2004-07-10 23:11:10 +000083
84#define CONFIG_BOOTDELAY 3
85#define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2
86#define CONFIG_NETMASK 255.255.255.0
87#define CONFIG_IPADDR 192.168.0.5
88#define CONFIG_SERVERIP 192.168.0.2
89#define CONFIG_BOOTCOMMAND "bootm 0xC0000"
90#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
91#define CONFIG_CMDLINE_TAG
92
Jon Loeliger37e4f242007-07-04 22:31:56 -050093#if defined(CONFIG_CMD_KGDB)
wdenkfabd46a2004-07-10 23:11:10 +000094#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
95#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
96#endif
97
98/*
99 * Miscellaneous configurable options
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_HUSH_PARSER 1
102#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkfabd46a2004-07-10 23:11:10 +0000103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_LONGHELP /* undef to save memory */
105#ifdef CONFIG_SYS_HUSH_PARSER
106#define CONFIG_SYS_PROMPT "uboot$ " /* Monitor Command Prompt */
wdenkfabd46a2004-07-10 23:11:10 +0000107#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkfabd46a2004-07-10 23:11:10 +0000109#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
111#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
wdenkfabd46a2004-07-10 23:11:10 +0000112 /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
114#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
115#define CONFIG_SYS_DEVICE_NULLDEV 1
wdenkfabd46a2004-07-10 23:11:10 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
118#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenkfabd46a2004-07-10 23:11:10 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
wdenkfabd46a2004-07-10 23:11:10 +0000121
Micha Kalfon94a33122009-02-11 19:50:11 +0200122#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */
wdenkfabd46a2004-07-10 23:11:10 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkfabd46a2004-07-10 23:11:10 +0000126
127
128/*
129 * Stack sizes
130 *
131 * The stack sizes are set up in start.S using the settings below
132 */
133#define CONFIG_STACKSIZE (128*1024) /* regular stack */
134#ifdef CONFIG_USE_IRQ
135#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
136#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
137#endif
138
139/*
140 * Physical Memory Map
141 */
Marek Vasutcaeb8c02010-10-20 18:56:41 +0200142#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200143#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
144#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
wdenkfabd46a2004-07-10 23:11:10 +0000145
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200146#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
147#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
148#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
149#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
150#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
wdenkfabd46a2004-07-10 23:11:10 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_DRAM_BASE 0xa0000000
153#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenkfabd46a2004-07-10 23:11:10 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenkfabd46a2004-07-10 23:11:10 +0000156
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200157#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200158#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200159
wdenkfabd46a2004-07-10 23:11:10 +0000160/*
161 * GPIO settings
162 */
163
164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_GPSR0_VAL 0x00408030
166#define CONFIG_SYS_GPSR1_VAL 0x00BFA882
167#define CONFIG_SYS_GPSR2_VAL 0x0001C000
168#define CONFIG_SYS_GPCR0_VAL 0xC0031100
169#define CONFIG_SYS_GPCR1_VAL 0xFC400300
170#define CONFIG_SYS_GPCR2_VAL 0x00003FFF
171#define CONFIG_SYS_GPDR0_VAL 0xC0439330
172#define CONFIG_SYS_GPDR1_VAL 0xFCFFAB82
173#define CONFIG_SYS_GPDR2_VAL 0x0001FFFF
174#define CONFIG_SYS_GAFR0_L_VAL 0x80000000
175#define CONFIG_SYS_GAFR0_U_VAL 0xA5000010
176#define CONFIG_SYS_GAFR1_L_VAL 0x60008018
177#define CONFIG_SYS_GAFR1_U_VAL 0xAAA5AAAA
178#define CONFIG_SYS_GAFR2_L_VAL 0xAAA0000A
179#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenkfabd46a2004-07-10 23:11:10 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_PSSR_VAL 0x20
wdenkfabd46a2004-07-10 23:11:10 +0000182
Marek Vasutcaeb8c02010-10-20 18:56:41 +0200183#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
184#define CONFIG_SYS_CKEN 0x0
185
wdenkfabd46a2004-07-10 23:11:10 +0000186/*
187 * Memory settings
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MSC0_VAL 0x12447FF0
190#define CONFIG_SYS_MSC1_VAL 0x12BC5554
191#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1
192#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
193#define CONFIG_SYS_MDREFR_VAL 0x03CDC017
194#define CONFIG_SYS_MDMRS_VAL 0x00000000
Marek Vasutcaeb8c02010-10-20 18:56:41 +0200195#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
196#define CONFIG_SYS_SXCNFG_VAL 0x00000000
wdenkfabd46a2004-07-10 23:11:10 +0000197
198/*
199 * PCMCIA and CF Interfaces
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_MECR_VAL 0x00000000
202#define CONFIG_SYS_MCMEM0_VAL 0x00010504
203#define CONFIG_SYS_MCMEM1_VAL 0x00010504
204#define CONFIG_SYS_MCATT0_VAL 0x00010504
205#define CONFIG_SYS_MCATT1_VAL 0x00010504
206#define CONFIG_SYS_MCIO0_VAL 0x00004715
207#define CONFIG_SYS_MCIO1_VAL 0x00004715
wdenkfabd46a2004-07-10 23:11:10 +0000208
209#define _LED 0x08000010 /*check this */
210#define LED_BLANK 0x08000040
211#define LED_GPIO 0x10
212
213/*
214 * FLASH and environment organization
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
217#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkfabd46a2004-07-10 23:11:10 +0000218
219/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
221#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenkfabd46a2004-07-10 23:11:10 +0000222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_MONITOR_LEN 0x40000 /* 256 KiB */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200224#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200226#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
wdenkfabd46a2004-07-10 23:11:10 +0000227
228
229#endif /* __CONFIG_H */