Blame - arch/arm/cpu/tegra30-common/pinmux.c - github/trini/u-boot

Tom Warren

b287103

2012-12-11 13:34:15 +0000

[diff] [blame]

1

/*

Tom Warren

8ca79b2

2013-03-06 16:16:22 -0700

[diff] [blame]

2

Tom Warren

b287103

2012-12-11 13:34:15 +0000

[diff] [blame]

3

*

4

* This program is free software; you can redistribute it and/or modify it

5

* under the terms and conditions of the GNU General Public License,

6

* version 2, as published by the Free Software Foundation.

7

*

8

* This program is distributed in the hope it will be useful, but WITHOUT

9

* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

10

* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for

11

* more details.

12

*

13

* You should have received a copy of the GNU General Public License

14

* along with this program. If not, see <http://www.gnu.org/licenses/>.

15

*/

16

17

/* Tegra30 pin multiplexing functions */

18

19

#include <common.h>

20

#include <asm/io.h>

Tom Warren

b287103

2012-12-11 13:34:15 +0000

[diff] [blame]

21

#include <asm/arch/pinmux.h>

22

Tom Warren

b287103

2012-12-11 13:34:15 +0000

[diff] [blame]

23

/* Convenient macro for defining pin group properties */

Stephen Warren

e296995

2014-03-21 12:28:54 -0600

[diff] [blame^]

24

#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \

Tom Warren

b287103

2012-12-11 13:34:15 +0000

[diff] [blame]

25

{ \

Tom Warren

b287103

2012-12-11 13:34:15 +0000

[diff] [blame]

.funcs = { \

PMUX_FUNC_ ## f0, \

PMUX_FUNC_ ## f1, \

PMUX_FUNC_ ## f2, \

PMUX_FUNC_ ## f3, \

}, \

Tom Warren

b287103

2012-12-11 13:34:15 +0000

[diff] [blame]

32

}

33

34

/* Input and output pins */

35

#define PINI(pg_name, vdd, f0, f1, f2, f3) \

36

PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)

37

#define PINO(pg_name, vdd, f0, f1, f2, f3) \

38

PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)

39

Stephen Warren

e296995

2014-03-21 12:28:54 -0600

[diff] [blame^]

40

static const struct tegra_pingroup_desc tegra30_pingroups[PINGRP_COUNT] = {

Tom Warren

b287103

2012-12-11 13:34:15 +0000

[diff] [blame]

41

/* NAME VDD f0 f1 f2 f3 */

42

PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),

43

PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),

44

PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),

45

PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),

46

PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),

47

PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),

48

PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),

49

PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),

50

PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI),

51

PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI),

52

PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI),

53

PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI),

54

PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB),

55

PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB),

56

PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB),

57

PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB),

58

PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4),

59

PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),

60

PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),

61

PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),

62

PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),

63

PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),

64

PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),

65

PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),

66

PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4),

67

PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),

68

PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),

69

PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),

70

PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4),

71

PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP),

72

PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4),

73

PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP),

74

PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP),

75

PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4),

76

PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4),

77

PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP),

78

PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP),

79

PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4),

80

PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4),

81

PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),

82

PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),

83

PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4),

84

PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4),

85

PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4),

86

PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4),

87

PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4),

88

PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4),

89

PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4),

90

PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4),

91

PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4),

92

PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4),

93

PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4),

94

PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4),

95

PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4),

96

PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4),

97

PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4),

98

PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4),

99

PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4),

100

PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4),

101

PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4),

102

PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4),

103

PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4),

104

PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4),

105

PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4),

106

PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4),

107

PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4),

108

PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4),

109

PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4),

110

PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4),

111

PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),

112

PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),

113

PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),

114

PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),

115

PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4),

116

PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4),

117

PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4),

118

PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4),

119

PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4),

120

PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4),

121

PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4),

122

PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4),

123

PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4),

124

PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4),

125

PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4),

126

PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4),

127

PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4),

128

PINI(VI_MCLK, VI, VI, VI, VI, VI),

129

PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4),

130

PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4),

131

PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),

132

PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),

133

PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4),

134

PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4),

135

PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4),

136

PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4),

137

PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4),

138

PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4),

139

PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4),

140

PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4),

141

PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4),

142

PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4),

143

PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4),

144

PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4),

145

PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4),

146

PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),

147

PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),

148

PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4),

149

PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4),

150

PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4),

151

PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4),

152

PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),

153

PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),

154

PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),

155

PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4),

156

PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4),

157

PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4),

158

PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4),

159

PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV),

160

PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV),

161

PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4),

162

PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT),

163

PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4),

164

PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA),

165

PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT),

166

PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),

167

PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),

168

PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),

169

PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),

170

PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),

171

PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4),

172

PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4),

173

PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4),

174

PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4),

175

PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4),

176

PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4),

177

PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4),

178

PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4),

179

PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4),

180

PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4),

181

PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4),

182

PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT),

183

PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV),

184

PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV),

185

PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4),

186

PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4),

187

PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4),

188

PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4),

189

PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),

190

PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4),

191

PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4),

192

PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4),

193

PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4),

194

PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4),

195

PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4),

196

PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4),

197

PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4),

198

PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4),

199

PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4),

200

PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4),

201

PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4),

202

PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4),

203

PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4),

204

PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4),

205

PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4),

206

PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4),

207

PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4),

208

PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4),

209

PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4),

210

PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4),

211

PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4),

212

PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4),

213

PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),

214

PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),

215

PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),

216

PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),

217

PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4),

218

PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4),

219

PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4),

220

PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4),

221

PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4),

222

PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR),

223

PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO),

224

PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO),

225

PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO),

226

PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO),

227

PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO),

228

PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO),

229

PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO),

230

PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO),

231

PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO),

232

PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO),

233

PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST),

234

PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST),

235

PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4),

236

PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4),

237

PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4),

238

PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4),

239

PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO),

240

PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO),

241

PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4),

242

PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),

243

PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),

244

PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),

245

PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4),

246

PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4),

247

PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4),

248

PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2),

249

PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2),

250

PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2),

251

PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2),

252

PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4),

253

PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4),

254

PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2),

255

PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2),

256

PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI),

257

PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI),

258

PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI),

259

PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI),

260

PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI),

261

PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI),

262

PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI),

263

PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI),

264

PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),

265

PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),

266

PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),

267

PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4),

268

PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),

269

PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),

270

PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3),

271

PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2),

272

PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),

273

PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),

274

PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3),

275

PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3),

276

PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2),

277

PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2),

278

PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),

279

PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),

280

PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),

281

PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),

282

PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),

283

PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),

284

PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),

285

PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),

286

PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),

287

PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),

288

PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),

289

PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),

290

PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),

291

};

Stephen Warren

e296995

2014-03-21 12:28:54 -0600

[diff] [blame^]

292

const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra30_pingroups;