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Heiko Schocherac9db062008-01-11 01:12:08 +01001/*
Heiko Schocher0809ea22008-10-15 09:34:05 +02002 * (C) Copyright 2007 - 2008
Heiko Schocherac9db062008-01-11 01:12:08 +01003 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocherac9db062008-01-11 01:12:08 +01006 */
7
8#include <common.h>
9#include <mpc8260.h>
10#include <ioports.h>
Heiko Schocher9661bf92008-10-15 09:36:03 +020011#include <malloc.h>
Heiko Schocher9e299192008-10-17 12:15:55 +020012#include <asm/io.h>
Heiko Schocherac9db062008-01-11 01:12:08 +010013
14#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
15#include <libfdt.h>
16#endif
17
Heiko Schocher9661bf92008-10-15 09:36:03 +020018#include <i2c.h>
Heiko Schocher210c8c02008-11-21 08:29:40 +010019#include "../common/common.h"
20
Heiko Schocherac9db062008-01-11 01:12:08 +010021/*
22 * I/O Port configuration table
23 *
24 * if conf is 1, then that port pin will be configured at boot time
25 * according to the five values podr/pdir/ppar/psor/pdat for that entry
26 */
27const iop_conf_t iop_conf_tab[4][32] = {
28
Holger Brunck2220e6c2011-04-08 02:47:25 +000029 /* Port A */
30 { /* conf ppar psor pdir podr pdat */
31 { 0, 0, 0, 0, 0, 0 }, /* PA31 */
32 { 0, 0, 0, 0, 0, 0 }, /* PA30 */
33 { 0, 0, 0, 0, 0, 0 }, /* PA29 */
34 { 0, 0, 0, 0, 0, 0 }, /* PA28 */
35 { 0, 0, 0, 0, 0, 0 }, /* PA27 */
36 { 0, 0, 0, 0, 0, 0 }, /* PA26 */
37 { 0, 0, 0, 0, 0, 0 }, /* PA25 */
38 { 0, 0, 0, 0, 0, 0 }, /* PA24 */
39 { 0, 0, 0, 0, 0, 0 }, /* PA23 */
40 { 0, 0, 0, 0, 0, 0 }, /* PA22 */
41 { 0, 0, 0, 0, 0, 0 }, /* PA21 */
42 { 0, 0, 0, 0, 0, 0 }, /* PA20 */
43 { 0, 0, 0, 0, 0, 0 }, /* PA19 */
44 { 0, 0, 0, 0, 0, 0 }, /* PA18 */
45 { 0, 0, 0, 0, 0, 0 }, /* PA17 */
46 { 0, 0, 0, 0, 0, 0 }, /* PA16 */
47 { 0, 0, 0, 0, 0, 0 }, /* PA15 */
48 { 0, 0, 0, 0, 0, 0 }, /* PA14 */
49 { 0, 0, 0, 0, 0, 0 }, /* PA13 */
50 { 0, 0, 0, 0, 0, 0 }, /* PA12 */
51 { 0, 0, 0, 0, 0, 0 }, /* PA11 */
52 { 0, 0, 0, 0, 0, 0 }, /* PA10 */
53 { 1, 1, 0, 1, 0, 0 }, /* PA9 SMC2 TxD */
54 { 1, 1, 0, 0, 0, 0 }, /* PA8 SMC2 RxD */
55 { 0, 0, 0, 0, 0, 0 }, /* PA7 */
56 { 0, 0, 0, 0, 0, 0 }, /* PA6 */
57 { 0, 0, 0, 0, 0, 0 }, /* PA5 */
58 { 0, 0, 0, 0, 0, 0 }, /* PA4 */
59 { 0, 0, 0, 0, 0, 0 }, /* PA3 */
60 { 0, 0, 0, 0, 0, 0 }, /* PA2 */
61 { 0, 0, 0, 0, 0, 0 }, /* PA1 */
62 { 0, 0, 0, 0, 0, 0 } /* PA0 */
63 },
Heiko Schocherac9db062008-01-11 01:12:08 +010064
Holger Brunck2220e6c2011-04-08 02:47:25 +000065 /* Port B */
66 { /* conf ppar psor pdir podr pdat */
67 { 0, 0, 0, 0, 0, 0 }, /* PB31 */
68 { 0, 0, 0, 0, 0, 0 }, /* PB30 */
69 { 0, 0, 0, 0, 0, 0 }, /* PB29 */
70 { 0, 0, 0, 0, 0, 0 }, /* PB28 */
71 { 0, 0, 0, 0, 0, 0 }, /* PB27 */
72 { 0, 0, 0, 0, 0, 0 }, /* PB26 */
73 { 0, 0, 0, 0, 0, 0 }, /* PB25 */
74 { 0, 0, 0, 0, 0, 0 }, /* PB24 */
75 { 0, 0, 0, 0, 0, 0 }, /* PB23 */
76 { 0, 0, 0, 0, 0, 0 }, /* PB22 */
77 { 0, 0, 0, 0, 0, 0 }, /* PB21 */
78 { 0, 0, 0, 0, 0, 0 }, /* PB20 */
79 { 0, 0, 0, 0, 0, 0 }, /* PB19 */
80 { 0, 0, 0, 0, 0, 0 }, /* PB18 */
81 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
82 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
83 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
84 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
85 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
86 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
87 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
88 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
89 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
90 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
91 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
92 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
93 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
94 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
95 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
96 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
97 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
98 { 0, 0, 0, 0, 0, 0 } /* non-existent */
99 },
Heiko Schocherac9db062008-01-11 01:12:08 +0100100
Holger Brunck2220e6c2011-04-08 02:47:25 +0000101 /* Port C */
102 { /* conf ppar psor pdir podr pdat */
103 { 0, 0, 0, 0, 0, 0 }, /* PC31 */
104 { 0, 0, 0, 0, 0, 0 }, /* PC30 */
105 { 0, 0, 0, 0, 0, 0 }, /* PC29 */
106 { 0, 0, 0, 0, 0, 0 }, /* PC28 */
107 { 0, 0, 0, 0, 0, 0 }, /* PC27 */
108 { 0, 0, 0, 0, 0, 0 }, /* PC26 */
109 { 1, 1, 0, 0, 0, 0 }, /* PC25 RxClk */
110 { 1, 1, 0, 0, 0, 0 }, /* PC24 TxClk */
111 { 0, 0, 0, 0, 0, 0 }, /* PC23 */
112 { 0, 0, 0, 0, 0, 0 }, /* PC22 */
113 { 0, 0, 0, 0, 0, 0 }, /* PC21 */
114 { 0, 0, 0, 0, 0, 0 }, /* PC20 */
115 { 0, 0, 0, 0, 0, 0 }, /* PC19 */
116 { 0, 0, 0, 0, 0, 0 }, /* PC18 */
117 { 0, 0, 0, 0, 0, 0 }, /* PC17 */
118 { 0, 0, 0, 0, 0, 0 }, /* PC16 */
119 { 0, 0, 0, 0, 0, 0 }, /* PC15 */
120 { 0, 0, 0, 0, 0, 0 }, /* PC14 */
121 { 0, 0, 0, 0, 0, 0 }, /* PC13 */
122 { 0, 0, 0, 0, 0, 0 }, /* PC12 */
123 { 0, 0, 0, 0, 0, 0 }, /* PC11 */
124 { 0, 0, 0, 0, 0, 0 }, /* PC10 */
125 { 1, 1, 0, 0, 0, 0 }, /* PC9 SCC4: CTS */
126 { 1, 1, 0, 0, 0, 0 }, /* PC8 SCC4: CD */
127 { 0, 0, 0, 0, 0, 0 }, /* PC7 */
128 { 0, 0, 0, 0, 0, 0 }, /* PC6 */
129 { 0, 0, 0, 0, 0, 0 }, /* PC5 */
130 { 0, 0, 0, 0, 0, 0 }, /* PC4 */
131 { 0, 0, 0, 0, 0, 0 }, /* PC3 */
132 { 0, 0, 0, 0, 0, 0 }, /* PC2 */
133 { 0, 0, 0, 0, 0, 0 }, /* PC1 */
134 { 0, 0, 0, 0, 0, 0 }, /* PC0 */
135 },
Heiko Schocherac9db062008-01-11 01:12:08 +0100136
Holger Brunck2220e6c2011-04-08 02:47:25 +0000137 /* Port D */
138 { /* conf ppar psor pdir podr pdat */
139 { 0, 0, 0, 0, 0, 0 }, /* PD31 */
140 { 0, 0, 0, 0, 0, 0 }, /* PD30 */
141 { 0, 0, 0, 0, 0, 0 }, /* PD29 */
142 { 0, 0, 0, 0, 0, 0 }, /* PD28 */
143 { 0, 0, 0, 0, 0, 0 }, /* PD27 */
144 { 0, 0, 0, 0, 0, 0 }, /* PD26 */
145 { 0, 0, 0, 0, 0, 0 }, /* PD25 */
146 { 0, 0, 0, 0, 0, 0 }, /* PD24 */
147 { 0, 0, 0, 0, 0, 0 }, /* PD23 */
148 { 1, 1, 0, 0, 0, 0 }, /* PD22 SCC4: RXD */
149 { 1, 1, 0, 1, 0, 0 }, /* PD21 SCC4: TXD */
150 { 1, 1, 0, 1, 0, 0 }, /* PD20 SCC4: RTS */
151 { 0, 0, 0, 0, 0, 0 }, /* PD19 */
152 { 0, 0, 0, 0, 0, 0 }, /* PD18 */
153 { 0, 0, 0, 0, 0, 0 }, /* PD17 */
154 { 0, 0, 0, 0, 0, 0 }, /* PD16 */
Heiko Schocher9661bf92008-10-15 09:36:03 +0200155#if defined(CONFIG_HARD_I2C)
Holger Brunck2220e6c2011-04-08 02:47:25 +0000156 { 1, 1, 1, 0, 1, 0 }, /* PD15 I2C SDA */
157 { 1, 1, 1, 0, 1, 0 }, /* PD14 I2C SCL */
Heiko Schocher9661bf92008-10-15 09:36:03 +0200158#else
Holger Brunck2220e6c2011-04-08 02:47:25 +0000159 { 1, 0, 0, 0, 1, 1 }, /* PD15 */
160 { 1, 0, 0, 1, 1, 1 }, /* PD14 */
Heiko Schocher9661bf92008-10-15 09:36:03 +0200161#endif
Holger Brunck2220e6c2011-04-08 02:47:25 +0000162 { 0, 0, 0, 0, 0, 0 }, /* PD13 */
163 { 0, 0, 0, 0, 0, 0 }, /* PD12 */
164 { 0, 0, 0, 0, 0, 0 }, /* PD11 */
165 { 0, 0, 0, 0, 0, 0 }, /* PD10 */
166 { 0, 0, 0, 0, 0, 0 }, /* PD9 */
167 { 0, 0, 0, 0, 0, 0 }, /* PD8 */
168 { 0, 0, 0, 0, 0, 0 }, /* PD7 */
169 { 0, 0, 0, 0, 0, 0 }, /* PD6 */
170 { 0, 0, 0, 0, 0, 0 }, /* PD5 */
171 { 0, 0, 0, 0, 0, 0 }, /* PD4 */
172 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
173 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
174 { 0, 0, 0, 0, 0, 0 }, /* non-existent */
175 { 0, 0, 0, 0, 0, 0 } /* non-existent */
176 }
Heiko Schocherac9db062008-01-11 01:12:08 +0100177};
178
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100179/*
180 * Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
Heiko Schocherac9db062008-01-11 01:12:08 +0100181 *
182 * This routine performs standard 8260 initialization sequence
183 * and calculates the available memory size. It may be called
184 * several times to try different SDRAM configurations on both
185 * 60x and local buses.
186 */
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100187static long int try_init(memctl8260_t *memctl, ulong sdmr,
188 ulong orx, uchar *base)
Heiko Schocherac9db062008-01-11 01:12:08 +0100189{
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100190 uchar c = 0xff;
Heiko Schocherac9db062008-01-11 01:12:08 +0100191 ulong maxsize, size;
192 int i;
193
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100194 /*
195 * We must be able to test a location outsize the maximum legal size
Heiko Schocherac9db062008-01-11 01:12:08 +0100196 * to find out THAT we are outside; but this address still has to be
197 * mapped by the controller. That means, that the initial mapping has
198 * to be (at least) twice as large as the maximum expected size.
199 */
200 maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
201
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100202 out_be32(&memctl->memc_or1, orx);
Heiko Schocherac9db062008-01-11 01:12:08 +0100203
204 /*
205 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
206 *
207 * "At system reset, initialization software must set up the
208 * programmable parameters in the memory controller banks registers
209 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
210 * system software should execute the following initialization sequence
211 * for each SDRAM device.
212 *
213 * 1. Issue a PRECHARGE-ALL-BANKS command
214 * 2. Issue eight CBR REFRESH commands
215 * 3. Issue a MODE-SET command to initialize the mode register
216 *
217 * The initial commands are executed by setting P/LSDMR[OP] and
218 * accessing the SDRAM with a single-byte transaction."
219 *
220 * The appropriate BRx/ORx registers have already been set when we
Holger Brunck2220e6c2011-04-08 02:47:25 +0000221 * get here. The SDRAM can be accessed at the address
222 * CONFIG_SYS_SDRAM_BASE.
Heiko Schocherac9db062008-01-11 01:12:08 +0100223 */
224
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100225 out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_PREA);
226 out_8(base, c);
Heiko Schocherac9db062008-01-11 01:12:08 +0100227
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100228 out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_CBRR);
Heiko Schocherac9db062008-01-11 01:12:08 +0100229 for (i = 0; i < 8; i++)
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100230 out_8(base, c);
Heiko Schocherac9db062008-01-11 01:12:08 +0100231
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100232 out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_MRW);
233 /* setting MR on address lines */
234 out_8((uchar *)(base + CONFIG_SYS_MRS_OFFS), c);
Heiko Schocherac9db062008-01-11 01:12:08 +0100235
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100236 out_be32(&memctl->memc_psdmr, sdmr | PSDMR_OP_NORM | PSDMR_RFEN);
237 out_8(base, c);
Heiko Schocherac9db062008-01-11 01:12:08 +0100238
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100239 size = get_ram_size((long *)base, maxsize);
240 out_be32(&memctl->memc_or1, orx | ~(size - 1));
Heiko Schocherac9db062008-01-11 01:12:08 +0100241
Holger Brunck2220e6c2011-04-08 02:47:25 +0000242 return size;
Heiko Schocherac9db062008-01-11 01:12:08 +0100243}
244
Gerlando Falauto3a532342012-07-27 05:16:38 +0000245#ifdef CONFIG_SYS_SDRAM_LIST
246
247/*
248 * If CONFIG_SYS_SDRAM_LIST is defined, we cycle through all SDRAM
249 * configurations therein (should be from high to lower) to find the
250 * one actually matching the current configuration.
251 * CONFIG_SYS_PSDMR and CONFIG_SYS_OR1 will contain the base values which are
252 * common among all possible configurations; values in CONFIG_SYS_SDRAM_LIST
253 * (defined as the initialization value for the array of struct sdram_conf_s)
254 * will then be ORed with such base values.
255 */
256
257struct sdram_conf_s {
258 ulong size;
259 int or1;
260 int psdmr;
261};
262
263static struct sdram_conf_s sdram_conf[] = CONFIG_SYS_SDRAM_LIST;
264
265static long probe_sdram(memctl8260_t *memctl)
266{
267 int n = 0;
268 long psize = 0;
269
270 for (n = 0; n < ARRAY_SIZE(sdram_conf); psize = 0, n++) {
271 psize = try_init(memctl,
272 CONFIG_SYS_PSDMR | sdram_conf[n].psdmr,
273 CONFIG_SYS_OR1 | sdram_conf[n].or1,
274 (uchar *) CONFIG_SYS_SDRAM_BASE);
275 debug("Probing %ld bytes returned %ld\n",
276 sdram_conf[n].size, psize);
277 if (psize == sdram_conf[n].size)
278 break;
279 }
280 return psize;
281}
282
283#else /* CONFIG_SYS_SDRAM_LIST */
284
285static long probe_sdram(memctl8260_t *memctl)
286{
287 return try_init(memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
288 (uchar *) CONFIG_SYS_SDRAM_BASE);
289}
290#endif /* CONFIG_SYS_SDRAM_LIST */
291
292
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100293phys_size_t initdram(int board_type)
Heiko Schocherac9db062008-01-11 01:12:08 +0100294{
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100295 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
296 memctl8260_t *memctl = &immap->im_memctl;
Heiko Schocherac9db062008-01-11 01:12:08 +0100297
298 long psize;
299
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100300 out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
301 out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
Heiko Schocherac9db062008-01-11 01:12:08 +0100302
Heiko Schocherac9db062008-01-11 01:12:08 +0100303 /* 60x SDRAM setup:
304 */
Gerlando Falauto3a532342012-07-27 05:16:38 +0000305 psize = probe_sdram(memctl);
Heiko Schocherac9db062008-01-11 01:12:08 +0100306
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100307 icache_enable();
Heiko Schocherac9db062008-01-11 01:12:08 +0100308
Holger Brunck2220e6c2011-04-08 02:47:25 +0000309 return psize;
Heiko Schocherac9db062008-01-11 01:12:08 +0100310}
311
312int checkboard(void)
313{
Heiko Schocheraf895e42011-02-22 08:58:19 +0100314#if defined(CONFIG_MGCOGE)
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100315 puts("Board: Keymile mgcoge");
Heiko Schocheraf895e42011-02-22 08:58:19 +0100316#else
Holger Brunck489337f2011-05-02 22:56:55 +0000317 puts("Board: Keymile mgcoge3ne");
Heiko Schocheraf895e42011-02-22 08:58:19 +0100318#endif
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100319 if (ethernet_present())
320 puts(" with PIGGY.");
321 puts("\n");
Heiko Schocherac9db062008-01-11 01:12:08 +0100322 return 0;
323}
324
Andreas Huber91a3c142011-01-25 11:26:15 +0100325int last_stage_init(void)
326{
Huber, Andreasf30c62b2011-05-02 22:56:54 +0000327 struct bfticu_iomap *base =
328 (struct bfticu_iomap *)CONFIG_SYS_FPGA_BASE;
Andreas Huber91a3c142011-01-25 11:26:15 +0100329 u8 dip_switch;
Huber, Andreasf30c62b2011-05-02 22:56:54 +0000330
331 dip_switch = in_8(&base->mswitch);
332 dip_switch &= BFTICU_DIPSWITCH_MASK;
Andreas Huber91a3c142011-01-25 11:26:15 +0100333 /* dip switch 'full reset' or 'db erase' */
334 if (dip_switch & 0x1 || dip_switch & 0x2) {
335 /* start bootloader */
336 puts("DIP: Enabled\n");
337 setenv("actual_bank", "0");
338 }
Heiko Schocherf1fef1d2010-04-26 13:07:28 +0200339 set_km_env();
Andreas Huber91a3c142011-01-25 11:26:15 +0100340 return 0;
341}
342
Holger Brunck489337f2011-05-02 22:56:55 +0000343#ifdef CONFIG_MGCOGE3NE
Holger Brunck1adfd9d2011-06-05 22:22:20 +0000344static void set_pin(int state, unsigned long mask);
345
Holger Brunck489337f2011-05-02 22:56:55 +0000346/*
347 * For mgcoge3ne boards, the mgcoge3un control is controlled from
348 * a GPIO line on the PPC CPU. If bobcatreset is set the line
349 * will toggle once what forces the mgocge3un part to restart
350 * immediately.
351 */
Holger Brunck47ce50e2013-01-18 00:28:16 +0000352static void handle_mgcoge3un_reset(void)
Holger Brunck489337f2011-05-02 22:56:55 +0000353{
354 char *bobcatreset = getenv("bobcatreset");
355 if (bobcatreset) {
356 if (strcmp(bobcatreset, "true") == 0) {
357 puts("Forcing bobcat reset\n");
358 set_pin(0, 0x00000004); /* clear PD29 to reset arm */
359 udelay(1000);
360 set_pin(1, 0x00000004);
361 } else
362 set_pin(1, 0x00000004); /* set PD29 to not reset arm */
363 }
364}
365#endif
366
Karlheinz Jerg1eb95eb2013-01-21 03:55:16 +0000367int ethernet_present(void)
368{
369 struct km_bec_fpga *base =
370 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
371
372 return in_8(&base->bprth) & PIGGY_PRESENT;
373}
374
Heiko Schochere492c902008-03-07 08:13:41 +0100375/*
376 * Early board initalization.
377 */
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100378int board_early_init_r(void)
Heiko Schochere492c902008-03-07 08:13:41 +0100379{
Heiko Schocher8ed74342011-03-08 10:47:39 +0100380 struct km_bec_fpga *base =
381 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100382
Heiko Schochere492c902008-03-07 08:13:41 +0100383 /* setup the UPIOx */
Heiko Schocher4897ee32010-01-07 08:55:50 +0100384 /* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100385 out_8(&base->oprth, (WRG_RESET | H_OPORTS_14 | WRG_LED));
Heiko Schocher4897ee32010-01-07 08:55:50 +0100386 /* SCC4 enable, halfduplex, FCC1 powerdown */
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100387 out_8(&base->oprtl, (H_OPORTS_SCC4_ENA | H_OPORTS_SCC4_FD_ENA |
388 H_OPORTS_FCC1_PW_DWN));
389
Holger Brunck489337f2011-05-02 22:56:55 +0000390#ifdef CONFIG_MGCOGE3NE
391 handle_mgcoge3un_reset();
392#endif
Heiko Schochere492c902008-03-07 08:13:41 +0100393 return 0;
394}
395
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100396int hush_init_var(void)
Heiko Schocher8f64da72008-10-15 09:41:00 +0200397{
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100398 ivm_read_eeprom();
Heiko Schocher8f64da72008-10-15 09:41:00 +0200399 return 0;
400}
401
Holger Brunck1adfd9d2011-06-05 22:22:20 +0000402#define SDA_MASK 0x00010000
403#define SCL_MASK 0x00020000
404
405static void set_pin(int state, unsigned long mask)
406{
407 ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
408
409 if (state)
410 setbits_be32(&iop->pdat, mask);
411 else
412 clrbits_be32(&iop->pdat, mask);
413
414 setbits_be32(&iop->pdir, mask);
415}
416
417static int get_pin(unsigned long mask)
418{
419 ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
420
421 clrbits_be32(&iop->pdir, mask);
422 return 0 != (in_be32(&iop->pdat) & mask);
423}
424
425void set_sda(int state)
426{
427 set_pin(state, SDA_MASK);
428}
429
430void set_scl(int state)
431{
432 set_pin(state, SCL_MASK);
433}
434
435int get_sda(void)
436{
437 return get_pin(SDA_MASK);
438}
439
440int get_scl(void)
441{
442 return get_pin(SCL_MASK);
443}
444
445#if defined(CONFIG_HARD_I2C)
446static void setports(int gpio)
447{
448 ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
449
450 if (gpio) {
451 clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
452 clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
453 } else {
454 setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
455 clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
456 setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
457 }
458}
459#endif
Heiko Schocherac9db062008-01-11 01:12:08 +0100460#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
Simon Glasse895a4b2014-10-23 18:58:47 -0600461int ft_board_setup(void *blob, bd_t *bd)
Heiko Schocherac9db062008-01-11 01:12:08 +0100462{
Heiko Schocherb11f53f2011-03-15 16:52:29 +0100463 ft_cpu_setup(blob, bd);
Simon Glasse895a4b2014-10-23 18:58:47 -0600464
465 return 0;
Heiko Schocherac9db062008-01-11 01:12:08 +0100466}
467#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */