blob: 803d722806046ab3fc296631b6094d0641e9895a [file] [log] [blame]
Timur Tabi2ad6b512006-10-31 18:44:42 -06001/*
Kumar Gala4c2e3da2009-07-28 21:49:52 -05002 * Copyright (C) Freescale Semiconductor, Inc. 2006.
Timur Tabi2ad6b512006-10-31 18:44:42 -06003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Timur Tabi2ad6b512006-10-31 18:44:42 -06005 */
6
7#include <common.h>
8#include <ioports.h>
9#include <mpc83xx.h>
10#include <i2c.h>
Timur Tabi2ad6b512006-10-31 18:44:42 -060011#include <miiphy.h>
Timur Tabi89c77842008-02-08 13:15:55 -060012#include <vsc7385.h>
Timur Tabi2ad6b512006-10-31 18:44:42 -060013#ifdef CONFIG_PCI
14#include <asm/mpc8349_pci.h>
15#include <pci.h>
16#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -060017#include <spd_sdram.h>
Timur Tabi2ad6b512006-10-31 18:44:42 -060018#include <asm/mmu.h>
Kim Phillipsb3458d22007-12-20 15:57:28 -060019#if defined(CONFIG_OF_LIBFDT)
Kim Phillips3fde9e82007-08-15 22:30:33 -050020#include <libfdt.h>
Kim Phillipsbf0b5422006-11-01 00:10:40 -060021#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -060022
23#ifndef CONFIG_SPD_EEPROM
24/*************************************************************************
25 * fixed sdram init -- doesn't use serial presence detect.
26 ************************************************************************/
27int fixed_sdram(void)
28{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Joe Hershberger2e651b22011-10-11 23:57:31 -050030 /* The size of RAM, in bytes */
31 u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
32 u32 ddr_size_log2 = __ilog2(ddr_size);
Timur Tabi2ad6b512006-10-31 18:44:42 -060033
34 im->sysconf.ddrlaw[0].ar =
35 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
Timur Tabi2ad6b512006-10-31 18:44:42 -060037
Joe Hershberger2e651b22011-10-11 23:57:31 -050038#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
39#warning Chip select bounds is only configurable in 16MB increments
40#endif
41 im->ddr.csbnds[0].csbnds =
42 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
43 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
44 CSBNDS_EA_SHIFT) & CSBNDS_EA);
45 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
46
47 /* Only one CS for DDR */
48 im->ddr.cs_config[1] = 0;
49 im->ddr.cs_config[2] = 0;
50 im->ddr.cs_config[3] = 0;
Timur Tabi2ad6b512006-10-31 18:44:42 -060051
52 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
53 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
54
55 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
56 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
57
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
59 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
Kim Phillipsbbea46f2007-08-16 22:52:48 -050060 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
Timur Tabi2ad6b512006-10-31 18:44:42 -060061 im->ddr.sdram_mode =
62 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
63 im->ddr.sdram_interval =
64 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
65 SDRAM_INTERVAL_BSTOPRE_SHIFT);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
Timur Tabi2ad6b512006-10-31 18:44:42 -060067
68 udelay(200);
69
70 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
71
72 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
73 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
74 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
75 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
76 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
77
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078 return CONFIG_SYS_DDR_SIZE;
Timur Tabi2ad6b512006-10-31 18:44:42 -060079}
80#endif
81
82#ifdef CONFIG_PCI
83/*
84 * Initialize PCI Devices, report devices found
85 */
86#ifndef CONFIG_PCI_PNP
87static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
88 {
89 PCI_ANY_ID,
90 PCI_ANY_ID,
91 PCI_ANY_ID,
92 PCI_ANY_ID,
93 0x0f,
94 PCI_ANY_ID,
95 pci_cfgfunc_config_device,
96 {
97 PCI_ENET0_IOADDR,
98 PCI_ENET0_MEMADDR,
99 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
100 },
101 {}
102}
103#endif
104
105volatile static struct pci_controller hose[] = {
106 {
107#ifndef CONFIG_PCI_PNP
108 config_table:pci_mpc83xxmitx_config_table,
109#endif
110 },
111 {
112#ifndef CONFIG_PCI_PNP
113 config_table:pci_mpc83xxmitx_config_table,
114#endif
115 }
116};
117#endif /* CONFIG_PCI */
118
Becky Bruce9973e3c2008-06-09 16:03:40 -0500119phys_size_t initdram(int board_type)
Timur Tabi2ad6b512006-10-31 18:44:42 -0600120{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600122 u32 msize = 0;
123#ifdef CONFIG_DDR_ECC
124 volatile ddr83xx_t *ddr = &im->ddr;
125#endif
126
127 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
128 return -1;
129
130 /* DDR SDRAM - Main SODIMM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600132#ifdef CONFIG_SPD_EEPROM
133 msize = spd_sdram();
134#else
135 msize = fixed_sdram();
136#endif
137
138#ifdef CONFIG_DDR_ECC
139 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
140 /* Unlike every other board, on the 83xx spd_sdram() returns
141 megabytes instead of just bytes. That's why we need to
142 multiple by 1MB when calling ddr_enable_ecc(). */
143 ddr_enable_ecc(msize * 1048576);
144#endif
145
Timur Tabifab16802007-01-31 15:54:20 -0600146 /* return total bus RAM size(bytes) */
Timur Tabi2ad6b512006-10-31 18:44:42 -0600147 return msize * 1024 * 1024;
148}
149
150int checkboard(void)
151{
Timur Tabi7a78f142007-01-31 15:54:29 -0600152#ifdef CONFIG_MPC8349ITX
Timur Tabibe5e6182006-11-03 19:15:00 -0600153 puts("Board: Freescale MPC8349E-mITX\n");
Timur Tabi7a78f142007-01-31 15:54:29 -0600154#else
155 puts("Board: Freescale MPC8349E-mITX-GP\n");
156#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600157
158 return 0;
159}
160
Timur Tabibe5e6182006-11-03 19:15:00 -0600161/*
Timur Tabi2ad6b512006-10-31 18:44:42 -0600162 * Implement a work-around for a hardware problem with compact
163 * flash.
164 *
165 * Program the UPM if compact flash is enabled.
166 */
167int misc_init_f(void)
168{
Timur Tabi89c77842008-02-08 13:15:55 -0600169#ifdef CONFIG_VSC7385_ENET
Timur Tabi2ad6b512006-10-31 18:44:42 -0600170 volatile u32 *vsc7385_cpuctrl;
171
172 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
173 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
174 means it is 0 when the IRQ is not active. This makes the wire-AND
175 logic always assert IRQ7 to CPU even if there is no request from the
176 switch. Since the compact flash and the switch share the same IRQ,
177 the Linux kernel will think that the compact flash is requesting irq
178 and get stuck when it tries to clear the IRQ. Thus we need to set
179 the L2_IRQ0 and L2_IRQ1 to active low.
180
181 The following code sets the L1_IRQ and L2_IRQ polarity to active low.
182 Without this code, compact flash will not work in Linux because
183 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
184 don't enable compact flash for U-Boot.
185 */
186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187 vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
Timur Tabi2ad6b512006-10-31 18:44:42 -0600188 *vsc7385_cpuctrl |= 0x0c;
Timur Tabi7a78f142007-01-31 15:54:29 -0600189#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600190
191#ifdef CONFIG_COMPACT_FLASH
192 /* UPM Table Configuration Code */
193 static uint UPMATable[] = {
194 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
195 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
196 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
197 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
198 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
199 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
200 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
201 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
202 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
203 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
204 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
205 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
206 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
207 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
208 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
209 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
210 };
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600212
Becky Brucef51cdaf2010-06-17 11:37:20 -0500213 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
214 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
Timur Tabi2ad6b512006-10-31 18:44:42 -0600215
216 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
217 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
218 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500219 immap->im_lbc.mamr = 0x08404440;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600220
221 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
222
223 puts("UPMA: Configured for compact flash\n");
224#endif
225
226 return 0;
227}
228
Timur Tabibe5e6182006-11-03 19:15:00 -0600229/*
Timur Tabi89c77842008-02-08 13:15:55 -0600230 * Miscellaneous late-boot configurations
231 *
Timur Tabi2ad6b512006-10-31 18:44:42 -0600232 * Make sure the EEPROM has the HRCW correctly programmed.
233 * Make sure the RTC is correctly programmed.
234 *
235 * The MPC8349E-mITX can be configured to load the HRCW from
236 * EEPROM instead of flash. This is controlled via jumpers
237 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
238 * jumpered), but if they're set to 001 or 010, then the HRCW is
239 * read from the "I2C EEPROM".
240 *
241 * This function makes sure that the I2C EEPROM is programmed
242 * correctly.
Timur Tabi89c77842008-02-08 13:15:55 -0600243 *
244 * If a VSC7385 microcode image is present, then upload it.
Timur Tabi2ad6b512006-10-31 18:44:42 -0600245 */
246int misc_init_r(void)
247{
248 int rc = 0;
249
Heiko Schocher00f792e2012-10-24 13:48:22 +0200250#if defined(CONFIG_SYS_I2C)
Sam Song05031db2006-12-14 19:03:21 +0800251 unsigned int orig_bus = i2c_get_bus_num();
Timur Tabibe5e6182006-11-03 19:15:00 -0600252 u8 i2c_data;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#ifdef CONFIG_SYS_I2C_RTC_ADDR
Timur Tabie857a5b2006-11-28 12:09:35 -0600255 u8 ds1339_data[17];
Timur Tabi2ad6b512006-10-31 18:44:42 -0600256#endif
257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
Timur Tabi2ad6b512006-10-31 18:44:42 -0600259 static u8 eeprom_data[] = /* HRCW data */
260 {
Timur Tabi7a78f142007-01-31 15:54:29 -0600261 0xAA, 0x55, 0xAA, /* Preamble */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200262 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
263 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
265 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
266 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
267 CONFIG_SYS_HRCW_LOW & 0xFF,
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200268 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
Timur Tabi7a78f142007-01-31 15:54:29 -0600269 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
271 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
272 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
273 CONFIG_SYS_HRCW_HIGH & 0xFF
Timur Tabi2ad6b512006-10-31 18:44:42 -0600274 };
275
276 u8 data[sizeof(eeprom_data)];
Timur Tabibe5e6182006-11-03 19:15:00 -0600277#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -0600278
Timur Tabibe5e6182006-11-03 19:15:00 -0600279 printf("Board revision: ");
Timur Tabi9ca880a2006-10-31 21:23:16 -0600280 i2c_set_bus_num(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281 if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
Timur Tabibe5e6182006-11-03 19:15:00 -0600282 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283 else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
Timur Tabibe5e6182006-11-03 19:15:00 -0600284 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
285 else {
286 printf("Unknown\n");
287 rc = 1;
288 }
289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
Timur Tabibe5e6182006-11-03 19:15:00 -0600291 i2c_set_bus_num(0);
Timur Tabi2ad6b512006-10-31 18:44:42 -0600292
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
Timur Tabi2ad6b512006-10-31 18:44:42 -0600294 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
295 if (i2c_write
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296 (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
Timur Tabi2ad6b512006-10-31 18:44:42 -0600297 sizeof(eeprom_data)) != 0) {
298 puts("Failure writing the HRCW to EEPROM via I2C.\n");
299 rc = 1;
300 }
301 }
302 } else {
303 puts("Failure reading the HRCW from EEPROM via I2C.\n");
304 rc = 1;
305 }
306#endif
307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#ifdef CONFIG_SYS_I2C_RTC_ADDR
Timur Tabibe5e6182006-11-03 19:15:00 -0600309 i2c_set_bus_num(1);
Timur Tabi2ad6b512006-10-31 18:44:42 -0600310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
Timur Tabi2ad6b512006-10-31 18:44:42 -0600312 == 0) {
313
314 /* Work-around for MPC8349E-mITX bug #13601.
315 If the RTC does not contain valid register values, the DS1339
316 Linux driver will not work.
317 */
318
319 /* Make sure status register bits 6-2 are zero */
320 ds1339_data[0x0f] &= ~0x7c;
321
322 /* Check for a valid day register value */
323 ds1339_data[0x03] &= ~0xf8;
324 if (ds1339_data[0x03] == 0) {
325 ds1339_data[0x03] = 1;
326 }
327
328 /* Check for a valid date register value */
329 ds1339_data[0x04] &= ~0xc0;
330 if ((ds1339_data[0x04] == 0) ||
331 ((ds1339_data[0x04] & 0x0f) > 9) ||
332 (ds1339_data[0x04] >= 0x32)) {
333 ds1339_data[0x04] = 1;
334 }
335
336 /* Check for a valid month register value */
337 ds1339_data[0x05] &= ~0x60;
338
339 if ((ds1339_data[0x05] == 0) ||
340 ((ds1339_data[0x05] & 0x0f) > 9) ||
341 ((ds1339_data[0x05] >= 0x13)
342 && (ds1339_data[0x05] <= 0x19))) {
343 ds1339_data[0x05] = 1;
344 }
345
346 /* Enable Oscillator and rate select */
347 ds1339_data[0x0e] = 0x1c;
348
349 /* Work-around for MPC8349E-mITX bug #13330.
350 Ensure that the RTC control register contains the value 0x1c.
351 This affects SATA performance.
352 */
353
354 if (i2c_write
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355 (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
Timur Tabi2ad6b512006-10-31 18:44:42 -0600356 sizeof(ds1339_data))) {
357 puts("Failure writing to the RTC via I2C.\n");
358 rc = 1;
359 }
360 } else {
361 puts("Failure reading from the RTC via I2C.\n");
362 rc = 1;
363 }
364#endif
365
366 i2c_set_bus_num(orig_bus);
367#endif
368
Timur Tabi89c77842008-02-08 13:15:55 -0600369#ifdef CONFIG_VSC7385_IMAGE
370 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
371 CONFIG_VSC7385_IMAGE_SIZE)) {
372 puts("Failure uploading VSC7385 microcode.\n");
373 rc = 1;
374 }
375#endif
376
Timur Tabi2ad6b512006-10-31 18:44:42 -0600377 return rc;
378}
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600379
Kim Phillips3fde9e82007-08-15 22:30:33 -0500380#if defined(CONFIG_OF_BOARD_SETUP)
381void ft_board_setup(void *blob, bd_t *bd)
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600382{
Kim Phillips3fde9e82007-08-15 22:30:33 -0500383 ft_cpu_setup(blob, bd);
384#ifdef CONFIG_PCI
385 ft_pci_setup(blob, bd);
386#endif
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600387}
388#endif