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wdenk42d1f032003-10-15 23:53:47 +00001/*
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +00002 * Copyright 2004, 2007-2012 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00003 * Copyright (C) 2003 Motorola,Inc.
wdenk42d1f032003-10-15 23:53:47 +00004 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +00006 */
7
8/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
9 *
10 * The processor starts at 0xfffffffc and the code is first executed in the
11 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
12 *
13 */
14
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020015#include <asm-offsets.h>
wdenk42d1f032003-10-15 23:53:47 +000016#include <config.h>
17#include <mpc85xx.h>
18#include <version.h>
19
wdenk42d1f032003-10-15 23:53:47 +000020#include <ppc_asm.tmpl>
21#include <ppc_defs.h>
22
23#include <asm/cache.h>
24#include <asm/mmu.h>
25
wdenk42d1f032003-10-15 23:53:47 +000026#undef MSR_KERNEL
Andy Fleming61a21e92007-08-14 01:34:21 -050027#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
wdenk42d1f032003-10-15 23:53:47 +000028
Prabhakar Kushwahab26df182014-04-08 19:12:05 +053029#define LAW_EN 0x80000000
30
Scott Wood4b919722012-09-20 16:35:21 -050031#if defined(CONFIG_NAND_SPL) || \
32 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
33#define MINIMAL_SPL
34#endif
35
Liu Gang17b86142013-06-28 17:58:37 +080036#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
37 !defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Scott Wood4b919722012-09-20 16:35:21 -050038#define NOR_BOOT
39#endif
40
wdenk42d1f032003-10-15 23:53:47 +000041/*
42 * Set up GOT: Global Offset Table
43 *
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +010044 * Use r12 to access the GOT
wdenk42d1f032003-10-15 23:53:47 +000045 */
46 START_GOT
47 GOT_ENTRY(_GOT2_TABLE_)
48 GOT_ENTRY(_FIXUP_TABLE_)
49
Scott Wood4b919722012-09-20 16:35:21 -050050#ifndef MINIMAL_SPL
wdenk42d1f032003-10-15 23:53:47 +000051 GOT_ENTRY(_start)
52 GOT_ENTRY(_start_of_vectors)
53 GOT_ENTRY(_end_of_vectors)
54 GOT_ENTRY(transfer_to_handler)
Mingkai Hu7da53352009-09-11 14:19:10 +080055#endif
wdenk42d1f032003-10-15 23:53:47 +000056
57 GOT_ENTRY(__init_end)
Simon Glass3929fb02013-03-14 06:54:53 +000058 GOT_ENTRY(__bss_end)
wdenk42d1f032003-10-15 23:53:47 +000059 GOT_ENTRY(__bss_start)
60 END_GOT
61
62/*
63 * e500 Startup -- after reset only the last 4KB of the effective
64 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
65 * section is located at THIS LAST page and basically does three
66 * things: clear some registers, set up exception tables and
67 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
68 * continue the boot procedure.
69
70 * Once the boot rom is mapped by TLB entries we can proceed
71 * with normal startup.
72 *
73 */
74
Andy Fleming61a21e92007-08-14 01:34:21 -050075 .section .bootpg,"ax"
76 .globl _start_e500
wdenk42d1f032003-10-15 23:53:47 +000077
78_start_e500:
Prabhakar Kushwaha5344f7a2012-04-29 23:56:30 +000079/* Enable debug exception */
80 li r1,MSR_DE
81 mtmsr r1
wdenk97d80fc2004-06-09 00:34:46 +000082
Alexander Graffa08d392014-04-11 17:09:45 +020083 /*
84 * If we got an ePAPR device tree pointer passed in as r3, we need that
85 * later in cpu_init_early_f(). Save it to a safe register before we
86 * clobber it so that we can fetch it from there later.
87 */
88 mr r24, r3
89
Scott Wood33eee332012-08-14 10:14:53 +000090#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
91 mfspr r3,SPRN_SVR
92 rlwinm r3,r3,0,0xff
93 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
94 cmpw r3,r4
95 beq 1f
96
97#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
98 li r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
99 cmpw r3,r4
100 beq 1f
101#endif
102
103 /* Not a supported revision affected by erratum */
104 li r27,0
105 b 2f
106
1071: li r27,1 /* Remember for later that we have the erratum */
108 /* Erratum says set bits 55:60 to 001001 */
109 msync
110 isync
Andy Flemingcd7ad622013-03-25 07:33:10 +0000111 mfspr r3,SPRN_HDBCR0
Scott Wood33eee332012-08-14 10:14:53 +0000112 li r4,0x48
113 rlwimi r3,r4,0,0x1f8
Andy Flemingcd7ad622013-03-25 07:33:10 +0000114 mtspr SPRN_HDBCR0,r3
Scott Wood33eee332012-08-14 10:14:53 +0000115 isync
1162:
117#endif
York Sun954a1a42013-08-20 15:09:43 -0700118#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
119 msync
120 isync
121 mfspr r3, SPRN_HDBCR0
122 oris r3, r3, 0x0080
123 mtspr SPRN_HDBCR0, r3
124#endif
125
Scott Wood33eee332012-08-14 10:14:53 +0000126
Aneesh Bansalfb4a2402014-03-18 23:40:26 +0530127#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
128 !defined(CONFIG_E6500)
Ruchika Gupta7065b7d2010-12-15 17:02:08 +0000129 /* ISBC uses L2 as stack.
130 * Disable L2 cache here so that u-boot can enable it later
131 * as part of it's normal flow
132 */
133
134 /* Check if L2 is enabled */
135 mfspr r3, SPRN_L2CSR0
136 lis r2, L2CSR0_L2E@h
137 ori r2, r2, L2CSR0_L2E@l
138 and. r4, r3, r2
139 beq l2_disabled
140
141 mfspr r3, SPRN_L2CSR0
142 /* Flush L2 cache */
143 lis r2,(L2CSR0_L2FL)@h
144 ori r2, r2, (L2CSR0_L2FL)@l
145 or r3, r2, r3
146 sync
147 isync
148 mtspr SPRN_L2CSR0,r3
149 isync
1501:
151 mfspr r3, SPRN_L2CSR0
152 and. r1, r3, r2
153 bne 1b
154
155 mfspr r3, SPRN_L2CSR0
156 lis r2, L2CSR0_L2E@h
157 ori r2, r2, L2CSR0_L2E@l
158 andc r4, r3, r2
159 sync
160 isync
161 mtspr SPRN_L2CSR0,r4
162 isync
163
164l2_disabled:
165#endif
166
Andy Fleming61a21e92007-08-14 01:34:21 -0500167/* clear registers/arrays not reset by hardware */
wdenk42d1f032003-10-15 23:53:47 +0000168
Andy Fleming61a21e92007-08-14 01:34:21 -0500169 /* L1 */
170 li r0,2
171 mtspr L1CSR0,r0 /* invalidate d-cache */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200172 mtspr L1CSR1,r0 /* invalidate i-cache */
wdenk42d1f032003-10-15 23:53:47 +0000173
174 mfspr r1,DBSR
175 mtspr DBSR,r1 /* Clear all valid bits */
176
wdenk42d1f032003-10-15 23:53:47 +0000177
York Sun69c78262012-10-08 07:44:07 +0000178 .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
179 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
180 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
181 mtspr MAS0, \scratch
182 lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
183 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
184 mtspr MAS1, \scratch
185 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
186 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
187 mtspr MAS2, \scratch
188 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
189 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
190 mtspr MAS3, \scratch
191 lis \scratch, \phy_high@h
192 ori \scratch, \scratch, \phy_high@l
193 mtspr MAS7, \scratch
194 isync
195 msync
196 tlbwe
197 isync
198 .endm
199
200 .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
201 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
202 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
203 mtspr MAS0, \scratch
204 lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
205 ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
206 mtspr MAS1, \scratch
207 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
208 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
209 mtspr MAS2, \scratch
210 lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
211 ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
212 mtspr MAS3, \scratch
213 lis \scratch, \phy_high@h
214 ori \scratch, \scratch, \phy_high@l
215 mtspr MAS7, \scratch
216 isync
217 msync
218 tlbwe
219 isync
220 .endm
221
222 .macro delete_tlb1_entry esel scratch
223 lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
224 ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
225 mtspr MAS0, \scratch
226 li \scratch, 0
227 mtspr MAS1, \scratch
228 isync
229 msync
230 tlbwe
231 isync
232 .endm
233
234 .macro delete_tlb0_entry esel epn wimg scratch
235 lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
236 ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
237 mtspr MAS0, \scratch
238 li \scratch, 0
239 mtspr MAS1, \scratch
240 lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
241 ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
242 mtspr MAS2, \scratch
243 isync
244 msync
245 tlbwe
246 isync
247 .endm
248
Scott Wood4b919722012-09-20 16:35:21 -0500249/* Interrupt vectors do not fit in minimal SPL. */
250#if !defined(MINIMAL_SPL)
wdenk42d1f032003-10-15 23:53:47 +0000251 /* Setup interrupt vectors */
Haiying Wang0635b092010-11-10 15:37:13 -0500252 lis r1,CONFIG_SYS_MONITOR_BASE@h
Andy Fleming61a21e92007-08-14 01:34:21 -0500253 mtspr IVPR,r1
wdenk42d1f032003-10-15 23:53:47 +0000254
Scott Wood96d2bb92015-04-07 20:20:00 -0500255 li r4,CriticalInput@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000256 mtspr IVOR0,r4 /* 0: Critical input */
Scott Wood96d2bb92015-04-07 20:20:00 -0500257 li r4,MachineCheck@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000258 mtspr IVOR1,r4 /* 1: Machine check */
Scott Wood96d2bb92015-04-07 20:20:00 -0500259 li r4,DataStorage@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000260 mtspr IVOR2,r4 /* 2: Data storage */
Scott Wood96d2bb92015-04-07 20:20:00 -0500261 li r4,InstStorage@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000262 mtspr IVOR3,r4 /* 3: Instruction storage */
Scott Wood96d2bb92015-04-07 20:20:00 -0500263 li r4,ExtInterrupt@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000264 mtspr IVOR4,r4 /* 4: External interrupt */
Scott Wood96d2bb92015-04-07 20:20:00 -0500265 li r4,Alignment@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000266 mtspr IVOR5,r4 /* 5: Alignment */
Scott Wood96d2bb92015-04-07 20:20:00 -0500267 li r4,ProgramCheck@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000268 mtspr IVOR6,r4 /* 6: Program check */
Scott Wood96d2bb92015-04-07 20:20:00 -0500269 li r4,FPUnavailable@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000270 mtspr IVOR7,r4 /* 7: floating point unavailable */
Scott Wood96d2bb92015-04-07 20:20:00 -0500271 li r4,SystemCall@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000272 mtspr IVOR8,r4 /* 8: System call */
wdenk42d1f032003-10-15 23:53:47 +0000273 /* 9: Auxiliary processor unavailable(unsupported) */
Scott Wood96d2bb92015-04-07 20:20:00 -0500274 li r4,Decrementer@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000275 mtspr IVOR10,r4 /* 10: Decrementer */
Scott Wood96d2bb92015-04-07 20:20:00 -0500276 li r4,IntervalTimer@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000277 mtspr IVOR11,r4 /* 11: Interval timer */
Scott Wood96d2bb92015-04-07 20:20:00 -0500278 li r4,WatchdogTimer@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000279 mtspr IVOR12,r4 /* 12: Watchdog timer */
Scott Wood96d2bb92015-04-07 20:20:00 -0500280 li r4,DataTLBError@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000281 mtspr IVOR13,r4 /* 13: Data TLB error */
Scott Wood96d2bb92015-04-07 20:20:00 -0500282 li r4,InstructionTLBError@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000283 mtspr IVOR14,r4 /* 14: Instruction TLB error */
Scott Wood96d2bb92015-04-07 20:20:00 -0500284 li r4,DebugBreakpoint@l
Prabhakar Kushwahaa4107f82012-02-14 22:49:29 +0000285 mtspr IVOR15,r4 /* 15: Debug */
Prabhakar Kushwaha119a55f2012-02-14 22:50:02 +0000286#endif
wdenk42d1f032003-10-15 23:53:47 +0000287
wdenk42d1f032003-10-15 23:53:47 +0000288 /* Clear and set up some registers. */
Kumar Gala87163182008-01-16 22:38:34 -0600289 li r0,0x0000
wdenk42d1f032003-10-15 23:53:47 +0000290 lis r1,0xffff
291 mtspr DEC,r0 /* prevent dec exceptions */
292 mttbl r0 /* prevent fit & wdt exceptions */
293 mttbu r0
294 mtspr TSR,r1 /* clear all timer exception status */
295 mtspr TCR,r0 /* disable all */
296 mtspr ESR,r0 /* clear exception syndrome register */
297 mtspr MCSR,r0 /* machine check syndrome register */
298 mtxer r0 /* clear integer exception register */
wdenk42d1f032003-10-15 23:53:47 +0000299
Scott Wooddcc87dd2009-08-20 17:45:05 -0500300#ifdef CONFIG_SYS_BOOK3E_HV
301 mtspr MAS8,r0 /* make sure MAS8 is clear */
302#endif
303
wdenk42d1f032003-10-15 23:53:47 +0000304 /* Enable Time Base and Select Time Base Clock */
wdenk0ac6f8b2004-07-09 23:27:13 +0000305 lis r0,HID0_EMCP@h /* Enable machine check */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500306#if defined(CONFIG_ENABLE_36BIT_PHYS)
Kumar Gala87163182008-01-16 22:38:34 -0600307 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500308#endif
Kumar Gala1b3e4042009-03-19 09:16:10 -0500309#ifndef CONFIG_E500MC
Kumar Gala87163182008-01-16 22:38:34 -0600310 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
Kumar Gala1b3e4042009-03-19 09:16:10 -0500311#endif
wdenk42d1f032003-10-15 23:53:47 +0000312 mtspr HID0,r0
wdenk42d1f032003-10-15 23:53:47 +0000313
Alexander Grafa6c46b92014-04-30 19:21:11 +0200314#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
Andy Fleming61a21e92007-08-14 01:34:21 -0500315 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
Sandeep Gopalpetff8473e2010-03-12 10:45:02 +0530316 mfspr r3,PVR
317 andi. r3,r3, 0xff
318 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
319 blt 1f
320 /* Set MBDD bit also */
321 ori r0, r0, HID1_MBDD@l
3221:
wdenk42d1f032003-10-15 23:53:47 +0000323 mtspr HID1,r0
Kumar Gala0f060c32008-10-23 01:47:38 -0500324#endif
wdenk42d1f032003-10-15 23:53:47 +0000325
Kumar Gala43f082b2011-11-22 06:51:15 -0600326#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
Andy Flemingcd7ad622013-03-25 07:33:10 +0000327 mfspr r3,SPRN_HDBCR1
Kumar Gala43f082b2011-11-22 06:51:15 -0600328 oris r3,r3,0x0100
Andy Flemingcd7ad622013-03-25 07:33:10 +0000329 mtspr SPRN_HDBCR1,r3
Kumar Gala43f082b2011-11-22 06:51:15 -0600330#endif
331
wdenk42d1f032003-10-15 23:53:47 +0000332 /* Enable Branch Prediction */
333#if defined(CONFIG_BTB)
Kumar Gala69bcf5b2010-03-29 13:50:31 -0500334 lis r0,BUCSR_ENABLE@h
335 ori r0,r0,BUCSR_ENABLE@l
336 mtspr SPRN_BUCSR,r0
wdenk42d1f032003-10-15 23:53:47 +0000337#endif
338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#if defined(CONFIG_SYS_INIT_DBCR)
wdenk42d1f032003-10-15 23:53:47 +0000340 lis r1,0xffff
341 ori r1,r1,0xffff
wdenk0ac6f8b2004-07-09 23:27:13 +0000342 mtspr DBSR,r1 /* Clear all status bits */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
344 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
wdenk0ac6f8b2004-07-09 23:27:13 +0000345 mtspr DBCR0,r0
wdenk42d1f032003-10-15 23:53:47 +0000346#endif
347
Haiying Wang22b6dbc2009-03-27 17:02:44 -0400348#ifdef CONFIG_MPC8569
349#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
350#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
351
352 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
353 * use address space which is more than 12bits, and it must be done in
354 * the 4K boot page. So we set this bit here.
355 */
356
357 /* create a temp mapping TLB0[0] for LBCR */
York Sun69c78262012-10-08 07:44:07 +0000358 create_tlb0_entry 0, \
359 0, BOOKE_PAGESZ_4K, \
360 CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
361 CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
362 0, r6
Haiying Wang22b6dbc2009-03-27 17:02:44 -0400363
364 /* Set LBCR register */
365 lis r4,CONFIG_SYS_LBCR_ADDR@h
366 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
367
368 lis r5,CONFIG_SYS_LBC_LBCR@h
369 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
370 stw r5,0(r4)
371 isync
372
373 /* invalidate this temp TLB */
374 lis r4,CONFIG_SYS_LBC_ADDR@h
375 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
376 tlbivax 0,r4
377 isync
378
379#endif /* CONFIG_MPC8569 */
380
Timur Tabi6ca88b02011-08-03 16:30:10 -0500381/*
Timur Tabi72243c02011-10-31 13:30:45 -0500382 * Search for the TLB that covers the code we're executing, and shrink it
383 * so that it covers only this 4K page. That will ensure that any other
384 * TLB we create won't interfere with it. We assume that the TLB exists,
Scott Wood3ea21532012-08-20 13:10:08 +0000385 * which is why we don't check the Valid bit of MAS1. We also assume
386 * it is in TLB1.
Timur Tabi72243c02011-10-31 13:30:45 -0500387 *
388 * This is necessary, for example, when booting from the on-chip ROM,
389 * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
Timur Tabi72243c02011-10-31 13:30:45 -0500390 */
391 bl nexti /* Find our address */
392nexti: mflr r1 /* R1 = our PC */
393 li r2, 0
394 mtspr MAS6, r2 /* Assume the current PID and AS are 0 */
395 isync
396 msync
397 tlbsx 0, r1 /* This must succeed */
398
Scott Wood3ea21532012-08-20 13:10:08 +0000399 mfspr r14, MAS0 /* Save ESEL for later */
400 rlwinm r14, r14, 16, 0xfff
401
Timur Tabi72243c02011-10-31 13:30:45 -0500402 /* Set the size of the TLB to 4KB */
403 mfspr r3, MAS1
Scott Wood31d084d2013-01-18 15:45:58 +0000404 li r2, 0xF80
Timur Tabi72243c02011-10-31 13:30:45 -0500405 andc r3, r3, r2 /* Clear the TSIZE bits */
406 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
Scott Wood3ea21532012-08-20 13:10:08 +0000407 oris r3, r3, MAS1_IPROT@h
Timur Tabi72243c02011-10-31 13:30:45 -0500408 mtspr MAS1, r3
409
410 /*
411 * Set the base address of the TLB to our PC. We assume that
412 * virtual == physical. We also assume that MAS2_EPN == MAS3_RPN.
413 */
414 lis r3, MAS2_EPN@h
415 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
416
417 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
418
419 mfspr r2, MAS2
420 andc r2, r2, r3
421 or r2, r2, r1
Scott Wood33eee332012-08-14 10:14:53 +0000422#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
423 cmpwi r27,0
424 beq 1f
425 andi. r15, r2, MAS2_I|MAS2_G /* save the old I/G for later */
426 rlwinm r2, r2, 0, ~MAS2_I
427 ori r2, r2, MAS2_G
4281:
429#endif
Timur Tabi72243c02011-10-31 13:30:45 -0500430 mtspr MAS2, r2 /* Set the EPN to our PC base address */
431
432 mfspr r2, MAS3
433 andc r2, r2, r3
434 or r2, r2, r1
435 mtspr MAS3, r2 /* Set the RPN to our PC base address */
436
437 isync
438 msync
439 tlbwe
440
441/*
Scott Wood3ea21532012-08-20 13:10:08 +0000442 * Clear out any other TLB entries that may exist, to avoid conflicts.
443 * Our TLB entry is in r14.
444 */
445 li r0, TLBIVAX_ALL | TLBIVAX_TLB0
446 tlbivax 0, r0
447 tlbsync
448
449 mfspr r4, SPRN_TLB1CFG
450 rlwinm r4, r4, 0, TLBnCFG_NENTRY_MASK
451
452 li r3, 0
453 mtspr MAS1, r3
4541: cmpw r3, r14
Scott Wood3ea21532012-08-20 13:10:08 +0000455 rlwinm r5, r3, 16, MAS0_ESEL_MSK
456 addi r3, r3, 1
457 beq 2f /* skip the entry we're executing from */
458
459 oris r5, r5, MAS0_TLBSEL(1)@h
460 mtspr MAS0, r5
461
462 isync
463 tlbwe
464 isync
465 msync
466
4672: cmpw r3, r4
468 blt 1b
469
Aneesh Bansalf978f7c2014-03-12 00:07:27 +0530470#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
471 !defined(CONFIG_SECURE_BOOT)
Scott Woodf545d302012-10-25 19:27:41 -0500472/*
473 * TLB entry for debuggging in AS1
474 * Create temporary TLB entry in AS0 to handle debug exception
475 * As on debug exception MSR is cleared i.e. Address space is changed
476 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
477 * in AS1.
478 */
479
Scott Wood4b919722012-09-20 16:35:21 -0500480#ifdef NOR_BOOT
Scott Woodf545d302012-10-25 19:27:41 -0500481/*
482 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
483 * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
484 * and this window is outside of 4K boot window.
485 */
486 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
487 0, BOOKE_PAGESZ_4M, \
488 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
489 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
490 0, r6
491
Scott Woodf545d302012-10-25 19:27:41 -0500492#else
493/*
494 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
495 * because "nexti" will resize TLB to 4K
496 */
497 create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
498 0, BOOKE_PAGESZ_256K, \
499 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
500 CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
501 0, r6
502#endif
503#endif
504
Scott Wood3ea21532012-08-20 13:10:08 +0000505/*
Timur Tabi6ca88b02011-08-03 16:30:10 -0500506 * Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
507 * location is not where we want it. This typically happens on a 36-bit
508 * system, where we want to move CCSR to near the top of 36-bit address space.
509 *
510 * To move CCSR, we create two temporary TLBs, one for the old location, and
511 * another for the new location. On CoreNet systems, we also need to create
512 * a special, temporary LAW.
513 *
514 * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for
515 * long-term TLBs, so we use TLB0 here.
516 */
517#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
518
519#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW)
520#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined."
521#endif
522
Timur Tabi6ca88b02011-08-03 16:30:10 -0500523create_ccsr_new_tlb:
524 /*
525 * Create a TLB for the new location of CCSR. Register R8 is reserved
526 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR).
527 */
Scott Wood3ea21532012-08-20 13:10:08 +0000528 lis r8, CONFIG_SYS_CCSRBAR@h
529 ori r8, r8, CONFIG_SYS_CCSRBAR@l
530 lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
531 ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
York Sun69c78262012-10-08 07:44:07 +0000532 create_tlb0_entry 0, \
533 0, BOOKE_PAGESZ_4K, \
534 CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
535 CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
536 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
Timur Tabi6ca88b02011-08-03 16:30:10 -0500537 /*
Timur Tabic2efa0a2011-10-31 13:30:42 -0500538 * Create a TLB for the current location of CCSR. Register R9 is reserved
Timur Tabi6ca88b02011-08-03 16:30:10 -0500539 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
540 */
541create_ccsr_old_tlb:
York Sun69c78262012-10-08 07:44:07 +0000542 create_tlb0_entry 1, \
543 0, BOOKE_PAGESZ_4K, \
544 CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
545 CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
546 0, r3 /* The default CCSR address is always a 32-bit number */
547
Timur Tabi6ca88b02011-08-03 16:30:10 -0500548
Timur Tabi19e43842011-10-31 13:30:44 -0500549 /*
550 * We have a TLB for what we think is the current (old) CCSR. Let's
551 * verify that, otherwise we won't be able to move it.
552 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
553 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
554 */
555verify_old_ccsr:
556 lis r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
557 ori r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
558#ifdef CONFIG_FSL_CORENET
559 lwz r1, 4(r9) /* CCSRBARL */
560#else
561 lwz r1, 0(r9) /* CCSRBAR, shifted right by 12 */
562 slwi r1, r1, 12
563#endif
564
565 cmpl 0, r0, r1
566
567 /*
568 * If the value we read from CCSRBARL is not what we expect, then
569 * enter an infinite loop. This will at least allow a debugger to
570 * halt execution and examine TLBs, etc. There's no point in going
571 * on.
572 */
573infinite_debug_loop:
574 bne infinite_debug_loop
575
Timur Tabi6ca88b02011-08-03 16:30:10 -0500576#ifdef CONFIG_FSL_CORENET
577
578#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
Timur Tabi6ca88b02011-08-03 16:30:10 -0500579#define LAW_SIZE_4K 0xb
580#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
581#define CCSRAR_C 0x80000000 /* Commit */
582
583create_temp_law:
584 /*
585 * On CoreNet systems, we create the temporary LAW using a special LAW
586 * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR.
587 */
588 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
589 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
590 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
591 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
592 lis r2, CCSRBAR_LAWAR@h
593 ori r2, r2, CCSRBAR_LAWAR@l
594
595 stw r0, 0xc00(r9) /* LAWBARH0 */
596 stw r1, 0xc04(r9) /* LAWBARL0 */
597 sync
598 stw r2, 0xc08(r9) /* LAWAR0 */
599
600 /*
601 * Read back from LAWAR to ensure the update is complete. e500mc
602 * cores also require an isync.
603 */
604 lwz r0, 0xc08(r9) /* LAWAR0 */
605 isync
606
607 /*
608 * Read the current CCSRBARH and CCSRBARL using load word instructions.
609 * Follow this with an isync instruction. This forces any outstanding
610 * accesses to configuration space to completion.
611 */
612read_old_ccsrbar:
613 lwz r0, 0(r9) /* CCSRBARH */
Timur Tabic2efa0a2011-10-31 13:30:42 -0500614 lwz r0, 4(r9) /* CCSRBARL */
Timur Tabi6ca88b02011-08-03 16:30:10 -0500615 isync
616
617 /*
618 * Write the new values for CCSRBARH and CCSRBARL to their old
619 * locations. The CCSRBARH has a shadow register. When the CCSRBARH
620 * has a new value written it loads a CCSRBARH shadow register. When
621 * the CCSRBARL is written, the CCSRBARH shadow register contents
622 * along with the CCSRBARL value are loaded into the CCSRBARH and
623 * CCSRBARL registers, respectively. Follow this with a sync
624 * instruction.
625 */
626write_new_ccsrbar:
627 lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
628 ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
629 lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
630 ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
631 lis r2, CCSRAR_C@h
632 ori r2, r2, CCSRAR_C@l
633
634 stw r0, 0(r9) /* Write to CCSRBARH */
635 sync /* Make sure we write to CCSRBARH first */
636 stw r1, 4(r9) /* Write to CCSRBARL */
637 sync
638
639 /*
640 * Write a 1 to the commit bit (C) of CCSRAR at the old location.
641 * Follow this with a sync instruction.
642 */
643 stw r2, 8(r9)
644 sync
645
646 /* Delete the temporary LAW */
647delete_temp_law:
648 li r1, 0
649 stw r1, 0xc08(r8)
650 sync
651 stw r1, 0xc00(r8)
652 stw r1, 0xc04(r8)
653 sync
654
655#else /* #ifdef CONFIG_FSL_CORENET */
656
657write_new_ccsrbar:
658 /*
659 * Read the current value of CCSRBAR using a load word instruction
660 * followed by an isync. This forces all accesses to configuration
661 * space to complete.
662 */
663 sync
664 lwz r0, 0(r9)
665 isync
666
667/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */
668#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \
669 (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12))
670
671 /* Write the new value to CCSRBAR. */
672 lis r0, CCSRBAR_PHYS_RS12@h
673 ori r0, r0, CCSRBAR_PHYS_RS12@l
674 stw r0, 0(r9)
675 sync
676
677 /*
678 * The manual says to perform a load of an address that does not
679 * access configuration space or the on-chip SRAM using an existing TLB,
680 * but that doesn't appear to be necessary. We will do the isync,
681 * though.
682 */
683 isync
684
685 /*
686 * Read the contents of CCSRBAR from its new location, followed by
687 * another isync.
688 */
689 lwz r0, 0(r8)
690 isync
691
692#endif /* #ifdef CONFIG_FSL_CORENET */
693
694 /* Delete the temporary TLBs */
695delete_temp_tlbs:
York Sun69c78262012-10-08 07:44:07 +0000696 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
697 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
Timur Tabi6ca88b02011-08-03 16:30:10 -0500698
Timur Tabi6ca88b02011-08-03 16:30:10 -0500699#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
700
Prabhakar Kushwahae9827462013-08-29 13:10:38 +0530701#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
York Sun6d2b9da2012-10-08 07:44:08 +0000702create_ccsr_l2_tlb:
703 /*
704 * Create a TLB for the MMR location of CCSR
705 * to access L2CSR0 register
706 */
707 create_tlb0_entry 0, \
708 0, BOOKE_PAGESZ_4K, \
709 CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
710 CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
711 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
712
713enable_l2_cluster_l2:
714 /* enable L2 cache */
715 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
716 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
717 li r4, 33 /* stash id */
718 stw r4, 4(r3)
719 lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
720 ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
721 sync
722 stw r4, 0(r3) /* invalidate L2 */
7231: sync
724 lwz r0, 0(r3)
725 twi 0, r0, 0
726 isync
727 and. r1, r0, r4
728 bne 1b
James Yangc416faf2013-03-25 07:39:58 +0000729 lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
James Yang9cd95ac2013-03-25 07:40:03 +0000730 ori r4, r4, (L2CSR0_L2REP_MODE)@l
York Sun6d2b9da2012-10-08 07:44:08 +0000731 sync
Andy Fleming3e4c3132013-03-25 07:33:14 +0000732 stw r4, 0(r3) /* enable L2 */
York Sun6d2b9da2012-10-08 07:44:08 +0000733delete_ccsr_l2_tlb:
734 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
735#endif
736
Andy Fleming3e4c3132013-03-25 07:33:14 +0000737 /*
738 * Enable the L1. On e6500, this has to be done
739 * after the L2 is up.
740 */
741
742#ifdef CONFIG_SYS_CACHE_STASHING
743 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
744 li r2,(32 + 0)
745 mtspr L1CSR2,r2
746#endif
747
748 /* Enable/invalidate the I-Cache */
749 lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
750 ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
751 mtspr SPRN_L1CSR1,r2
7521:
753 mfspr r3,SPRN_L1CSR1
754 and. r1,r3,r2
755 bne 1b
756
757 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
758 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
759 mtspr SPRN_L1CSR1,r3
760 isync
7612:
762 mfspr r3,SPRN_L1CSR1
763 andi. r1,r3,L1CSR1_ICE@l
764 beq 2b
765
766 /* Enable/invalidate the D-Cache */
767 lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
768 ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
769 mtspr SPRN_L1CSR0,r2
7701:
771 mfspr r3,SPRN_L1CSR0
772 and. r1,r3,r2
773 bne 1b
774
775 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
776 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
777 mtspr SPRN_L1CSR0,r3
778 isync
7792:
780 mfspr r3,SPRN_L1CSR0
781 andi. r1,r3,L1CSR0_DCE@l
782 beq 2b
Scott Wood33eee332012-08-14 10:14:53 +0000783#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
784#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
785#define LAW_SIZE_1M 0x13
786#define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M)
787
788 cmpwi r27,0
789 beq 9f
790
791 /*
792 * Create a TLB entry for CCSR
793 *
794 * We're executing out of TLB1 entry in r14, and that's the only
795 * TLB entry that exists. To allocate some TLB entries for our
796 * own use, flip a bit high enough that we won't flip it again
797 * via incrementing.
798 */
799
800 xori r8, r14, 32
801 lis r0, MAS0_TLBSEL(1)@h
802 rlwimi r0, r8, 16, MAS0_ESEL_MSK
803 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h
804 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l
805 lis r7, CONFIG_SYS_CCSRBAR@h
806 ori r7, r7, CONFIG_SYS_CCSRBAR@l
807 ori r2, r7, MAS2_I|MAS2_G
808 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
809 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
810 lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
811 ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
812 mtspr MAS0, r0
813 mtspr MAS1, r1
814 mtspr MAS2, r2
815 mtspr MAS3, r3
816 mtspr MAS7, r4
817 isync
818 tlbwe
819 isync
820 msync
821
822 /* Map DCSR temporarily to physical address zero */
823 li r0, 0
824 lis r3, DCSRBAR_LAWAR@h
825 ori r3, r3, DCSRBAR_LAWAR@l
826
827 stw r0, 0xc00(r7) /* LAWBARH0 */
828 stw r0, 0xc04(r7) /* LAWBARL0 */
829 sync
830 stw r3, 0xc08(r7) /* LAWAR0 */
831
832 /* Read back from LAWAR to ensure the update is complete. */
833 lwz r3, 0xc08(r7) /* LAWAR0 */
834 isync
835
836 /* Create a TLB entry for DCSR at zero */
837
838 addi r9, r8, 1
839 lis r0, MAS0_TLBSEL(1)@h
840 rlwimi r0, r9, 16, MAS0_ESEL_MSK
841 lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
842 ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
843 li r6, 0 /* DCSR effective address */
844 ori r2, r6, MAS2_I|MAS2_G
845 li r3, MAS3_SW|MAS3_SR
846 li r4, 0
847 mtspr MAS0, r0
848 mtspr MAS1, r1
849 mtspr MAS2, r2
850 mtspr MAS3, r3
851 mtspr MAS7, r4
852 isync
853 tlbwe
854 isync
855 msync
856
857 /* enable the timebase */
858#define CTBENR 0xe2084
859 li r3, 1
860 addis r4, r7, CTBENR@ha
861 stw r3, CTBENR@l(r4)
862 lwz r3, CTBENR@l(r4)
863 twi 0,r3,0
864 isync
865
866 .macro erratum_set_ccsr offset value
867 addis r3, r7, \offset@ha
868 lis r4, \value@h
869 addi r3, r3, \offset@l
870 ori r4, r4, \value@l
871 bl erratum_set_value
872 .endm
873
874 .macro erratum_set_dcsr offset value
875 addis r3, r6, \offset@ha
876 lis r4, \value@h
877 addi r3, r3, \offset@l
878 ori r4, r4, \value@l
879 bl erratum_set_value
880 .endm
881
882 erratum_set_dcsr 0xb0e08 0xe0201800
883 erratum_set_dcsr 0xb0e18 0xe0201800
884 erratum_set_dcsr 0xb0e38 0xe0400000
885 erratum_set_dcsr 0xb0008 0x00900000
886 erratum_set_dcsr 0xb0e40 0xe00a0000
887 erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
Dave Liu24936ed2013-11-28 14:58:08 +0800888#ifdef CONFIG_RAMBOOT_PBL
889 erratum_set_ccsr 0x10f00 0x495e5000
890#else
Scott Wood33eee332012-08-14 10:14:53 +0000891 erratum_set_ccsr 0x10f00 0x415e5000
Dave Liu24936ed2013-11-28 14:58:08 +0800892#endif
Scott Wood33eee332012-08-14 10:14:53 +0000893 erratum_set_ccsr 0x11f00 0x415e5000
894
895 /* Make temp mapping uncacheable again, if it was initially */
896 bl 2f
8972: mflr r3
898 tlbsx 0, r3
899 mfspr r4, MAS2
900 rlwimi r4, r15, 0, MAS2_I
901 rlwimi r4, r15, 0, MAS2_G
902 mtspr MAS2, r4
903 isync
904 tlbwe
905 isync
906 msync
907
908 /* Clear the cache */
909 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
910 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
911 sync
912 isync
913 mtspr SPRN_L1CSR1,r3
914 isync
9152: sync
916 mfspr r4,SPRN_L1CSR1
917 and. r4,r4,r3
918 bne 2b
919
920 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
921 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
922 sync
923 isync
924 mtspr SPRN_L1CSR1,r3
925 isync
9262: sync
927 mfspr r4,SPRN_L1CSR1
928 and. r4,r4,r3
929 beq 2b
930
931 /* Remove temporary mappings */
932 lis r0, MAS0_TLBSEL(1)@h
933 rlwimi r0, r9, 16, MAS0_ESEL_MSK
934 li r3, 0
935 mtspr MAS0, r0
936 mtspr MAS1, r3
937 isync
938 tlbwe
939 isync
940 msync
941
942 li r3, 0
943 stw r3, 0xc08(r7) /* LAWAR0 */
944 lwz r3, 0xc08(r7)
945 isync
946
947 lis r0, MAS0_TLBSEL(1)@h
948 rlwimi r0, r8, 16, MAS0_ESEL_MSK
949 li r3, 0
950 mtspr MAS0, r0
951 mtspr MAS1, r3
952 isync
953 tlbwe
954 isync
955 msync
956
957 b 9f
958
959 /* r3 = addr, r4 = value, clobbers r5, r11, r12 */
960erratum_set_value:
961 /* Lock two cache lines into I-Cache */
962 sync
963 mfspr r11, SPRN_L1CSR1
964 rlwinm r11, r11, 0, ~L1CSR1_ICUL
965 sync
966 isync
967 mtspr SPRN_L1CSR1, r11
968 isync
969
970 mflr r12
971 bl 5f
9725: mflr r5
973 addi r5, r5, 2f - 5b
974 icbtls 0, 0, r5
975 addi r5, r5, 64
976
977 sync
978 mfspr r11, SPRN_L1CSR1
9793: andi. r11, r11, L1CSR1_ICUL
980 bne 3b
981
982 icbtls 0, 0, r5
983 addi r5, r5, 64
984
985 sync
986 mfspr r11, SPRN_L1CSR1
9873: andi. r11, r11, L1CSR1_ICUL
988 bne 3b
989
990 b 2f
991 .align 6
992 /* Inside a locked cacheline, wait a while, write, then wait a while */
9932: sync
994
995 mfspr r5, SPRN_TBRL
996 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
9974: mfspr r5, SPRN_TBRL
998 subf. r5, r5, r11
999 bgt 4b
1000
1001 stw r4, 0(r3)
1002
1003 mfspr r5, SPRN_TBRL
1004 addis r11, r5, 0x10000@h /* wait 65536 timebase ticks */
10054: mfspr r5, SPRN_TBRL
1006 subf. r5, r5, r11
1007 bgt 4b
1008
1009 sync
1010
1011 /*
1012 * Fill out the rest of this cache line and the next with nops,
1013 * to ensure that nothing outside the locked area will be
1014 * fetched due to a branch.
1015 */
1016 .rept 19
1017 nop
1018 .endr
1019
1020 sync
1021 mfspr r11, SPRN_L1CSR1
1022 rlwinm r11, r11, 0, ~L1CSR1_ICUL
1023 sync
1024 isync
1025 mtspr SPRN_L1CSR1, r11
1026 isync
1027
1028 mtlr r12
1029 blr
1030
10319:
1032#endif
1033
Timur Tabi6ca88b02011-08-03 16:30:10 -05001034create_init_ram_area:
Kumar Gala87163182008-01-16 22:38:34 -06001035 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
1036 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
1037
Scott Wood4b919722012-09-20 16:35:21 -05001038#ifdef NOR_BOOT
Mingkai Hu7da53352009-09-11 14:19:10 +08001039 /* create a temp mapping in AS=1 to the 4M boot window */
York Sun69c78262012-10-08 07:44:07 +00001040 create_tlb1_entry 15, \
1041 1, BOOKE_PAGESZ_4M, \
1042 CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
1043 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
1044 0, r6
Kumar Gala87163182008-01-16 22:38:34 -06001045
Ruchika Gupta7065b7d2010-12-15 17:02:08 +00001046#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
1047 /* create a temp mapping in AS = 1 for Flash mapping
1048 * created by PBL for ISBC code
1049 */
York Sun69c78262012-10-08 07:44:07 +00001050 create_tlb1_entry 15, \
1051 1, BOOKE_PAGESZ_1M, \
Scott Wood7f0a22f2012-09-20 18:34:49 -05001052 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1053 CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
York Sun69c78262012-10-08 07:44:07 +00001054 0, r6
Mingkai Hu7da53352009-09-11 14:19:10 +08001055#else
1056 /*
Haiying Wang0635b092010-11-10 15:37:13 -05001057 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
1058 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
Mingkai Hu7da53352009-09-11 14:19:10 +08001059 */
York Sun69c78262012-10-08 07:44:07 +00001060 create_tlb1_entry 15, \
1061 1, BOOKE_PAGESZ_1M, \
Scott Wood7f0a22f2012-09-20 18:34:49 -05001062 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
1063 CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
York Sun69c78262012-10-08 07:44:07 +00001064 0, r6
Mingkai Hu7da53352009-09-11 14:19:10 +08001065#endif
Kumar Gala87163182008-01-16 22:38:34 -06001066
Kumar Gala87163182008-01-16 22:38:34 -06001067 /* create a temp mapping in AS=1 to the stack */
yorka3f18522010-07-02 22:25:57 +00001068#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
1069 defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
York Sun69c78262012-10-08 07:44:07 +00001070 create_tlb1_entry 14, \
1071 1, BOOKE_PAGESZ_16K, \
1072 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1073 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
1074 CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
Kumar Gala87163182008-01-16 22:38:34 -06001075
York Sun69c78262012-10-08 07:44:07 +00001076#else
1077 create_tlb1_entry 14, \
1078 1, BOOKE_PAGESZ_16K, \
1079 CONFIG_SYS_INIT_RAM_ADDR, 0, \
1080 CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
1081 0, r6
1082#endif
Kumar Gala87163182008-01-16 22:38:34 -06001083
Prabhakar Kushwaha5344f7a2012-04-29 23:56:30 +00001084 lis r6,MSR_IS|MSR_DS|MSR_DE@h
1085 ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
Kumar Gala87163182008-01-16 22:38:34 -06001086 lis r7,switch_as@h
1087 ori r7,r7,switch_as@l
1088
1089 mtspr SPRN_SRR0,r7
1090 mtspr SPRN_SRR1,r6
1091 rfi
1092
1093switch_as:
Andy Fleming61a21e92007-08-14 01:34:21 -05001094/* L1 DCache is used for initial RAM */
1095
wdenk42d1f032003-10-15 23:53:47 +00001096 /* Allocate Initial RAM in data cache.
1097 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001098 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1099 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
Kumar Galab009f3e2008-01-08 01:22:21 -06001100 mfspr r2, L1CFG0
1101 andi. r2, r2, 0x1ff
1102 /* cache size * 1024 / (2 * L1 line size) */
1103 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
wdenk343117b2005-05-13 22:49:36 +00001104 mtctr r2
Andy Fleming61a21e92007-08-14 01:34:21 -05001105 li r0,0
wdenk42d1f032003-10-15 23:53:47 +000011061:
Andy Fleming61a21e92007-08-14 01:34:21 -05001107 dcbz r0,r3
1108 dcbtls 0,r0,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001109 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
wdenk343117b2005-05-13 22:49:36 +00001110 bdnz 1b
wdenk42d1f032003-10-15 23:53:47 +00001111
Kumar Gala3db0bef2007-08-07 18:07:27 -05001112 /* Jump out the last 4K page and continue to 'normal' start */
Scott Wood4b919722012-09-20 16:35:21 -05001113#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
1114 /* We assume that we're already running at the address we're linked at */
Kumar Gala3db0bef2007-08-07 18:07:27 -05001115 b _start_cont
1116#else
wdenk343117b2005-05-13 22:49:36 +00001117 /* Calculate absolute address in FLASH and jump there */
wdenk42d1f032003-10-15 23:53:47 +00001118 /*--------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001119 lis r3,CONFIG_SYS_MONITOR_BASE@h
1120 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
Scott Wood96d2bb92015-04-07 20:20:00 -05001121 addi r3,r3,_start_cont - _start
wdenk343117b2005-05-13 22:49:36 +00001122 mtlr r3
urwithsughosh@gmail.com1e701e72007-09-24 13:36:01 -04001123 blr
Kumar Gala3db0bef2007-08-07 18:07:27 -05001124#endif
wdenk42d1f032003-10-15 23:53:47 +00001125
Kumar Gala3db0bef2007-08-07 18:07:27 -05001126 .text
1127 .globl _start
1128_start:
1129 .long 0x27051956 /* U-BOOT Magic Number */
1130 .globl version_string
1131version_string:
Andreas Bießmann09c2e902011-07-18 20:24:04 +02001132 .ascii U_BOOT_VERSION_STRING, "\0"
Kumar Gala3db0bef2007-08-07 18:07:27 -05001133
1134 .align 4
1135 .globl _start_cont
1136_start_cont:
wdenk42d1f032003-10-15 23:53:47 +00001137 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
Joakim Tjernlund89f42892012-07-23 10:58:02 +00001138 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1139 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
wdenk42d1f032003-10-15 23:53:47 +00001140 li r0,0
Joakim Tjernlund89f42892012-07-23 10:58:02 +00001141 stw r0,0(r3) /* Terminate Back Chain */
1142 stw r0,+4(r3) /* NULL return address. */
1143 mr r1,r3 /* Transfer to SP(r1) */
wdenk42d1f032003-10-15 23:53:47 +00001144
1145 GET_GOT
Alexander Graffa08d392014-04-11 17:09:45 +02001146
1147 /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
1148 mr r3, r24
1149
Kumar Gala87163182008-01-16 22:38:34 -06001150 bl cpu_init_early_f
1151
1152 /* switch back to AS = 0 */
1153 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1154 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1155 mtmsr r3
1156 isync
1157
York Sun701e6402014-04-30 14:43:47 -07001158 bl cpu_init_f /* return boot_flag for calling board_init_f */
wdenk42d1f032003-10-15 23:53:47 +00001159 bl board_init_f
wdenk0ac6f8b2004-07-09 23:27:13 +00001160 isync
wdenk42d1f032003-10-15 23:53:47 +00001161
Peter Tyser52ebd9c2010-09-14 19:13:53 -05001162 /* NOTREACHED - board_init_f() does not return */
1163
Scott Wood4b919722012-09-20 16:35:21 -05001164#ifndef MINIMAL_SPL
wdenk42d1f032003-10-15 23:53:47 +00001165 .globl _start_of_vectors
1166_start_of_vectors:
Andy Fleming61a21e92007-08-14 01:34:21 -05001167
wdenk42d1f032003-10-15 23:53:47 +00001168/* Critical input. */
Andy Fleming61a21e92007-08-14 01:34:21 -05001169 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
1170
1171/* Machine check */
1172 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
wdenk42d1f032003-10-15 23:53:47 +00001173
1174/* Data Storage exception. */
1175 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
1176
1177/* Instruction Storage exception. */
1178 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
1179
1180/* External Interrupt exception. */
Andy Fleming61a21e92007-08-14 01:34:21 -05001181 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
wdenk42d1f032003-10-15 23:53:47 +00001182
1183/* Alignment exception. */
wdenk42d1f032003-10-15 23:53:47 +00001184Alignment:
Rafal Jaworowski02032e82007-06-22 14:58:04 +02001185 EXCEPTION_PROLOG(SRR0, SRR1)
wdenk42d1f032003-10-15 23:53:47 +00001186 mfspr r4,DAR
1187 stw r4,_DAR(r21)
1188 mfspr r5,DSISR
1189 stw r5,_DSISR(r21)
1190 addi r3,r1,STACK_FRAME_OVERHEAD
Scott Wood96d2bb92015-04-07 20:20:00 -05001191 EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException,
1192 MSR_KERNEL, COPY_EE)
wdenk42d1f032003-10-15 23:53:47 +00001193
1194/* Program check exception */
wdenk42d1f032003-10-15 23:53:47 +00001195ProgramCheck:
Rafal Jaworowski02032e82007-06-22 14:58:04 +02001196 EXCEPTION_PROLOG(SRR0, SRR1)
wdenk42d1f032003-10-15 23:53:47 +00001197 addi r3,r1,STACK_FRAME_OVERHEAD
Scott Wood96d2bb92015-04-07 20:20:00 -05001198 EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException,
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +01001199 MSR_KERNEL, COPY_EE)
wdenk42d1f032003-10-15 23:53:47 +00001200
1201 /* No FPU on MPC85xx. This exception is not supposed to happen.
1202 */
1203 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
Scott Woodd87a2ad2015-04-07 20:20:01 -05001204 STD_EXCEPTION(0x0900, SystemCall, UnknownException)
wdenk343117b2005-05-13 22:49:36 +00001205 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
1206 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
1207 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
wdenk42d1f032003-10-15 23:53:47 +00001208
wdenk343117b2005-05-13 22:49:36 +00001209 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
1210 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
wdenk42d1f032003-10-15 23:53:47 +00001211
wdenk343117b2005-05-13 22:49:36 +00001212 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
wdenk42d1f032003-10-15 23:53:47 +00001213
wdenk343117b2005-05-13 22:49:36 +00001214 .globl _end_of_vectors
wdenk42d1f032003-10-15 23:53:47 +00001215_end_of_vectors:
1216
1217
Andy Fleming61a21e92007-08-14 01:34:21 -05001218 . = . + (0x100 - ( . & 0xff )) /* align for debug */
wdenk42d1f032003-10-15 23:53:47 +00001219
1220/*
1221 * This code finishes saving the registers to the exception frame
1222 * and jumps to the appropriate handler for the exception.
1223 * Register r21 is pointer into trap frame, r1 has new stack pointer.
Scott Wood96d2bb92015-04-07 20:20:00 -05001224 * r23 is the address of the handler.
wdenk42d1f032003-10-15 23:53:47 +00001225 */
1226 .globl transfer_to_handler
1227transfer_to_handler:
wdenk42d1f032003-10-15 23:53:47 +00001228 SAVE_GPR(7, r21)
1229 SAVE_4GPRS(8, r21)
1230 SAVE_8GPRS(12, r21)
1231 SAVE_8GPRS(24, r21)
1232
wdenk42d1f032003-10-15 23:53:47 +00001233 li r22,0
1234 stw r22,RESULT(r21)
1235 mtspr SPRG2,r22 /* r1 is now kernel sp */
1236
Scott Wood96d2bb92015-04-07 20:20:00 -05001237 mtctr r23 /* virtual address of handler */
1238 mtmsr r20
1239 bctrl
wdenk42d1f032003-10-15 23:53:47 +00001240
1241int_return:
1242 mfmsr r28 /* Disable interrupts */
1243 li r4,0
1244 ori r4,r4,MSR_EE
1245 andc r28,r28,r4
1246 SYNC /* Some chip revs need this... */
1247 mtmsr r28
1248 SYNC
1249 lwz r2,_CTR(r1)
1250 lwz r0,_LINK(r1)
1251 mtctr r2
1252 mtlr r0
1253 lwz r2,_XER(r1)
1254 lwz r0,_CCR(r1)
1255 mtspr XER,r2
1256 mtcrf 0xFF,r0
1257 REST_10GPRS(3, r1)
1258 REST_10GPRS(13, r1)
1259 REST_8GPRS(23, r1)
1260 REST_GPR(31, r1)
1261 lwz r2,_NIP(r1) /* Restore environment */
1262 lwz r0,_MSR(r1)
1263 mtspr SRR0,r2
1264 mtspr SRR1,r0
1265 lwz r0,GPR0(r1)
1266 lwz r2,GPR2(r1)
1267 lwz r1,GPR1(r1)
1268 SYNC
1269 rfi
1270
wdenk42d1f032003-10-15 23:53:47 +00001271/* Cache functions.
1272*/
Matthew McClintock0a9fe8e2011-05-23 08:38:53 +00001273.globl flush_icache
1274flush_icache:
Kumar Gala54e091d2008-09-22 14:11:10 -05001275.globl invalidate_icache
wdenk42d1f032003-10-15 23:53:47 +00001276invalidate_icache:
1277 mfspr r0,L1CSR1
Andy Fleming61a21e92007-08-14 01:34:21 -05001278 ori r0,r0,L1CSR1_ICFI
1279 msync
1280 isync
wdenk42d1f032003-10-15 23:53:47 +00001281 mtspr L1CSR1,r0
1282 isync
Andy Fleming61a21e92007-08-14 01:34:21 -05001283 blr /* entire I cache */
wdenk42d1f032003-10-15 23:53:47 +00001284
Kumar Gala54e091d2008-09-22 14:11:10 -05001285.globl invalidate_dcache
wdenk42d1f032003-10-15 23:53:47 +00001286invalidate_dcache:
1287 mfspr r0,L1CSR0
Andy Fleming61a21e92007-08-14 01:34:21 -05001288 ori r0,r0,L1CSR0_DCFI
wdenk42d1f032003-10-15 23:53:47 +00001289 msync
1290 isync
1291 mtspr L1CSR0,r0
1292 isync
1293 blr
1294
1295 .globl icache_enable
1296icache_enable:
1297 mflr r8
1298 bl invalidate_icache
1299 mtlr r8
1300 isync
1301 mfspr r4,L1CSR1
1302 ori r4,r4,0x0001
1303 oris r4,r4,0x0001
1304 mtspr L1CSR1,r4
1305 isync
1306 blr
1307
1308 .globl icache_disable
1309icache_disable:
1310 mfspr r0,L1CSR1
Andy Fleming61a21e92007-08-14 01:34:21 -05001311 lis r3,0
1312 ori r3,r3,L1CSR1_ICE
1313 andc r0,r0,r3
wdenk42d1f032003-10-15 23:53:47 +00001314 mtspr L1CSR1,r0
1315 isync
1316 blr
1317
1318 .globl icache_status
1319icache_status:
1320 mfspr r3,L1CSR1
Andy Fleming61a21e92007-08-14 01:34:21 -05001321 andi. r3,r3,L1CSR1_ICE
wdenk42d1f032003-10-15 23:53:47 +00001322 blr
1323
1324 .globl dcache_enable
1325dcache_enable:
1326 mflr r8
1327 bl invalidate_dcache
1328 mtlr r8
1329 isync
1330 mfspr r0,L1CSR0
1331 ori r0,r0,0x0001
1332 oris r0,r0,0x0001
1333 msync
1334 isync
1335 mtspr L1CSR0,r0
1336 isync
1337 blr
1338
1339 .globl dcache_disable
1340dcache_disable:
Andy Fleming61a21e92007-08-14 01:34:21 -05001341 mfspr r3,L1CSR0
1342 lis r4,0
1343 ori r4,r4,L1CSR0_DCE
1344 andc r3,r3,r4
Kumar Gala45a68132011-01-05 10:33:46 -06001345 mtspr L1CSR0,r3
wdenk42d1f032003-10-15 23:53:47 +00001346 isync
1347 blr
1348
1349 .globl dcache_status
1350dcache_status:
1351 mfspr r3,L1CSR0
Andy Fleming61a21e92007-08-14 01:34:21 -05001352 andi. r3,r3,L1CSR0_DCE
wdenk42d1f032003-10-15 23:53:47 +00001353 blr
1354
wdenk42d1f032003-10-15 23:53:47 +00001355 .globl get_pvr
1356get_pvr:
Andy Fleming61a21e92007-08-14 01:34:21 -05001357 mfspr r3,PVR
wdenk42d1f032003-10-15 23:53:47 +00001358 blr
1359
wdenk97d80fc2004-06-09 00:34:46 +00001360 .globl get_svr
1361get_svr:
Andy Fleming61a21e92007-08-14 01:34:21 -05001362 mfspr r3,SVR
wdenk97d80fc2004-06-09 00:34:46 +00001363 blr
1364
wdenk42d1f032003-10-15 23:53:47 +00001365/*------------------------------------------------------------------------------- */
1366/* Function: in8 */
1367/* Description: Input 8 bits */
1368/*------------------------------------------------------------------------------- */
1369 .globl in8
1370in8:
1371 lbz r3,0x0000(r3)
1372 blr
1373
1374/*------------------------------------------------------------------------------- */
1375/* Function: out8 */
1376/* Description: Output 8 bits */
1377/*------------------------------------------------------------------------------- */
1378 .globl out8
1379out8:
1380 stb r4,0x0000(r3)
Ed Swarthout1487adb2007-09-26 16:35:54 -05001381 sync
wdenk42d1f032003-10-15 23:53:47 +00001382 blr
1383
1384/*------------------------------------------------------------------------------- */
1385/* Function: out16 */
1386/* Description: Output 16 bits */
1387/*------------------------------------------------------------------------------- */
1388 .globl out16
1389out16:
1390 sth r4,0x0000(r3)
Ed Swarthout1487adb2007-09-26 16:35:54 -05001391 sync
wdenk42d1f032003-10-15 23:53:47 +00001392 blr
1393
1394/*------------------------------------------------------------------------------- */
1395/* Function: out16r */
1396/* Description: Byte reverse and output 16 bits */
1397/*------------------------------------------------------------------------------- */
1398 .globl out16r
1399out16r:
1400 sthbrx r4,r0,r3
Ed Swarthout1487adb2007-09-26 16:35:54 -05001401 sync
wdenk42d1f032003-10-15 23:53:47 +00001402 blr
1403
1404/*------------------------------------------------------------------------------- */
1405/* Function: out32 */
1406/* Description: Output 32 bits */
1407/*------------------------------------------------------------------------------- */
1408 .globl out32
1409out32:
1410 stw r4,0x0000(r3)
Ed Swarthout1487adb2007-09-26 16:35:54 -05001411 sync
wdenk42d1f032003-10-15 23:53:47 +00001412 blr
1413
1414/*------------------------------------------------------------------------------- */
1415/* Function: out32r */
1416/* Description: Byte reverse and output 32 bits */
1417/*------------------------------------------------------------------------------- */
1418 .globl out32r
1419out32r:
1420 stwbrx r4,r0,r3
Ed Swarthout1487adb2007-09-26 16:35:54 -05001421 sync
wdenk42d1f032003-10-15 23:53:47 +00001422 blr
1423
1424/*------------------------------------------------------------------------------- */
1425/* Function: in16 */
1426/* Description: Input 16 bits */
1427/*------------------------------------------------------------------------------- */
1428 .globl in16
1429in16:
1430 lhz r3,0x0000(r3)
1431 blr
1432
1433/*------------------------------------------------------------------------------- */
1434/* Function: in16r */
1435/* Description: Input 16 bits and byte reverse */
1436/*------------------------------------------------------------------------------- */
1437 .globl in16r
1438in16r:
1439 lhbrx r3,r0,r3
1440 blr
1441
1442/*------------------------------------------------------------------------------- */
1443/* Function: in32 */
1444/* Description: Input 32 bits */
1445/*------------------------------------------------------------------------------- */
1446 .globl in32
1447in32:
1448 lwz 3,0x0000(3)
1449 blr
1450
1451/*------------------------------------------------------------------------------- */
1452/* Function: in32r */
1453/* Description: Input 32 bits and byte reverse */
1454/*------------------------------------------------------------------------------- */
1455 .globl in32r
1456in32r:
1457 lwbrx r3,r0,r3
1458 blr
Scott Wood4b919722012-09-20 16:35:21 -05001459#endif /* !MINIMAL_SPL */
wdenk42d1f032003-10-15 23:53:47 +00001460
wdenk42d1f032003-10-15 23:53:47 +00001461/*------------------------------------------------------------------------------*/
1462
1463/*
Kumar Galad30f9042009-09-11 11:27:00 -05001464 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
1465 */
1466 .globl write_tlb
1467write_tlb:
1468 mtspr MAS0,r3
1469 mtspr MAS1,r4
1470 mtspr MAS2,r5
1471 mtspr MAS3,r6
1472#ifdef CONFIG_ENABLE_36BIT_PHYS
1473 mtspr MAS7,r7
1474#endif
1475 li r3,0
1476#ifdef CONFIG_SYS_BOOK3E_HV
1477 mtspr MAS8,r3
1478#endif
1479 isync
1480 tlbwe
1481 msync
1482 isync
1483 blr
1484
1485/*
wdenk42d1f032003-10-15 23:53:47 +00001486 * void relocate_code (addr_sp, gd, addr_moni)
1487 *
1488 * This "function" does not return, instead it continues in RAM
1489 * after relocating the monitor code.
1490 *
1491 * r3 = dest
1492 * r4 = src
1493 * r5 = length in bytes
1494 * r6 = cachelinesize
1495 */
1496 .globl relocate_code
1497relocate_code:
Andy Fleming61a21e92007-08-14 01:34:21 -05001498 mr r1,r3 /* Set new stack pointer */
1499 mr r9,r4 /* Save copy of Init Data pointer */
1500 mr r10,r5 /* Save copy of Destination Address */
wdenk42d1f032003-10-15 23:53:47 +00001501
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001502 GET_GOT
Prabhakar Kushwaha651fcf62014-04-08 19:12:31 +05301503#ifndef CONFIG_SPL_SKIP_RELOCATE
Andy Fleming61a21e92007-08-14 01:34:21 -05001504 mr r3,r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001505 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1506 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
wdenk42d1f032003-10-15 23:53:47 +00001507 lwz r5,GOT(__init_end)
1508 sub r5,r5,r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001509 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
wdenk42d1f032003-10-15 23:53:47 +00001510
1511 /*
1512 * Fix GOT pointer:
1513 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001514 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
wdenk42d1f032003-10-15 23:53:47 +00001515 *
1516 * Offset:
1517 */
Andy Fleming61a21e92007-08-14 01:34:21 -05001518 sub r15,r10,r4
wdenk42d1f032003-10-15 23:53:47 +00001519
1520 /* First our own GOT */
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001521 add r12,r12,r15
wdenk42d1f032003-10-15 23:53:47 +00001522 /* the the one used by the C code */
Andy Fleming61a21e92007-08-14 01:34:21 -05001523 add r30,r30,r15
wdenk42d1f032003-10-15 23:53:47 +00001524
1525 /*
1526 * Now relocate code
1527 */
1528
1529 cmplw cr1,r3,r4
1530 addi r0,r5,3
1531 srwi. r0,r0,2
1532 beq cr1,4f /* In place copy is not necessary */
1533 beq 7f /* Protect against 0 count */
1534 mtctr r0
1535 bge cr1,2f
1536
1537 la r8,-4(r4)
1538 la r7,-4(r3)
15391: lwzu r0,4(r8)
1540 stwu r0,4(r7)
1541 bdnz 1b
1542 b 4f
1543
15442: slwi r0,r0,2
1545 add r8,r4,r0
1546 add r7,r3,r0
15473: lwzu r0,-4(r8)
1548 stwu r0,-4(r7)
1549 bdnz 3b
1550
1551/*
1552 * Now flush the cache: note that we must start from a cache aligned
1553 * address. Otherwise we might miss one cache line.
1554 */
15554: cmpwi r6,0
1556 add r5,r3,r5
1557 beq 7f /* Always flush prefetch queue in any case */
1558 subi r0,r6,1
1559 andc r3,r3,r0
1560 mr r4,r3
15615: dcbst 0,r4
1562 add r4,r4,r6
1563 cmplw r4,r5
1564 blt 5b
1565 sync /* Wait for all dcbst to complete on bus */
1566 mr r4,r3
15676: icbi 0,r4
1568 add r4,r4,r6
1569 cmplw r4,r5
1570 blt 6b
15717: sync /* Wait for all icbi to complete on bus */
1572 isync
1573
1574/*
1575 * We are done. Do not return, instead branch to second part of board
1576 * initialization, now running from RAM.
1577 */
1578
Scott Wood96d2bb92015-04-07 20:20:00 -05001579 addi r0,r10,in_ram - _start
Prabhakar Kushwaha689f00f2012-04-29 23:56:43 +00001580
1581 /*
1582 * As IVPR is going to point RAM address,
1583 * Make sure IVOR15 has valid opcode to support debugger
1584 */
1585 mtspr IVOR15,r0
1586
1587 /*
1588 * Re-point the IVPR at RAM
1589 */
1590 mtspr IVPR,r10
1591
wdenk42d1f032003-10-15 23:53:47 +00001592 mtlr r0
1593 blr /* NEVER RETURNS! */
Prabhakar Kushwaha651fcf62014-04-08 19:12:31 +05301594#endif
Andy Fleming61a21e92007-08-14 01:34:21 -05001595 .globl in_ram
wdenk42d1f032003-10-15 23:53:47 +00001596in_ram:
1597
1598 /*
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +01001599 * Relocation Function, r12 point to got2+0x8000
wdenk42d1f032003-10-15 23:53:47 +00001600 *
1601 * Adjust got2 pointers, no need to check for 0, this code
1602 * already puts a few entries in the table.
1603 */
1604 li r0,__got2_entries@sectoff@l
1605 la r3,GOT(_GOT2_TABLE_)
1606 lwz r11,GOT(_GOT2_TABLE_)
1607 mtctr r0
1608 sub r11,r3,r11
1609 addi r3,r3,-4
16101: lwzu r0,4(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02001611 cmpwi r0,0
1612 beq- 2f
wdenk42d1f032003-10-15 23:53:47 +00001613 add r0,r0,r11
1614 stw r0,0(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +020016152: bdnz 1b
wdenk42d1f032003-10-15 23:53:47 +00001616
1617 /*
1618 * Now adjust the fixups and the pointers to the fixups
1619 * in case we need to move ourselves again.
1620 */
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02001621 li r0,__fixup_entries@sectoff@l
wdenk42d1f032003-10-15 23:53:47 +00001622 lwz r3,GOT(_FIXUP_TABLE_)
1623 cmpwi r0,0
1624 mtctr r0
1625 addi r3,r3,-4
1626 beq 4f
16273: lwzu r4,4(r3)
1628 lwzux r0,r4,r11
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +02001629 cmpwi r0,0
wdenk42d1f032003-10-15 23:53:47 +00001630 add r0,r0,r11
Joakim Tjernlund34bbf612010-11-04 19:02:00 +01001631 stw r4,0(r3)
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +02001632 beq- 5f
wdenk42d1f032003-10-15 23:53:47 +00001633 stw r0,0(r4)
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +020016345: bdnz 3b
wdenk42d1f032003-10-15 23:53:47 +000016354:
1636clear_bss:
1637 /*
1638 * Now clear BSS segment
1639 */
1640 lwz r3,GOT(__bss_start)
Simon Glass3929fb02013-03-14 06:54:53 +00001641 lwz r4,GOT(__bss_end)
wdenk42d1f032003-10-15 23:53:47 +00001642
Andy Fleming61a21e92007-08-14 01:34:21 -05001643 cmplw 0,r3,r4
wdenk42d1f032003-10-15 23:53:47 +00001644 beq 6f
1645
Andy Fleming61a21e92007-08-14 01:34:21 -05001646 li r0,0
wdenk42d1f032003-10-15 23:53:47 +000016475:
Andy Fleming61a21e92007-08-14 01:34:21 -05001648 stw r0,0(r3)
1649 addi r3,r3,4
1650 cmplw 0,r3,r4
Ying Zhang67ad0d52013-06-07 17:25:16 +08001651 blt 5b
wdenk42d1f032003-10-15 23:53:47 +000016526:
1653
Andy Fleming61a21e92007-08-14 01:34:21 -05001654 mr r3,r9 /* Init Data pointer */
1655 mr r4,r10 /* Destination Address */
wdenk42d1f032003-10-15 23:53:47 +00001656 bl board_init_r
1657
Scott Wood4b919722012-09-20 16:35:21 -05001658#ifndef MINIMAL_SPL
wdenk42d1f032003-10-15 23:53:47 +00001659 /*
1660 * Copy exception vector code to low memory
1661 *
1662 * r3: dest_addr
1663 * r7: source address, r8: end address, r9: target address
1664 */
wdenk343117b2005-05-13 22:49:36 +00001665 .globl trap_init
wdenk42d1f032003-10-15 23:53:47 +00001666trap_init:
Scott Woode1bfd1c2015-04-23 20:01:56 -05001667 mflr r11
1668 bl _GLOBAL_OFFSET_TABLE_-4
1669 mflr r12
1670
Scott Wood96d2bb92015-04-07 20:20:00 -05001671 /* Update IVORs as per relocation */
1672 mtspr IVPR,r3
wdenk42d1f032003-10-15 23:53:47 +00001673
Scott Woode1bfd1c2015-04-23 20:01:56 -05001674 lwz r4,CriticalInput@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001675 mtspr IVOR0,r4 /* 0: Critical input */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001676 lwz r4,MachineCheck@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001677 mtspr IVOR1,r4 /* 1: Machine check */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001678 lwz r4,DataStorage@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001679 mtspr IVOR2,r4 /* 2: Data storage */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001680 lwz r4,InstStorage@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001681 mtspr IVOR3,r4 /* 3: Instruction storage */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001682 lwz r4,ExtInterrupt@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001683 mtspr IVOR4,r4 /* 4: External interrupt */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001684 lwz r4,Alignment@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001685 mtspr IVOR5,r4 /* 5: Alignment */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001686 lwz r4,ProgramCheck@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001687 mtspr IVOR6,r4 /* 6: Program check */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001688 lwz r4,FPUnavailable@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001689 mtspr IVOR7,r4 /* 7: floating point unavailable */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001690 lwz r4,SystemCall@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001691 mtspr IVOR8,r4 /* 8: System call */
Prabhakar Kushwaha64829ba2012-02-14 22:49:49 +00001692 /* 9: Auxiliary processor unavailable(unsupported) */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001693 lwz r4,Decrementer@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001694 mtspr IVOR10,r4 /* 10: Decrementer */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001695 lwz r4,IntervalTimer@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001696 mtspr IVOR11,r4 /* 11: Interval timer */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001697 lwz r4,WatchdogTimer@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001698 mtspr IVOR12,r4 /* 12: Watchdog timer */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001699 lwz r4,DataTLBError@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001700 mtspr IVOR13,r4 /* 13: Data TLB error */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001701 lwz r4,InstructionTLBError@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001702 mtspr IVOR14,r4 /* 14: Instruction TLB error */
Scott Woode1bfd1c2015-04-23 20:01:56 -05001703 lwz r4,DebugBreakpoint@got(r12)
Scott Wood96d2bb92015-04-07 20:20:00 -05001704 mtspr IVOR15,r4 /* 15: Debug */
Prabhakar Kushwaha64829ba2012-02-14 22:49:49 +00001705
Scott Woode1bfd1c2015-04-23 20:01:56 -05001706 mtlr r11
wdenk42d1f032003-10-15 23:53:47 +00001707 blr
1708
wdenk42d1f032003-10-15 23:53:47 +00001709.globl unlock_ram_in_cache
1710unlock_ram_in_cache:
1711 /* invalidate the INIT_RAM section */
Kumar Galaa38a5b62008-10-23 01:47:37 -05001712 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1713 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
Kumar Galab009f3e2008-01-08 01:22:21 -06001714 mfspr r4,L1CFG0
1715 andi. r4,r4,0x1ff
1716 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
Andy Fleming61a21e92007-08-14 01:34:21 -05001717 mtctr r4
Kumar Gala2b22fa42008-02-27 16:30:47 -060017181: dcbi r0,r3
York Suna71d45d2013-04-05 13:07:13 +00001719 dcblc r0,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001720 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
wdenk42d1f032003-10-15 23:53:47 +00001721 bdnz 1b
Kumar Gala2b22fa42008-02-27 16:30:47 -06001722 sync
Andy Fleming21fae8b2008-02-27 14:29:58 -06001723
1724 /* Invalidate the TLB entries for the cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001725 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1726 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
Andy Fleming21fae8b2008-02-27 14:29:58 -06001727 tlbivax 0,r3
1728 addi r3,r3,0x1000
1729 tlbivax 0,r3
1730 addi r3,r3,0x1000
1731 tlbivax 0,r3
1732 addi r3,r3,0x1000
1733 tlbivax 0,r3
wdenk42d1f032003-10-15 23:53:47 +00001734 isync
1735 blr
Kumar Gala54e091d2008-09-22 14:11:10 -05001736
1737.globl flush_dcache
1738flush_dcache:
1739 mfspr r3,SPRN_L1CFG0
1740
1741 rlwinm r5,r3,9,3 /* Extract cache block size */
1742 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1743 * are currently defined.
1744 */
1745 li r4,32
1746 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1747 * log2(number of ways)
1748 */
1749 slw r5,r4,r5 /* r5 = cache block size */
1750
1751 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1752 mulli r7,r7,13 /* An 8-way cache will require 13
1753 * loads per set.
1754 */
1755 slw r7,r7,r6
1756
1757 /* save off HID0 and set DCFA */
1758 mfspr r8,SPRN_HID0
1759 ori r9,r8,HID0_DCFA@l
1760 mtspr SPRN_HID0,r9
1761 isync
1762
1763 lis r4,0
1764 mtctr r7
1765
17661: lwz r3,0(r4) /* Load... */
1767 add r4,r4,r5
1768 bdnz 1b
1769
1770 msync
1771 lis r4,0
1772 mtctr r7
1773
17741: dcbf 0,r4 /* ...and flush. */
1775 add r4,r4,r5
1776 bdnz 1b
1777
1778 /* restore HID0 */
1779 mtspr SPRN_HID0,r8
1780 isync
1781
1782 blr
Scott Wood4b919722012-09-20 16:35:21 -05001783#endif /* !MINIMAL_SPL */