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wdenk0f8c9762002-08-19 11:57:05 +00001/*
Stefan Roese8a316c92005-08-01 16:49:12 +02002 * (C) Copyright 2000-2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
wdenk0f8c9762002-08-19 11:57:05 +00004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
Wolfgang Denk095b8a32005-08-02 17:06:17 +020037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_WALNUT 1 /* ...on a WALNUT board */
39 /* ...and on a SYCAMORE board */
wdenk0f8c9762002-08-19 11:57:05 +000040
Stefan Roese72675dc2008-06-06 15:55:21 +020041/*
42 * Include common defines/options for all AMCC eval boards
43 */
44#define CONFIG_HOSTNAME walnut
45#include "amcc-common.h"
46
wdenkc837dcb2004-01-20 23:12:12 +000047#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenk0f8c9762002-08-19 11:57:05 +000048
Wolfgang Denk095b8a32005-08-02 17:06:17 +020049#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
wdenk0f8c9762002-08-19 11:57:05 +000050
Stefan Roese72675dc2008-06-06 15:55:21 +020051/*
52 * Default environment variables
53 */
54#define CONFIG_EXTRA_ENV_SETTINGS \
55 CONFIG_AMCC_DEF_ENV \
56 CONFIG_AMCC_DEF_ENV_POWERPC \
57 CONFIG_AMCC_DEF_ENV_PPC_OLD \
58 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese8a316c92005-08-01 16:49:12 +020059 "kernel_addr=fff80000\0" \
60 "ramdisk_addr=fff80000\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +020061 ""
wdenk0f8c9762002-08-19 11:57:05 +000062
Wolfgang Denk095b8a32005-08-02 17:06:17 +020063#define CONFIG_PHY_ADDR 1 /* PHY address */
Stefan Roesea00eccf2008-05-08 11:05:15 +020064#define CONFIG_HAS_ETH0 1
Stefan Roese4f92ed52006-08-07 14:33:32 +020065
wdenk0f8c9762002-08-19 11:57:05 +000066#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
67
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050068/*
Stefan Roese72675dc2008-06-06 15:55:21 +020069 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger079a1362007-07-10 10:12:10 -050070 */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050071#define CONFIG_CMD_DATE
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050072#define CONFIG_CMD_PCI
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050073#define CONFIG_CMD_SDRAM
74#define CONFIG_CMD_SNTP
75
wdenk0f8c9762002-08-19 11:57:05 +000076#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
77
78/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
80 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
81 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
wdenk0f8c9762002-08-19 11:57:05 +000082 * The Linux BASE_BAUD define should match this configuration.
83 * baseBaud = cpuClock/(uartDivisor*16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
wdenk0f8c9762002-08-19 11:57:05 +000085 * set Linux BASE_BAUD to 403200.
86 */
Stefan Roese550650d2010-09-20 16:05:31 +020087#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
89#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
90#define CONFIG_SYS_BASE_BAUD 691200
wdenk0f8c9762002-08-19 11:57:05 +000091
Stefan Roese8a316c92005-08-01 16:49:12 +020092/*-----------------------------------------------------------------------
93 * I2C stuff
94 *-----------------------------------------------------------------------
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
wdenk0f8c9762002-08-19 11:57:05 +000097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_I2C_MULTI_EEPROMS
99#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
100#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
101#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
102#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese4f92ed52006-08-07 14:33:32 +0200103
wdenk0f8c9762002-08-19 11:57:05 +0000104/*-----------------------------------------------------------------------
105 * PCI stuff
106 *-----------------------------------------------------------------------
107 */
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200108#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
109#define PCI_HOST_FORCE 1 /* configure as pci host */
110#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenk0f8c9762002-08-19 11:57:05 +0000111
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200112#define CONFIG_PCI /* include pci support */
113#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
114#define CONFIG_PCI_PNP /* do pci plug-and-play */
115 /* resource configuration */
Stefan Roese8a316c92005-08-01 16:49:12 +0200116#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
wdenk0f8c9762002-08-19 11:57:05 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
119#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
120#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
121#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
122#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
123#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
124#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
125#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk0f8c9762002-08-19 11:57:05 +0000126
127/*-----------------------------------------------------------------------
wdenk0f8c9762002-08-19 11:57:05 +0000128 * Start addresses for the final memory configuration
129 * (Set up by the startup code)
wdenk0f8c9762002-08-19 11:57:05 +0000130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_FLASH_BASE 0xFFF80000
Stefan Roese8a316c92005-08-01 16:49:12 +0200132
133/*
134 * Define here the location of the environment variables (FLASH or NVRAM).
135 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200136 * supported for backward compatibility.
Stefan Roese8a316c92005-08-01 16:49:12 +0200137 */
138#if 1
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200139#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese8a316c92005-08-01 16:49:12 +0200140#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200141#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Stefan Roese8a316c92005-08-01 16:49:12 +0200142#endif
wdenk0f8c9762002-08-19 11:57:05 +0000143
wdenk0f8c9762002-08-19 11:57:05 +0000144/*-----------------------------------------------------------------------
145 * FLASH organization
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200148#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
Stefan Roese8a316c92005-08-01 16:49:12 +0200149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
151#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
154#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese8a316c92005-08-01 16:49:12 +0200157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_FLASH_ADDR0 0x5555
159#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
160#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
Stefan Roese8a316c92005-08-01 16:49:12 +0200161
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200162#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200163#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200165#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese8a316c92005-08-01 16:49:12 +0200166
167/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200168#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
169#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200170#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese8a316c92005-08-01 16:49:12 +0200171
wdenk0f8c9762002-08-19 11:57:05 +0000172/*-----------------------------------------------------------------------
173 * NVRAM organization
174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
176#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
wdenk0f8c9762002-08-19 11:57:05 +0000177
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200178#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200179#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
180#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
wdenk0f8c9762002-08-19 11:57:05 +0000182#endif
Stefan Roese8a316c92005-08-01 16:49:12 +0200183
wdenk0f8c9762002-08-19 11:57:05 +0000184/*-----------------------------------------------------------------------
Stefan Roese8a316c92005-08-01 16:49:12 +0200185 * External Bus Controller (EBC) Setup
wdenk0f8c9762002-08-19 11:57:05 +0000186 */
187
Stefan Roese8a316c92005-08-01 16:49:12 +0200188/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_EBC_PB0AP 0x9B015480
190#define CONFIG_SYS_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_EBC_PB1AP 0x02815480
193#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_EBC_PB2AP 0x04815A80
196#define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese8a316c92005-08-01 16:49:12 +0200197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_EBC_PB3AP 0x01815280
199#define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese8a316c92005-08-01 16:49:12 +0200200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_EBC_PB7AP 0x01815280
202#define CONFIG_SYS_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenk0f8c9762002-08-19 11:57:05 +0000203
204/*-----------------------------------------------------------------------
Stefan Roese8a316c92005-08-01 16:49:12 +0200205 * External peripheral base address
206 *-----------------------------------------------------------------------
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
209#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
210#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
Stefan Roese8a316c92005-08-01 16:49:12 +0200211
212/*-----------------------------------------------------------------------
213 * Definitions for initial stack pointer and data area
wdenk0f8c9762002-08-19 11:57:05 +0000214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
wdenk0f8c9762002-08-19 11:57:05 +0000216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
218#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
219#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
220#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
221#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000222
223/*-----------------------------------------------------------------------
224 * Definitions for Serial Presence Detect EEPROM address
225 * (to get SDRAM settings)
226 */
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200227#define SPD_EEPROM_ADDRESS 0x50
wdenk0f8c9762002-08-19 11:57:05 +0000228
wdenk0f8c9762002-08-19 11:57:05 +0000229#endif /* __CONFIG_H */