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Stelian Pop39cf4802008-05-09 21:57:18 +02001/*
2 * Driver for AT91/AT32 LCD Controller
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/io.h>
Stelian Pop39cf4802008-05-09 21:57:18 +020027#include <asm/arch/gpio.h>
28#include <asm/arch/clk.h>
29#include <lcd.h>
30#include <atmel_lcdc.h>
31
32int lcd_line_length;
33int lcd_color_fg;
34int lcd_color_bg;
35
36void *lcd_base; /* Start of framebuffer memory */
37void *lcd_console_address; /* Start of console buffer */
38
39short console_col;
40short console_row;
41
42/* configurable parameters */
43#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
44#define ATMEL_LCDC_DMA_BURST_LEN 8
45
46#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9)
47#define ATMEL_LCDC_FIFO_SIZE 2048
48#else
49#define ATMEL_LCDC_FIFO_SIZE 512
50#endif
51
52#define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
53#define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
54
55void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
56{
57#if defined(CONFIG_ATMEL_LCD_BGR555)
58 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
59 (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
60#else
61 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
62 (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
63#endif
64}
65
66void lcd_ctrl_init(void *lcdbase)
67{
68 unsigned long value;
69
70 /* Turn off the LCD controller and the DMA controller */
71 lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
72 1 << ATMEL_LCDC_GUARDT_OFFSET);
73
74 /* Wait for the LCDC core to become idle */
75 while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
76 udelay(10);
77
78 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
79
80 /* Reset LCDC DMA */
81 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
82
83 /* ...set frame size and burst length = 8 words (?) */
84 value = (panel_info.vl_col * panel_info.vl_row *
85 NBITS(panel_info.vl_bpix)) / 32;
86 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
87 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
88
89 /* Set pixel clock */
90 value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
91 if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
92 value++;
93 value = (value / 2) - 1;
94
95 if (!value) {
96 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
97 } else
98 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
99 value << ATMEL_LCDC_CLKVAL_OFFSET);
100
101 /* Initialize control register 2 */
Stefan Roesef2302d42008-08-06 14:05:38 +0200102#ifdef CONFIG_AVR32
103 value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
104#else
Stelian Pop39cf4802008-05-09 21:57:18 +0200105 value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
Stefan Roesef2302d42008-08-06 14:05:38 +0200106#endif
Stelian Pop39cf4802008-05-09 21:57:18 +0200107 if (panel_info.vl_tft)
108 value |= ATMEL_LCDC_DISTYPE_TFT;
109
Haavard Skinnemoen70dbc542008-09-01 16:21:19 +0200110 value |= panel_info.vl_sync;
Stelian Pop39cf4802008-05-09 21:57:18 +0200111 value |= (panel_info.vl_bpix << 5);
112 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
113
114 /* Vertical timing */
115 value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
116 value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
117 value |= panel_info.vl_lower_margin;
118 lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
119
120 /* Horizontal timing */
121 value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
122 value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
123 value |= (panel_info.vl_left_margin - 1);
124 lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
125
126 /* Display size */
127 value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
128 value |= panel_info.vl_row - 1;
129 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
130
131 /* FIFO Threshold: Use formula from data sheet */
132 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
133 lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
134
135 /* Toggle LCD_MODE every frame */
136 lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
137
138 /* Disable all interrupts */
139 lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
140
141 /* Set contrast */
142 value = ATMEL_LCDC_PS_DIV8 |
143 ATMEL_LCDC_POL_POSITIVE |
144 ATMEL_LCDC_ENA_PWMENABLE;
145 lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
146 lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
147
148 /* Set framebuffer DMA base address and pixel offset */
149 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
150
151 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
152 lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
153 (1 << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
154}
155
156ulong calc_fbsize(void)
157{
158 return ((panel_info.vl_col * panel_info.vl_row *
159 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
160}