blob: df72516239dc716fcd622b1302f1ac134fa8f364 [file] [log] [blame]
Michal Simek84c72042015-01-15 10:01:51 +01001/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
Michal Simek679b9942015-09-30 17:26:55 +02009#include <sata.h>
Michal Simek6fe6f132015-07-23 13:27:40 +020010#include <ahci.h>
11#include <scsi.h>
Michal Simekb72894f2016-04-22 14:28:54 +020012#include <malloc.h>
Michal Simek0785dfd2015-11-05 08:34:35 +010013#include <asm/arch/clk.h>
Michal Simek84c72042015-01-15 10:01:51 +010014#include <asm/arch/hardware.h>
15#include <asm/arch/sys_proto.h>
16#include <asm/io.h>
Siva Durga Prasad Paladugu16fa00a2015-08-04 13:03:26 +053017#include <usb.h>
18#include <dwc3-uboot.h>
Michal Simek47e60cb2016-02-01 15:05:58 +010019#include <zynqmppl.h>
Michal Simek6919b4b2016-04-22 11:48:49 +020020#include <i2c.h>
Michal Simek9feff382016-09-01 11:16:40 +020021#include <g_dnl.h>
Michal Simek84c72042015-01-15 10:01:51 +010022
23DECLARE_GLOBAL_DATA_PTR;
24
Michal Simek47e60cb2016-02-01 15:05:58 +010025#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
26 !defined(CONFIG_SPL_BUILD)
27static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
28
29static const struct {
30 uint32_t id;
31 char *name;
32} zynqmp_devices[] = {
33 {
34 .id = 0x10,
35 .name = "3eg",
36 },
37 {
38 .id = 0x11,
39 .name = "2eg",
40 },
41 {
42 .id = 0x20,
43 .name = "5ev",
44 },
45 {
46 .id = 0x21,
47 .name = "4ev",
48 },
49 {
50 .id = 0x30,
51 .name = "7ev",
52 },
53 {
54 .id = 0x38,
55 .name = "9eg",
56 },
57 {
58 .id = 0x39,
59 .name = "6eg",
60 },
61 {
62 .id = 0x40,
63 .name = "11eg",
64 },
65 {
66 .id = 0x50,
67 .name = "15eg",
68 },
69 {
70 .id = 0x58,
71 .name = "19eg",
72 },
73 {
74 .id = 0x59,
75 .name = "17eg",
76 },
77};
78
79static int chip_id(void)
80{
81 struct pt_regs regs;
82 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
83 regs.regs[1] = 0;
84 regs.regs[2] = 0;
85 regs.regs[3] = 0;
86
87 smc_call(&regs);
88
Soren Brinkmann0cba6ab2016-09-29 11:44:41 -070089 /*
90 * SMC returns:
91 * regs[0][31:0] = status of the operation
92 * regs[0][63:32] = CSU.IDCODE register
93 * regs[1][31:0] = CSU.version register
94 */
95 regs.regs[0] = upper_32_bits(regs.regs[0]);
96 regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
97 ZYNQMP_CSU_IDCODE_SVD_MASK;
98 regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
99
Michal Simek47e60cb2016-02-01 15:05:58 +0100100 return regs.regs[0];
101}
102
103static char *zynqmp_get_silicon_idcode_name(void)
104{
105 uint32_t i, id;
106
107 id = chip_id();
108 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
109 if (zynqmp_devices[i].id == id)
110 return zynqmp_devices[i].name;
111 }
112 return "unknown";
113}
114#endif
115
116#define ZYNQMP_VERSION_SIZE 9
117
Michal Simek84c72042015-01-15 10:01:51 +0100118int board_init(void)
119{
Michal Simeka0736ef2015-06-22 14:31:06 +0200120 printf("EL Level:\tEL%d\n", current_el());
121
Michal Simek47e60cb2016-02-01 15:05:58 +0100122#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
123 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
124 defined(CONFIG_SPL_BUILD))
125 if (current_el() != 3) {
126 static char version[ZYNQMP_VERSION_SIZE];
127
128 strncat(version, "xczu", ZYNQMP_VERSION_SIZE);
129 zynqmppl.name = strncat(version,
130 zynqmp_get_silicon_idcode_name(),
131 ZYNQMP_VERSION_SIZE);
132 printf("Chip ID:\t%s\n", zynqmppl.name);
133 fpga_init();
134 fpga_add(fpga_xilinx, &zynqmppl);
135 }
136#endif
137
Michal Simek84c72042015-01-15 10:01:51 +0100138 return 0;
139}
140
141int board_early_init_r(void)
142{
143 u32 val;
144
Michal Simek0785dfd2015-11-05 08:34:35 +0100145 if (current_el() == 3) {
146 val = readl(&crlapb_base->timestamp_ref_ctrl);
147 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
148 writel(val, &crlapb_base->timestamp_ref_ctrl);
Michal Simek84c72042015-01-15 10:01:51 +0100149
Michal Simek0785dfd2015-11-05 08:34:35 +0100150 /* Program freq register in System counter */
151 writel(zynqmp_get_system_timer_freq(),
152 &iou_scntr_secure->base_frequency_id_register);
153 /* And enable system counter */
154 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
155 &iou_scntr_secure->counter_control_register);
156 }
Michal Simek84c72042015-01-15 10:01:51 +0100157 /* Program freq register in System counter and enable system counter */
158 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
159 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
160 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
161 &iou_scntr->counter_control_register);
162
163 return 0;
164}
165
Michal Simek6919b4b2016-04-22 11:48:49 +0200166int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
167{
168#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
169 defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
170 defined(CONFIG_ZYNQ_EEPROM_BUS)
171 i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
172
173 if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
174 CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
175 ethaddr, 6))
176 printf("I2C EEPROM MAC address read failed\n");
177#endif
178
179 return 0;
180}
181
Michal Simek8d59d7f2016-02-08 09:34:53 +0100182#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
183/*
184 * fdt_get_reg - Fill buffer by information from DT
185 */
186static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf,
187 const u32 *cell, int n)
188{
189 int i = 0, b, banks;
190 int parent_offset = fdt_parent_offset(fdt, nodeoffset);
191 int address_cells = fdt_address_cells(fdt, parent_offset);
192 int size_cells = fdt_size_cells(fdt, parent_offset);
193 char *p = buf;
Michal Simek658b3a52016-04-01 15:55:47 +0200194 u64 val;
195 u64 vals;
Michal Simek8d59d7f2016-02-08 09:34:53 +0100196
197 debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n",
198 __func__, address_cells, size_cells, buf, cell);
199
200 /* Check memory bank setup */
201 banks = n % (address_cells + size_cells);
202 if (banks)
203 panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n",
204 n, address_cells, size_cells);
205
206 banks = n / (address_cells + size_cells);
207
208 for (b = 0; b < banks; b++) {
209 debug("%s: Bank #%d:\n", __func__, b);
210 if (address_cells == 2) {
211 val = cell[i + 1];
212 val <<= 32;
213 val |= cell[i];
214 val = fdt64_to_cpu(val);
215 debug("%s: addr64=%llx, ptr=%p, cell=%p\n",
216 __func__, val, p, &cell[i]);
217 *(phys_addr_t *)p = val;
218 } else {
219 debug("%s: addr32=%x, ptr=%p\n",
220 __func__, fdt32_to_cpu(cell[i]), p);
221 *(phys_addr_t *)p = fdt32_to_cpu(cell[i]);
222 }
223 p += sizeof(phys_addr_t);
224 i += address_cells;
225
226 debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i,
227 sizeof(phys_addr_t));
228
229 if (size_cells == 2) {
230 vals = cell[i + 1];
231 vals <<= 32;
232 vals |= cell[i];
233 vals = fdt64_to_cpu(vals);
234
235 debug("%s: size64=%llx, ptr=%p, cell=%p\n",
236 __func__, vals, p, &cell[i]);
237 *(phys_size_t *)p = vals;
238 } else {
239 debug("%s: size32=%x, ptr=%p\n",
240 __func__, fdt32_to_cpu(cell[i]), p);
241 *(phys_size_t *)p = fdt32_to_cpu(cell[i]);
242 }
243 p += sizeof(phys_size_t);
244 i += size_cells;
245
246 debug("%s: ps=%p, i=%x, size=%zu\n",
247 __func__, p, i, sizeof(phys_size_t));
248 }
249
250 /* Return the first address size */
251 return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t));
252}
253
254#define FDT_REG_SIZE sizeof(u32)
255/* Temp location for sharing data for storing */
256/* Up to 64-bit address + 64-bit size */
257static u8 tmp[CONFIG_NR_DRAM_BANKS * 16];
258
259void dram_init_banksize(void)
260{
261 int bank;
262
263 memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp));
264
265 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
266 debug("Bank #%d: start %llx\n", bank,
267 (unsigned long long)gd->bd->bi_dram[bank].start);
268 debug("Bank #%d: size %llx\n", bank,
269 (unsigned long long)gd->bd->bi_dram[bank].size);
270 }
271}
272
273int dram_init(void)
274{
275 int node, len;
276 const void *blob = gd->fdt_blob;
277 const u32 *cell;
278
279 memset(&tmp, 0, sizeof(tmp));
280
281 /* find or create "/memory" node. */
282 node = fdt_subnode_offset(blob, 0, "memory");
283 if (node < 0) {
284 printf("%s: Can't get memory node\n", __func__);
285 return node;
286 }
287
288 /* Get pointer to cells and lenght of it */
289 cell = fdt_getprop(blob, node, "reg", &len);
290 if (!cell) {
291 printf("%s: Can't get reg property\n", __func__);
292 return -1;
293 }
294
295 gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE);
296
Michal Simek658b3a52016-04-01 15:55:47 +0200297 debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size);
Michal Simek8d59d7f2016-02-08 09:34:53 +0100298
299 return 0;
300}
301#else
Michal Simek84c72042015-01-15 10:01:51 +0100302int dram_init(void)
303{
304 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
305
306 return 0;
307}
Michal Simek8d59d7f2016-02-08 09:34:53 +0100308#endif
Michal Simek84c72042015-01-15 10:01:51 +0100309
Michal Simek84c72042015-01-15 10:01:51 +0100310void reset_cpu(ulong addr)
311{
312}
313
Michal Simek6fe6f132015-07-23 13:27:40 +0200314#ifdef CONFIG_SCSI_AHCI_PLAT
315void scsi_init(void)
316{
Michal Simek679b9942015-09-30 17:26:55 +0200317#if defined(CONFIG_SATA_CEVA)
318 init_sata(0);
319#endif
Michal Simek6fe6f132015-07-23 13:27:40 +0200320 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
321 scsi_scan(1);
322}
323#endif
324
Michal Simek84c72042015-01-15 10:01:51 +0100325int board_late_init(void)
326{
327 u32 reg = 0;
328 u8 bootmode;
Michal Simekb72894f2016-04-22 14:28:54 +0200329 const char *mode;
330 char *new_targets;
331
332 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
333 debug("Saved variables - Skipping\n");
334 return 0;
335 }
Michal Simek84c72042015-01-15 10:01:51 +0100336
337 reg = readl(&crlapb_base->boot_mode);
338 bootmode = reg & BOOT_MODES_MASK;
339
Michal Simekfb909172015-09-20 17:20:42 +0200340 puts("Bootmode: ");
Michal Simek84c72042015-01-15 10:01:51 +0100341 switch (bootmode) {
Michal Simekd58fc122016-08-19 14:14:52 +0200342 case USB_MODE:
343 puts("USB_MODE\n");
344 mode = "usb";
345 break;
Siva Durga Prasad Paladugu0a5bcc82015-03-13 11:10:26 +0530346 case JTAG_MODE:
Michal Simekfb909172015-09-20 17:20:42 +0200347 puts("JTAG_MODE\n");
Michal Simekb72894f2016-04-22 14:28:54 +0200348 mode = "pxe dhcp";
Siva Durga Prasad Paladugu0a5bcc82015-03-13 11:10:26 +0530349 break;
350 case QSPI_MODE_24BIT:
351 case QSPI_MODE_32BIT:
Michal Simekb72894f2016-04-22 14:28:54 +0200352 mode = "qspi0";
Michal Simekfb909172015-09-20 17:20:42 +0200353 puts("QSPI_MODE\n");
Siva Durga Prasad Paladugu0a5bcc82015-03-13 11:10:26 +0530354 break;
Michal Simek39c56f52015-04-15 15:02:28 +0200355 case EMMC_MODE:
Michal Simek78678fe2015-10-05 15:59:38 +0200356 puts("EMMC_MODE\n");
Michal Simekb72894f2016-04-22 14:28:54 +0200357 mode = "mmc0";
Michal Simek78678fe2015-10-05 15:59:38 +0200358 break;
359 case SD_MODE:
Michal Simekfb909172015-09-20 17:20:42 +0200360 puts("SD_MODE\n");
Michal Simekb72894f2016-04-22 14:28:54 +0200361 mode = "mmc0";
Michal Simek84c72042015-01-15 10:01:51 +0100362 break;
Siva Durga Prasad Paladugue1992272016-09-21 11:45:05 +0530363 case SD1_LSHFT_MODE:
364 puts("LVL_SHFT_");
365 /* fall through */
Michal Simekaf813ac2015-10-05 10:51:12 +0200366 case SD_MODE1:
Michal Simekfb909172015-09-20 17:20:42 +0200367 puts("SD_MODE1\n");
Michal Simek2d9925b2015-11-06 10:22:37 +0100368#if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
Michal Simekb72894f2016-04-22 14:28:54 +0200369 mode = "mmc1";
370#else
371 mode = "mmc0";
Michal Simek2d9925b2015-11-06 10:22:37 +0100372#endif
Michal Simekaf813ac2015-10-05 10:51:12 +0200373 break;
374 case NAND_MODE:
Michal Simekfb909172015-09-20 17:20:42 +0200375 puts("NAND_MODE\n");
Michal Simekb72894f2016-04-22 14:28:54 +0200376 mode = "nand0";
Michal Simekaf813ac2015-10-05 10:51:12 +0200377 break;
Michal Simek84c72042015-01-15 10:01:51 +0100378 default:
Michal Simekb72894f2016-04-22 14:28:54 +0200379 mode = "";
Michal Simek84c72042015-01-15 10:01:51 +0100380 printf("Invalid Boot Mode:0x%x\n", bootmode);
381 break;
382 }
383
Michal Simekb72894f2016-04-22 14:28:54 +0200384 /*
385 * One terminating char + one byte for space between mode
386 * and default boot_targets
387 */
388 new_targets = calloc(1, strlen(mode) +
389 strlen(getenv("boot_targets")) + 2);
390
391 sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
392 setenv("boot_targets", new_targets);
393
Michal Simek84c72042015-01-15 10:01:51 +0100394 return 0;
395}
Siva Durga Prasad Paladugu84696ff2015-08-04 13:01:05 +0530396
397int checkboard(void)
398{
Michal Simek5af08552016-01-25 11:04:21 +0100399 puts("Board: Xilinx ZynqMP\n");
Siva Durga Prasad Paladugu84696ff2015-08-04 13:01:05 +0530400 return 0;
401}
Siva Durga Prasad Paladugu16fa00a2015-08-04 13:03:26 +0530402
403#ifdef CONFIG_USB_DWC3
Michal Simek275bd6d2016-08-08 10:11:26 +0200404static struct dwc3_device dwc3_device_data0 = {
Siva Durga Prasad Paladugu16fa00a2015-08-04 13:03:26 +0530405 .maximum_speed = USB_SPEED_HIGH,
406 .base = ZYNQMP_USB0_XHCI_BASEADDR,
407 .dr_mode = USB_DR_MODE_PERIPHERAL,
408 .index = 0,
409};
410
Michal Simek275bd6d2016-08-08 10:11:26 +0200411static struct dwc3_device dwc3_device_data1 = {
412 .maximum_speed = USB_SPEED_HIGH,
413 .base = ZYNQMP_USB1_XHCI_BASEADDR,
414 .dr_mode = USB_DR_MODE_PERIPHERAL,
415 .index = 1,
416};
417
Michal Simek9feff382016-09-01 11:16:40 +0200418int usb_gadget_handle_interrupts(int index)
Siva Durga Prasad Paladugu16fa00a2015-08-04 13:03:26 +0530419{
Michal Simek9feff382016-09-01 11:16:40 +0200420 dwc3_uboot_handle_interrupt(index);
Siva Durga Prasad Paladugu16fa00a2015-08-04 13:03:26 +0530421 return 0;
422}
423
424int board_usb_init(int index, enum usb_init_type init)
425{
Michal Simek275bd6d2016-08-08 10:11:26 +0200426 debug("%s: index %x\n", __func__, index);
427
Michal Simek8ecd50c2016-09-01 11:27:32 +0200428#if defined(CONFIG_USB_GADGET_DOWNLOAD)
429 g_dnl_set_serialnumber(CONFIG_SYS_CONFIG_NAME);
430#endif
431
Michal Simek275bd6d2016-08-08 10:11:26 +0200432 switch (index) {
433 case 0:
434 return dwc3_uboot_init(&dwc3_device_data0);
435 case 1:
436 return dwc3_uboot_init(&dwc3_device_data1);
437 };
438
439 return -1;
Siva Durga Prasad Paladugu16fa00a2015-08-04 13:03:26 +0530440}
441
442int board_usb_cleanup(int index, enum usb_init_type init)
443{
444 dwc3_uboot_exit(index);
445 return 0;
446}
447#endif