blob: 452fc3e3b97ccde238774011bcec30f42ace90b5 [file] [log] [blame]
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01005 */
6#include <common.h>
Simon Glassf1dcc192016-05-05 07:28:11 -06007#include <dm.h>
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01008
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01009/*
10 * The u-boot networking stack is a little weird. It seems like the
11 * networking core allocates receive buffers up front without any
12 * regard to the hardware that's supposed to actually receive those
13 * packets.
14 *
15 * The MACB receives packets into 128-byte receive buffers, so the
16 * buffers allocated by the core isn't very practical to use. We'll
17 * allocate our own, but we need one such buffer in case a packet
18 * wraps around the DMA ring so that we have to copy it.
19 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020020 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010021 * configuration header. This way, the core allocates one RX buffer
22 * and one TX buffer, each of which can hold a ethernet packet of
23 * maximum size.
24 *
25 * For some reason, the networking core unconditionally specifies a
26 * 32-byte packet "alignment" (which really should be called
27 * "padding"). MACB shouldn't need that, but we'll refrain from any
28 * core modifications here...
29 */
30
31#include <net.h>
Simon Glassf1dcc192016-05-05 07:28:11 -060032#ifndef CONFIG_DM_ETH
Ben Warren89973f82008-08-31 22:22:04 -070033#include <netdev.h>
Simon Glassf1dcc192016-05-05 07:28:11 -060034#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010035#include <malloc.h>
Semih Hazar0f751d62009-12-17 15:07:15 +020036#include <miiphy.h>
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010037
38#include <linux/mii.h>
39#include <asm/io.h>
40#include <asm/dma-mapping.h>
41#include <asm/arch/clk.h>
Masahiro Yamada5d97dff2016-09-21 11:28:57 +090042#include <linux/errno.h>
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010043
44#include "macb.h"
45
Wenyou Yanga212b662016-05-17 13:11:35 +080046DECLARE_GLOBAL_DATA_PTR;
47
Andreas Bießmannceef9832014-05-26 22:55:18 +020048#define MACB_RX_BUFFER_SIZE 4096
49#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
50#define MACB_TX_RING_SIZE 16
51#define MACB_TX_TIMEOUT 1000
52#define MACB_AUTONEG_TIMEOUT 5000000
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010053
54struct macb_dma_desc {
55 u32 addr;
56 u32 ctrl;
57};
58
Wu, Josh5ae0e382014-05-27 16:31:05 +080059#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
60#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
61#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
Wu, Joshade4ea42015-06-03 16:45:44 +080062#define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
Wu, Josh5ae0e382014-05-27 16:31:05 +080063
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010064#define RXADDR_USED 0x00000001
65#define RXADDR_WRAP 0x00000002
66
67#define RXBUF_FRMLEN_MASK 0x00000fff
68#define RXBUF_FRAME_START 0x00004000
69#define RXBUF_FRAME_END 0x00008000
70#define RXBUF_TYPEID_MATCH 0x00400000
71#define RXBUF_ADDR4_MATCH 0x00800000
72#define RXBUF_ADDR3_MATCH 0x01000000
73#define RXBUF_ADDR2_MATCH 0x02000000
74#define RXBUF_ADDR1_MATCH 0x04000000
75#define RXBUF_BROADCAST 0x80000000
76
77#define TXBUF_FRMLEN_MASK 0x000007ff
78#define TXBUF_FRAME_END 0x00008000
79#define TXBUF_NOCRC 0x00010000
80#define TXBUF_EXHAUSTED 0x08000000
81#define TXBUF_UNDERRUN 0x10000000
82#define TXBUF_MAXRETRY 0x20000000
83#define TXBUF_WRAP 0x40000000
84#define TXBUF_USED 0x80000000
85
86struct macb_device {
87 void *regs;
88
89 unsigned int rx_tail;
90 unsigned int tx_head;
91 unsigned int tx_tail;
Simon Glassd5555b72016-05-05 07:28:09 -060092 unsigned int next_rx_tail;
93 bool wrapped;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +010094
95 void *rx_buffer;
96 void *tx_buffer;
97 struct macb_dma_desc *rx_ring;
98 struct macb_dma_desc *tx_ring;
99
100 unsigned long rx_buffer_dma;
101 unsigned long rx_ring_dma;
102 unsigned long tx_ring_dma;
103
Wu, Joshade4ea42015-06-03 16:45:44 +0800104 struct macb_dma_desc *dummy_desc;
105 unsigned long dummy_desc_dma;
106
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100107 const struct device *dev;
Simon Glassf1dcc192016-05-05 07:28:11 -0600108#ifndef CONFIG_DM_ETH
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100109 struct eth_device netdev;
Simon Glassf1dcc192016-05-05 07:28:11 -0600110#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100111 unsigned short phy_addr;
Bo Shenb1a00062013-04-24 15:59:27 +0800112 struct mii_dev *bus;
Wenyou Yanga212b662016-05-17 13:11:35 +0800113
114#ifdef CONFIG_DM_ETH
115 phy_interface_t phy_interface;
116#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100117};
Simon Glassf1dcc192016-05-05 07:28:11 -0600118#ifndef CONFIG_DM_ETH
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100119#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
Simon Glassf1dcc192016-05-05 07:28:11 -0600120#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100121
Bo Shend256be22013-04-24 15:59:28 +0800122static int macb_is_gem(struct macb_device *macb)
123{
124 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
125}
126
Gregory CLEMENT75b03cf2015-12-16 14:50:34 +0100127#ifndef cpu_is_sama5d2
128#define cpu_is_sama5d2() 0
129#endif
130
131#ifndef cpu_is_sama5d4
132#define cpu_is_sama5d4() 0
133#endif
134
135static int gem_is_gigabit_capable(struct macb_device *macb)
136{
137 /*
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400138 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
Gregory CLEMENT75b03cf2015-12-16 14:50:34 +0100139 * configured to support only 10/100.
140 */
141 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
142}
143
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100144static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
145{
146 unsigned long netctl;
147 unsigned long netstat;
148 unsigned long frame;
149
150 netctl = macb_readl(macb, NCR);
151 netctl |= MACB_BIT(MPE);
152 macb_writel(macb, NCR, netctl);
153
154 frame = (MACB_BF(SOF, 1)
155 | MACB_BF(RW, 1)
156 | MACB_BF(PHYA, macb->phy_addr)
157 | MACB_BF(REGA, reg)
158 | MACB_BF(CODE, 2)
159 | MACB_BF(DATA, value));
160 macb_writel(macb, MAN, frame);
161
162 do {
163 netstat = macb_readl(macb, NSR);
164 } while (!(netstat & MACB_BIT(IDLE)));
165
166 netctl = macb_readl(macb, NCR);
167 netctl &= ~MACB_BIT(MPE);
168 macb_writel(macb, NCR, netctl);
169}
170
171static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
172{
173 unsigned long netctl;
174 unsigned long netstat;
175 unsigned long frame;
176
177 netctl = macb_readl(macb, NCR);
178 netctl |= MACB_BIT(MPE);
179 macb_writel(macb, NCR, netctl);
180
181 frame = (MACB_BF(SOF, 1)
182 | MACB_BF(RW, 2)
183 | MACB_BF(PHYA, macb->phy_addr)
184 | MACB_BF(REGA, reg)
185 | MACB_BF(CODE, 2));
186 macb_writel(macb, MAN, frame);
187
188 do {
189 netstat = macb_readl(macb, NSR);
190 } while (!(netstat & MACB_BIT(IDLE)));
191
192 frame = macb_readl(macb, MAN);
193
194 netctl = macb_readl(macb, NCR);
195 netctl &= ~MACB_BIT(MPE);
196 macb_writel(macb, NCR, netctl);
197
198 return MACB_BFEXT(DATA, frame);
199}
200
Joe Hershberger1b8c18b2013-06-24 19:06:38 -0500201void __weak arch_get_mdio_control(const char *name)
Shiraz Hashim416ce622012-12-13 17:22:52 +0530202{
203 return;
204}
205
Bo Shenb1a00062013-04-24 15:59:27 +0800206#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Semih Hazar0f751d62009-12-17 15:07:15 +0200207
Joe Hershberger5a49f172016-08-08 11:28:38 -0500208int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
Semih Hazar0f751d62009-12-17 15:07:15 +0200209{
Joe Hershberger5a49f172016-08-08 11:28:38 -0500210 u16 value = 0;
Simon Glassf1dcc192016-05-05 07:28:11 -0600211#ifdef CONFIG_DM_ETH
Joe Hershberger5a49f172016-08-08 11:28:38 -0500212 struct udevice *dev = eth_get_dev_by_name(bus->name);
Simon Glassf1dcc192016-05-05 07:28:11 -0600213 struct macb_device *macb = dev_get_priv(dev);
214#else
Joe Hershberger5a49f172016-08-08 11:28:38 -0500215 struct eth_device *dev = eth_get_dev_by_name(bus->name);
Semih Hazar0f751d62009-12-17 15:07:15 +0200216 struct macb_device *macb = to_macb(dev);
Simon Glassf1dcc192016-05-05 07:28:11 -0600217#endif
Semih Hazar0f751d62009-12-17 15:07:15 +0200218
Andreas Bießmannceef9832014-05-26 22:55:18 +0200219 if (macb->phy_addr != phy_adr)
Semih Hazar0f751d62009-12-17 15:07:15 +0200220 return -1;
221
Joe Hershberger5a49f172016-08-08 11:28:38 -0500222 arch_get_mdio_control(bus->name);
223 value = macb_mdio_read(macb, reg);
Semih Hazar0f751d62009-12-17 15:07:15 +0200224
Joe Hershberger5a49f172016-08-08 11:28:38 -0500225 return value;
Semih Hazar0f751d62009-12-17 15:07:15 +0200226}
227
Joe Hershberger5a49f172016-08-08 11:28:38 -0500228int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
229 u16 value)
Semih Hazar0f751d62009-12-17 15:07:15 +0200230{
Simon Glassf1dcc192016-05-05 07:28:11 -0600231#ifdef CONFIG_DM_ETH
Joe Hershberger5a49f172016-08-08 11:28:38 -0500232 struct udevice *dev = eth_get_dev_by_name(bus->name);
Simon Glassf1dcc192016-05-05 07:28:11 -0600233 struct macb_device *macb = dev_get_priv(dev);
234#else
Joe Hershberger5a49f172016-08-08 11:28:38 -0500235 struct eth_device *dev = eth_get_dev_by_name(bus->name);
Semih Hazar0f751d62009-12-17 15:07:15 +0200236 struct macb_device *macb = to_macb(dev);
Simon Glassf1dcc192016-05-05 07:28:11 -0600237#endif
Semih Hazar0f751d62009-12-17 15:07:15 +0200238
Andreas Bießmannceef9832014-05-26 22:55:18 +0200239 if (macb->phy_addr != phy_adr)
Semih Hazar0f751d62009-12-17 15:07:15 +0200240 return -1;
241
Joe Hershberger5a49f172016-08-08 11:28:38 -0500242 arch_get_mdio_control(bus->name);
Semih Hazar0f751d62009-12-17 15:07:15 +0200243 macb_mdio_write(macb, reg, value);
244
245 return 0;
246}
247#endif
248
Wu, Josh5ae0e382014-05-27 16:31:05 +0800249#define RX 1
250#define TX 0
251static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
252{
253 if (rx)
Heiko Schocher592a7492016-08-29 07:46:11 +0200254 invalidate_dcache_range(macb->rx_ring_dma,
255 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
256 PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800257 else
Heiko Schocher592a7492016-08-29 07:46:11 +0200258 invalidate_dcache_range(macb->tx_ring_dma,
259 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
260 PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800261}
262
263static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
264{
265 if (rx)
266 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200267 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800268 else
269 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200270 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800271}
272
273static inline void macb_flush_rx_buffer(struct macb_device *macb)
274{
275 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200276 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800277}
278
279static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
280{
281 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200282 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
Wu, Josh5ae0e382014-05-27 16:31:05 +0800283}
Semih Hazar0f751d62009-12-17 15:07:15 +0200284
Jon Loeliger07d38a12007-07-09 17:30:01 -0500285#if defined(CONFIG_CMD_NET)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100286
Simon Glassd5555b72016-05-05 07:28:09 -0600287static int _macb_send(struct macb_device *macb, const char *name, void *packet,
288 int length)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100289{
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100290 unsigned long paddr, ctrl;
291 unsigned int tx_head = macb->tx_head;
292 int i;
293
294 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
295
296 ctrl = length & TXBUF_FRMLEN_MASK;
297 ctrl |= TXBUF_FRAME_END;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200298 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100299 ctrl |= TXBUF_WRAP;
300 macb->tx_head = 0;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200301 } else {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100302 macb->tx_head++;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200303 }
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100304
305 macb->tx_ring[tx_head].ctrl = ctrl;
306 macb->tx_ring[tx_head].addr = paddr;
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200307 barrier();
Wu, Josh5ae0e382014-05-27 16:31:05 +0800308 macb_flush_ring_desc(macb, TX);
309 /* Do we need check paddr and length is dcache line aligned? */
Simon Glassf589f8c2016-05-05 07:28:10 -0600310 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100311 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
312
313 /*
314 * I guess this is necessary because the networking core may
315 * re-use the transmit buffer as soon as we return...
316 */
Andreas Bießmannceef9832014-05-26 22:55:18 +0200317 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200318 barrier();
Wu, Josh5ae0e382014-05-27 16:31:05 +0800319 macb_invalidate_ring_desc(macb, TX);
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200320 ctrl = macb->tx_ring[tx_head].ctrl;
321 if (ctrl & TXBUF_USED)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100322 break;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100323 udelay(1);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100324 }
325
326 dma_unmap_single(packet, length, paddr);
327
Andreas Bießmannceef9832014-05-26 22:55:18 +0200328 if (i <= MACB_TX_TIMEOUT) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100329 if (ctrl & TXBUF_UNDERRUN)
Simon Glassd5555b72016-05-05 07:28:09 -0600330 printf("%s: TX underrun\n", name);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100331 if (ctrl & TXBUF_EXHAUSTED)
Simon Glassd5555b72016-05-05 07:28:09 -0600332 printf("%s: TX buffers exhausted in mid frame\n", name);
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200333 } else {
Simon Glassd5555b72016-05-05 07:28:09 -0600334 printf("%s: TX timeout\n", name);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100335 }
336
337 /* No one cares anyway */
338 return 0;
339}
340
341static void reclaim_rx_buffers(struct macb_device *macb,
342 unsigned int new_tail)
343{
344 unsigned int i;
345
346 i = macb->rx_tail;
Wu, Josh5ae0e382014-05-27 16:31:05 +0800347
348 macb_invalidate_ring_desc(macb, RX);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100349 while (i > new_tail) {
350 macb->rx_ring[i].addr &= ~RXADDR_USED;
351 i++;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200352 if (i > MACB_RX_RING_SIZE)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100353 i = 0;
354 }
355
356 while (i < new_tail) {
357 macb->rx_ring[i].addr &= ~RXADDR_USED;
358 i++;
359 }
360
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200361 barrier();
Wu, Josh5ae0e382014-05-27 16:31:05 +0800362 macb_flush_ring_desc(macb, RX);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100363 macb->rx_tail = new_tail;
364}
365
Simon Glassd5555b72016-05-05 07:28:09 -0600366static int _macb_recv(struct macb_device *macb, uchar **packetp)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100367{
Simon Glassd5555b72016-05-05 07:28:09 -0600368 unsigned int next_rx_tail = macb->next_rx_tail;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100369 void *buffer;
370 int length;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100371 u32 status;
372
Simon Glassd5555b72016-05-05 07:28:09 -0600373 macb->wrapped = false;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100374 for (;;) {
Wu, Josh5ae0e382014-05-27 16:31:05 +0800375 macb_invalidate_ring_desc(macb, RX);
376
Simon Glassd5555b72016-05-05 07:28:09 -0600377 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
378 return -EAGAIN;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100379
Simon Glassd5555b72016-05-05 07:28:09 -0600380 status = macb->rx_ring[next_rx_tail].ctrl;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100381 if (status & RXBUF_FRAME_START) {
Simon Glassd5555b72016-05-05 07:28:09 -0600382 if (next_rx_tail != macb->rx_tail)
383 reclaim_rx_buffers(macb, next_rx_tail);
384 macb->wrapped = false;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100385 }
386
387 if (status & RXBUF_FRAME_END) {
388 buffer = macb->rx_buffer + 128 * macb->rx_tail;
389 length = status & RXBUF_FRMLEN_MASK;
Wu, Josh5ae0e382014-05-27 16:31:05 +0800390
391 macb_invalidate_rx_buffer(macb);
Simon Glassd5555b72016-05-05 07:28:09 -0600392 if (macb->wrapped) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100393 unsigned int headlen, taillen;
394
Andreas Bießmannceef9832014-05-26 22:55:18 +0200395 headlen = 128 * (MACB_RX_RING_SIZE
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100396 - macb->rx_tail);
397 taillen = length - headlen;
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500398 memcpy((void *)net_rx_packets[0],
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100399 buffer, headlen);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500400 memcpy((void *)net_rx_packets[0] + headlen,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100401 macb->rx_buffer, taillen);
Simon Glassd5555b72016-05-05 07:28:09 -0600402 *packetp = (void *)net_rx_packets[0];
403 } else {
404 *packetp = buffer;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100405 }
406
Simon Glassd5555b72016-05-05 07:28:09 -0600407 if (++next_rx_tail >= MACB_RX_RING_SIZE)
408 next_rx_tail = 0;
409 macb->next_rx_tail = next_rx_tail;
410 return length;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100411 } else {
Simon Glassd5555b72016-05-05 07:28:09 -0600412 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
413 macb->wrapped = true;
414 next_rx_tail = 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100415 }
416 }
Haavard Skinnemoen04fcb5d2007-05-02 13:22:38 +0200417 barrier();
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100418 }
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100419}
420
Simon Glassd5555b72016-05-05 07:28:09 -0600421static void macb_phy_reset(struct macb_device *macb, const char *name)
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200422{
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200423 int i;
424 u16 status, adv;
425
426 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
427 macb_mdio_write(macb, MII_ADVERTISE, adv);
Simon Glassd5555b72016-05-05 07:28:09 -0600428 printf("%s: Starting autonegotiation...\n", name);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200429 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
430 | BMCR_ANRESTART));
431
Andreas Bießmannceef9832014-05-26 22:55:18 +0200432 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200433 status = macb_mdio_read(macb, MII_BMSR);
434 if (status & BMSR_ANEGCOMPLETE)
435 break;
436 udelay(100);
437 }
438
439 if (status & BMSR_ANEGCOMPLETE)
Simon Glassd5555b72016-05-05 07:28:09 -0600440 printf("%s: Autonegotiation complete\n", name);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200441 else
442 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600443 name, status);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200444}
445
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100446#ifdef CONFIG_MACB_SEARCH_PHY
Wenyou Yanga212b662016-05-17 13:11:35 +0800447static int macb_phy_find(struct macb_device *macb, const char *name)
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100448{
449 int i;
450 u16 phy_id;
451
452 /* Search for PHY... */
453 for (i = 0; i < 32; i++) {
454 macb->phy_addr = i;
455 phy_id = macb_mdio_read(macb, MII_PHYSID1);
456 if (phy_id != 0xffff) {
Wenyou Yanga212b662016-05-17 13:11:35 +0800457 printf("%s: PHY present at %d\n", name, i);
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100458 return 1;
459 }
460 }
461
462 /* PHY isn't up to snuff */
Wenyou Yanga212b662016-05-17 13:11:35 +0800463 printf("%s: PHY not found\n", name);
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100464
465 return 0;
466}
467#endif /* CONFIG_MACB_SEARCH_PHY */
468
Wenyou Yanga212b662016-05-17 13:11:35 +0800469#ifdef CONFIG_DM_ETH
470static int macb_phy_init(struct udevice *dev, const char *name)
471#else
Simon Glassd5555b72016-05-05 07:28:09 -0600472static int macb_phy_init(struct macb_device *macb, const char *name)
Wenyou Yanga212b662016-05-17 13:11:35 +0800473#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100474{
Wenyou Yanga212b662016-05-17 13:11:35 +0800475#ifdef CONFIG_DM_ETH
476 struct macb_device *macb = dev_get_priv(dev);
477#endif
Bo Shenb1a00062013-04-24 15:59:27 +0800478#ifdef CONFIG_PHYLIB
479 struct phy_device *phydev;
480#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100481 u32 ncfgr;
482 u16 phy_id, status, adv, lpa;
483 int media, speed, duplex;
484 int i;
485
Simon Glassd5555b72016-05-05 07:28:09 -0600486 arch_get_mdio_control(name);
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100487#ifdef CONFIG_MACB_SEARCH_PHY
488 /* Auto-detect phy_addr */
Wenyou Yanga212b662016-05-17 13:11:35 +0800489 if (!macb_phy_find(macb, name))
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100490 return 0;
Gunnar Rangoyfc01ea12009-01-23 12:56:31 +0100491#endif /* CONFIG_MACB_SEARCH_PHY */
492
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100493 /* Check if the PHY is up to snuff... */
494 phy_id = macb_mdio_read(macb, MII_PHYSID1);
495 if (phy_id == 0xffff) {
Simon Glassd5555b72016-05-05 07:28:09 -0600496 printf("%s: No PHY present\n", name);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100497 return 0;
498 }
499
Bo Shenb1a00062013-04-24 15:59:27 +0800500#ifdef CONFIG_PHYLIB
Wenyou Yanga212b662016-05-17 13:11:35 +0800501#ifdef CONFIG_DM_ETH
502 phydev = phy_connect(macb->bus, macb->phy_addr, dev,
503 macb->phy_interface);
504#else
Bo Shen8314ccd2013-08-19 10:35:47 +0800505 /* need to consider other phy interface mode */
Simon Glassd5555b72016-05-05 07:28:09 -0600506 phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
Bo Shen8314ccd2013-08-19 10:35:47 +0800507 PHY_INTERFACE_MODE_RGMII);
Wenyou Yanga212b662016-05-17 13:11:35 +0800508#endif
Bo Shen8314ccd2013-08-19 10:35:47 +0800509 if (!phydev) {
510 printf("phy_connect failed\n");
511 return -ENODEV;
512 }
513
Bo Shenb1a00062013-04-24 15:59:27 +0800514 phy_config(phydev);
515#endif
516
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200517 status = macb_mdio_read(macb, MII_BMSR);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100518 if (!(status & BMSR_LSTATUS)) {
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200519 /* Try to re-negotiate if we don't have link already. */
Simon Glassd5555b72016-05-05 07:28:09 -0600520 macb_phy_reset(macb, name);
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200521
Andreas Bießmannceef9832014-05-26 22:55:18 +0200522 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100523 status = macb_mdio_read(macb, MII_BMSR);
524 if (status & BMSR_LSTATUS)
525 break;
Haavard Skinnemoenf2134f82007-05-02 13:31:53 +0200526 udelay(100);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100527 }
528 }
529
530 if (!(status & BMSR_LSTATUS)) {
531 printf("%s: link down (status: 0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600532 name, status);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100533 return 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100534 }
Bo Shend256be22013-04-24 15:59:28 +0800535
Gregory CLEMENT75b03cf2015-12-16 14:50:34 +0100536 /* First check for GMAC and that it is GiB capable */
537 if (gem_is_gigabit_capable(macb)) {
Bo Shend256be22013-04-24 15:59:28 +0800538 lpa = macb_mdio_read(macb, MII_STAT1000);
Bo Shend256be22013-04-24 15:59:28 +0800539
Andreas Bießmann47609572014-09-18 23:46:48 +0200540 if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
541 duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
542
543 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600544 name,
Bo Shend256be22013-04-24 15:59:28 +0800545 duplex ? "full" : "half",
546 lpa);
547
548 ncfgr = macb_readl(macb, NCFGR);
Andreas Bießmann47609572014-09-18 23:46:48 +0200549 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
550 ncfgr |= GEM_BIT(GBE);
551
Bo Shend256be22013-04-24 15:59:28 +0800552 if (duplex)
553 ncfgr |= MACB_BIT(FD);
Andreas Bießmann47609572014-09-18 23:46:48 +0200554
Bo Shend256be22013-04-24 15:59:28 +0800555 macb_writel(macb, NCFGR, ncfgr);
556
557 return 1;
558 }
559 }
560
561 /* fall back for EMAC checking */
562 adv = macb_mdio_read(macb, MII_ADVERTISE);
563 lpa = macb_mdio_read(macb, MII_LPA);
564 media = mii_nway_result(lpa & adv);
565 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
566 ? 1 : 0);
567 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
568 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
Simon Glassd5555b72016-05-05 07:28:09 -0600569 name,
Bo Shend256be22013-04-24 15:59:28 +0800570 speed ? "100" : "10",
571 duplex ? "full" : "half",
572 lpa);
573
574 ncfgr = macb_readl(macb, NCFGR);
Bo Shenc83cb5f2015-03-04 13:35:16 +0800575 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
Bo Shend256be22013-04-24 15:59:28 +0800576 if (speed)
577 ncfgr |= MACB_BIT(SPD);
578 if (duplex)
579 ncfgr |= MACB_BIT(FD);
580 macb_writel(macb, NCFGR, ncfgr);
581
582 return 1;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100583}
584
Wu, Joshade4ea42015-06-03 16:45:44 +0800585static int gmac_init_multi_queues(struct macb_device *macb)
586{
587 int i, num_queues = 1;
588 u32 queue_mask;
589
590 /* bit 0 is never set but queue 0 always exists */
591 queue_mask = gem_readl(macb, DCFG6) & 0xff;
592 queue_mask |= 0x1;
593
594 for (i = 1; i < MACB_MAX_QUEUES; i++)
595 if (queue_mask & (1 << i))
596 num_queues++;
597
598 macb->dummy_desc->ctrl = TXBUF_USED;
599 macb->dummy_desc->addr = 0;
600 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
Heiko Schocher592a7492016-08-29 07:46:11 +0200601 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
Wu, Joshade4ea42015-06-03 16:45:44 +0800602
603 for (i = 1; i < num_queues; i++)
604 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
605
606 return 0;
607}
608
Wenyou Yanga212b662016-05-17 13:11:35 +0800609#ifdef CONFIG_DM_ETH
610static int _macb_init(struct udevice *dev, const char *name)
611#else
Simon Glassd5555b72016-05-05 07:28:09 -0600612static int _macb_init(struct macb_device *macb, const char *name)
Wenyou Yanga212b662016-05-17 13:11:35 +0800613#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100614{
Wenyou Yanga212b662016-05-17 13:11:35 +0800615#ifdef CONFIG_DM_ETH
616 struct macb_device *macb = dev_get_priv(dev);
617#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100618 unsigned long paddr;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100619 int i;
620
621 /*
622 * macb_halt should have been called at some point before now,
623 * so we'll assume the controller is idle.
624 */
625
626 /* initialize DMA descriptors */
627 paddr = macb->rx_buffer_dma;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200628 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
629 if (i == (MACB_RX_RING_SIZE - 1))
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100630 paddr |= RXADDR_WRAP;
631 macb->rx_ring[i].addr = paddr;
632 macb->rx_ring[i].ctrl = 0;
633 paddr += 128;
634 }
Wu, Josh5ae0e382014-05-27 16:31:05 +0800635 macb_flush_ring_desc(macb, RX);
636 macb_flush_rx_buffer(macb);
637
Andreas Bießmannceef9832014-05-26 22:55:18 +0200638 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100639 macb->tx_ring[i].addr = 0;
Andreas Bießmannceef9832014-05-26 22:55:18 +0200640 if (i == (MACB_TX_RING_SIZE - 1))
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100641 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
642 else
643 macb->tx_ring[i].ctrl = TXBUF_USED;
644 }
Wu, Josh5ae0e382014-05-27 16:31:05 +0800645 macb_flush_ring_desc(macb, TX);
646
Andreas Bießmannceef9832014-05-26 22:55:18 +0200647 macb->rx_tail = 0;
648 macb->tx_head = 0;
649 macb->tx_tail = 0;
Simon Glassd5555b72016-05-05 07:28:09 -0600650 macb->next_rx_tail = 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100651
652 macb_writel(macb, RBQP, macb->rx_ring_dma);
653 macb_writel(macb, TBQP, macb->tx_ring_dma);
654
Bo Shend256be22013-04-24 15:59:28 +0800655 if (macb_is_gem(macb)) {
Wu, Joshade4ea42015-06-03 16:45:44 +0800656 /* Check the multi queue and initialize the queue for tx */
657 gmac_init_multi_queues(macb);
658
Bo Shencabf61c2014-11-10 15:24:01 +0800659 /*
660 * When the GMAC IP with GE feature, this bit is used to
661 * select interface between RGMII and GMII.
662 * When the GMAC IP without GE feature, this bit is used
663 * to select interface between RMII and MII.
664 */
Wenyou Yanga212b662016-05-17 13:11:35 +0800665#ifdef CONFIG_DM_ETH
666 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
667 gem_writel(macb, UR, GEM_BIT(RGMII));
668 else
669 gem_writel(macb, UR, 0);
670#else
Bo Shencabf61c2014-11-10 15:24:01 +0800671#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
Bo Shend256be22013-04-24 15:59:28 +0800672 gem_writel(macb, UR, GEM_BIT(RGMII));
673#else
674 gem_writel(macb, UR, 0);
675#endif
Wenyou Yanga212b662016-05-17 13:11:35 +0800676#endif
Bo Shend256be22013-04-24 15:59:28 +0800677 } else {
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100678 /* choose RMII or MII mode. This depends on the board */
Wenyou Yanga212b662016-05-17 13:11:35 +0800679#ifdef CONFIG_DM_ETH
680#ifdef CONFIG_AT91FAMILY
681 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
682 macb_writel(macb, USRIO,
683 MACB_BIT(RMII) | MACB_BIT(CLKEN));
684 } else {
685 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
686 }
687#else
688 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
689 macb_writel(macb, USRIO, 0);
690 else
691 macb_writel(macb, USRIO, MACB_BIT(MII));
692#endif
693#else
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100694#ifdef CONFIG_RMII
Bo Shend8f64b42013-04-24 15:59:26 +0800695#ifdef CONFIG_AT91FAMILY
Stelian Pop7263ef12008-01-03 21:15:56 +0000696 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
697#else
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100698 macb_writel(macb, USRIO, 0);
Stelian Pop7263ef12008-01-03 21:15:56 +0000699#endif
700#else
Bo Shend8f64b42013-04-24 15:59:26 +0800701#ifdef CONFIG_AT91FAMILY
Stelian Pop7263ef12008-01-03 21:15:56 +0000702 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100703#else
704 macb_writel(macb, USRIO, MACB_BIT(MII));
705#endif
Stelian Pop7263ef12008-01-03 21:15:56 +0000706#endif /* CONFIG_RMII */
Wenyou Yanga212b662016-05-17 13:11:35 +0800707#endif
Bo Shend256be22013-04-24 15:59:28 +0800708 }
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100709
Wenyou Yanga212b662016-05-17 13:11:35 +0800710#ifdef CONFIG_DM_ETH
711 if (!macb_phy_init(dev, name))
712#else
Simon Glassd5555b72016-05-05 07:28:09 -0600713 if (!macb_phy_init(macb, name))
Wenyou Yanga212b662016-05-17 13:11:35 +0800714#endif
Ben Warren422b1a02008-01-09 18:15:53 -0500715 return -1;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100716
717 /* Enable TX and RX */
718 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
719
Ben Warren422b1a02008-01-09 18:15:53 -0500720 return 0;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100721}
722
Simon Glassd5555b72016-05-05 07:28:09 -0600723static void _macb_halt(struct macb_device *macb)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100724{
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100725 u32 ncr, tsr;
726
727 /* Halt the controller and wait for any ongoing transmission to end. */
728 ncr = macb_readl(macb, NCR);
729 ncr |= MACB_BIT(THALT);
730 macb_writel(macb, NCR, ncr);
731
732 do {
733 tsr = macb_readl(macb, TSR);
734 } while (tsr & MACB_BIT(TGO));
735
736 /* Disable TX and RX, and clear statistics */
737 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
738}
739
Simon Glassd5555b72016-05-05 07:28:09 -0600740static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
Ben Warren6bb46792010-06-01 11:55:42 -0700741{
Ben Warren6bb46792010-06-01 11:55:42 -0700742 u32 hwaddr_bottom;
743 u16 hwaddr_top;
744
745 /* set hardware address */
Simon Glassd5555b72016-05-05 07:28:09 -0600746 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
747 enetaddr[2] << 16 | enetaddr[3] << 24;
Ben Warren6bb46792010-06-01 11:55:42 -0700748 macb_writel(macb, SA1B, hwaddr_bottom);
Simon Glassd5555b72016-05-05 07:28:09 -0600749 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
Ben Warren6bb46792010-06-01 11:55:42 -0700750 macb_writel(macb, SA1T, hwaddr_top);
751 return 0;
752}
753
Bo Shend256be22013-04-24 15:59:28 +0800754static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
755{
756 u32 config;
757 unsigned long macb_hz = get_macb_pclk_rate(id);
758
759 if (macb_hz < 20000000)
760 config = MACB_BF(CLK, MACB_CLK_DIV8);
761 else if (macb_hz < 40000000)
762 config = MACB_BF(CLK, MACB_CLK_DIV16);
763 else if (macb_hz < 80000000)
764 config = MACB_BF(CLK, MACB_CLK_DIV32);
765 else
766 config = MACB_BF(CLK, MACB_CLK_DIV64);
767
768 return config;
769}
770
771static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
772{
773 u32 config;
774 unsigned long macb_hz = get_macb_pclk_rate(id);
775
776 if (macb_hz < 20000000)
777 config = GEM_BF(CLK, GEM_CLK_DIV8);
778 else if (macb_hz < 40000000)
779 config = GEM_BF(CLK, GEM_CLK_DIV16);
780 else if (macb_hz < 80000000)
781 config = GEM_BF(CLK, GEM_CLK_DIV32);
782 else if (macb_hz < 120000000)
783 config = GEM_BF(CLK, GEM_CLK_DIV48);
784 else if (macb_hz < 160000000)
785 config = GEM_BF(CLK, GEM_CLK_DIV64);
786 else
787 config = GEM_BF(CLK, GEM_CLK_DIV96);
788
789 return config;
790}
791
Bo Shen32e4f6b2013-09-18 15:07:44 +0800792/*
793 * Get the DMA bus width field of the network configuration register that we
794 * should program. We find the width from decoding the design configuration
795 * register to find the maximum supported data bus width.
796 */
797static u32 macb_dbw(struct macb_device *macb)
798{
799 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
800 case 4:
801 return GEM_BF(DBW, GEM_DBW128);
802 case 2:
803 return GEM_BF(DBW, GEM_DBW64);
804 case 1:
805 default:
806 return GEM_BF(DBW, GEM_DBW32);
807 }
808}
809
Simon Glassd5555b72016-05-05 07:28:09 -0600810static void _macb_eth_initialize(struct macb_device *macb)
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100811{
Simon Glassd5555b72016-05-05 07:28:09 -0600812 int id = 0; /* This is not used by functions we call */
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100813 u32 ncfgr;
814
Simon Glassd5555b72016-05-05 07:28:09 -0600815 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
Andreas Bießmannceef9832014-05-26 22:55:18 +0200816 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100817 &macb->rx_buffer_dma);
Wu, Josh5ae0e382014-05-27 16:31:05 +0800818 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100819 &macb->rx_ring_dma);
Wu, Josh5ae0e382014-05-27 16:31:05 +0800820 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100821 &macb->tx_ring_dma);
Wu, Joshade4ea42015-06-03 16:45:44 +0800822 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
823 &macb->dummy_desc_dma);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100824
Simon Glassd5555b72016-05-05 07:28:09 -0600825 /*
826 * Do some basic initialization so that we at least can talk
827 * to the PHY
828 */
829 if (macb_is_gem(macb)) {
830 ncfgr = gem_mdc_clk_div(id, macb);
831 ncfgr |= macb_dbw(macb);
832 } else {
833 ncfgr = macb_mdc_clk_div(id, macb);
834 }
835
836 macb_writel(macb, NCFGR, ncfgr);
837}
838
Simon Glassf1dcc192016-05-05 07:28:11 -0600839#ifndef CONFIG_DM_ETH
Simon Glassd5555b72016-05-05 07:28:09 -0600840static int macb_send(struct eth_device *netdev, void *packet, int length)
841{
842 struct macb_device *macb = to_macb(netdev);
843
844 return _macb_send(macb, netdev->name, packet, length);
845}
846
847static int macb_recv(struct eth_device *netdev)
848{
849 struct macb_device *macb = to_macb(netdev);
850 uchar *packet;
851 int length;
852
853 macb->wrapped = false;
854 for (;;) {
855 macb->next_rx_tail = macb->rx_tail;
856 length = _macb_recv(macb, &packet);
857 if (length >= 0) {
858 net_process_received_packet(packet, length);
859 reclaim_rx_buffers(macb, macb->next_rx_tail);
860 } else if (length < 0) {
861 return length;
862 }
863 }
864}
865
866static int macb_init(struct eth_device *netdev, bd_t *bd)
867{
868 struct macb_device *macb = to_macb(netdev);
869
870 return _macb_init(macb, netdev->name);
871}
872
873static void macb_halt(struct eth_device *netdev)
874{
875 struct macb_device *macb = to_macb(netdev);
876
877 return _macb_halt(macb);
878}
879
880static int macb_write_hwaddr(struct eth_device *netdev)
881{
882 struct macb_device *macb = to_macb(netdev);
883
884 return _macb_write_hwaddr(macb, netdev->enetaddr);
885}
886
887int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
888{
889 struct macb_device *macb;
890 struct eth_device *netdev;
891
892 macb = malloc(sizeof(struct macb_device));
893 if (!macb) {
894 printf("Error: Failed to allocate memory for MACB%d\n", id);
895 return -1;
896 }
897 memset(macb, 0, sizeof(struct macb_device));
898
899 netdev = &macb->netdev;
Wu, Josh5ae0e382014-05-27 16:31:05 +0800900
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100901 macb->regs = regs;
902 macb->phy_addr = phy_addr;
903
Bo Shend256be22013-04-24 15:59:28 +0800904 if (macb_is_gem(macb))
905 sprintf(netdev->name, "gmac%d", id);
906 else
907 sprintf(netdev->name, "macb%d", id);
908
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100909 netdev->init = macb_init;
910 netdev->halt = macb_halt;
911 netdev->send = macb_send;
912 netdev->recv = macb_recv;
Ben Warren6bb46792010-06-01 11:55:42 -0700913 netdev->write_hwaddr = macb_write_hwaddr;
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100914
Simon Glassd5555b72016-05-05 07:28:09 -0600915 _macb_eth_initialize(macb);
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100916
917 eth_register(netdev);
918
Bo Shenb1a00062013-04-24 15:59:27 +0800919#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Joe Hershberger5a49f172016-08-08 11:28:38 -0500920 int retval;
921 struct mii_dev *mdiodev = mdio_alloc();
922 if (!mdiodev)
923 return -ENOMEM;
924 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
925 mdiodev->read = macb_miiphy_read;
926 mdiodev->write = macb_miiphy_write;
927
928 retval = mdio_register(mdiodev);
929 if (retval < 0)
930 return retval;
Bo Shenb1a00062013-04-24 15:59:27 +0800931 macb->bus = miiphy_get_dev_by_name(netdev->name);
Semih Hazar0f751d62009-12-17 15:07:15 +0200932#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +0100933 return 0;
934}
Simon Glassf1dcc192016-05-05 07:28:11 -0600935#endif /* !CONFIG_DM_ETH */
936
937#ifdef CONFIG_DM_ETH
938
939static int macb_start(struct udevice *dev)
940{
Wenyou Yanga212b662016-05-17 13:11:35 +0800941 return _macb_init(dev, dev->name);
Simon Glassf1dcc192016-05-05 07:28:11 -0600942}
943
944static int macb_send(struct udevice *dev, void *packet, int length)
945{
946 struct macb_device *macb = dev_get_priv(dev);
947
948 return _macb_send(macb, dev->name, packet, length);
949}
950
951static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
952{
953 struct macb_device *macb = dev_get_priv(dev);
954
955 macb->next_rx_tail = macb->rx_tail;
956 macb->wrapped = false;
957
958 return _macb_recv(macb, packetp);
959}
960
961static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
962{
963 struct macb_device *macb = dev_get_priv(dev);
964
965 reclaim_rx_buffers(macb, macb->next_rx_tail);
966
967 return 0;
968}
969
970static void macb_stop(struct udevice *dev)
971{
972 struct macb_device *macb = dev_get_priv(dev);
973
974 _macb_halt(macb);
975}
976
977static int macb_write_hwaddr(struct udevice *dev)
978{
979 struct eth_pdata *plat = dev_get_platdata(dev);
980 struct macb_device *macb = dev_get_priv(dev);
981
982 return _macb_write_hwaddr(macb, plat->enetaddr);
983}
984
985static const struct eth_ops macb_eth_ops = {
986 .start = macb_start,
987 .send = macb_send,
988 .recv = macb_recv,
989 .stop = macb_stop,
990 .free_pkt = macb_free_pkt,
991 .write_hwaddr = macb_write_hwaddr,
992};
993
994static int macb_eth_probe(struct udevice *dev)
995{
996 struct eth_pdata *pdata = dev_get_platdata(dev);
997 struct macb_device *macb = dev_get_priv(dev);
998
Wenyou Yanga212b662016-05-17 13:11:35 +0800999#ifdef CONFIG_DM_ETH
1000 const char *phy_mode;
1001
Simon Glasse160f7d2017-01-17 16:52:55 -07001002 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1003 NULL);
Wenyou Yanga212b662016-05-17 13:11:35 +08001004 if (phy_mode)
1005 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1006 if (macb->phy_interface == -1) {
1007 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1008 return -EINVAL;
1009 }
1010#endif
1011
Simon Glassf1dcc192016-05-05 07:28:11 -06001012 macb->regs = (void *)pdata->iobase;
1013
1014 _macb_eth_initialize(macb);
1015#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Joe Hershberger5a49f172016-08-08 11:28:38 -05001016 int retval;
1017 struct mii_dev *mdiodev = mdio_alloc();
1018 if (!mdiodev)
1019 return -ENOMEM;
1020 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
1021 mdiodev->read = macb_miiphy_read;
1022 mdiodev->write = macb_miiphy_write;
1023
1024 retval = mdio_register(mdiodev);
1025 if (retval < 0)
1026 return retval;
Simon Glassf1dcc192016-05-05 07:28:11 -06001027 macb->bus = miiphy_get_dev_by_name(dev->name);
1028#endif
1029
1030 return 0;
1031}
1032
1033static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1034{
1035 struct eth_pdata *pdata = dev_get_platdata(dev);
1036
1037 pdata->iobase = dev_get_addr(dev);
1038 return 0;
1039}
1040
1041static const struct udevice_id macb_eth_ids[] = {
1042 { .compatible = "cdns,macb" },
1043 { }
1044};
1045
1046U_BOOT_DRIVER(eth_macb) = {
1047 .name = "eth_macb",
1048 .id = UCLASS_ETH,
1049 .of_match = macb_eth_ids,
1050 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1051 .probe = macb_eth_probe,
1052 .ops = &macb_eth_ops,
1053 .priv_auto_alloc_size = sizeof(struct macb_device),
1054 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1055};
1056#endif
Haavard Skinnemoen5c1fe1f2006-01-20 10:03:34 +01001057
Jon Loeliger07d38a12007-07-09 17:30:01 -05001058#endif