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Michal Simek293eb332013-04-22 14:56:49 +02001/*
Michal Simekd9ae52c2015-11-30 16:13:03 +01002 * (C) Copyright 2013 - 2015 Xilinx, Inc.
Michal Simek293eb332013-04-22 14:56:49 +02003 *
4 * Xilinx Zynq SD Host Controller Interface
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Michal Simek293eb332013-04-22 14:56:49 +02007 */
8
Stefan Herbrechtsmeiere0f4de12017-01-17 16:27:32 +01009#include <clk.h>
Michal Simek293eb332013-04-22 14:56:49 +020010#include <common.h>
Michal Simekd9ae52c2015-11-30 16:13:03 +010011#include <dm.h>
Michal Simek345d3c02014-02-24 11:16:31 +010012#include <fdtdec.h>
13#include <libfdt.h>
Michal Simek293eb332013-04-22 14:56:49 +020014#include <malloc.h>
15#include <sdhci.h>
Michal Simek293eb332013-04-22 14:56:49 +020016
Siva Durga Prasad Paladugua57a4a52016-01-05 12:21:04 +053017#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
18# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
19#endif
20
Simon Glass329a4492016-07-05 17:10:15 -060021struct arasan_sdhci_plat {
22 struct mmc_config cfg;
23 struct mmc mmc;
24};
25
Michal Simekd9ae52c2015-11-30 16:13:03 +010026static int arasan_sdhci_probe(struct udevice *dev)
Michal Simek293eb332013-04-22 14:56:49 +020027{
Simon Glass329a4492016-07-05 17:10:15 -060028 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Michal Simekd9ae52c2015-11-30 16:13:03 +010029 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
30 struct sdhci_host *host = dev_get_priv(dev);
Stefan Herbrechtsmeiere0f4de12017-01-17 16:27:32 +010031 struct clk clk;
32 unsigned long clock;
Simon Glass329a4492016-07-05 17:10:15 -060033 int ret;
Michal Simek293eb332013-04-22 14:56:49 +020034
Stefan Herbrechtsmeiere0f4de12017-01-17 16:27:32 +010035 ret = clk_get_by_index(dev, 0, &clk);
36 if (ret < 0) {
37 dev_err(dev, "failed to get clock\n");
38 return ret;
39 }
40
41 clock = clk_get_rate(&clk);
42 if (IS_ERR_VALUE(clock)) {
43 dev_err(dev, "failed to get rate\n");
44 return clock;
45 }
46 debug("%s: CLK %ld\n", __func__, clock);
47
48 ret = clk_enable(&clk);
49 if (ret && ret != -ENOSYS) {
50 dev_err(dev, "failed to enable clock\n");
51 return ret;
52 }
53
Siva Durga Prasad Paladugueddabd12014-07-08 15:31:04 +053054 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
Siva Durga Prasad Paladuguf9ec45d2014-01-22 09:17:09 +010055 SDHCI_QUIRK_BROKEN_R1B;
Siva Durga Prasad Paladugub2156142016-01-12 15:12:16 +053056
57#ifdef CONFIG_ZYNQ_HISPD_BROKEN
58 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
59#endif
60
Stefan Herbrechtsmeiere0f4de12017-01-17 16:27:32 +010061 host->max_clk = clock;
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +010062
Stefan Herbrechtsmeiere0f4de12017-01-17 16:27:32 +010063 ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
Jaehoon Chung14bed522016-07-26 19:06:24 +090064 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
Simon Glass329a4492016-07-05 17:10:15 -060065 host->mmc = &plat->mmc;
66 if (ret)
67 return ret;
68 host->mmc->priv = host;
Simon Glasscffe5d82016-05-01 13:52:34 -060069 host->mmc->dev = dev;
Simon Glass329a4492016-07-05 17:10:15 -060070 upriv->mmc = host->mmc;
Michal Simekd9ae52c2015-11-30 16:13:03 +010071
Simon Glass329a4492016-07-05 17:10:15 -060072 return sdhci_probe(dev);
Michal Simek293eb332013-04-22 14:56:49 +020073}
Michal Simekd9ae52c2015-11-30 16:13:03 +010074
75static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
76{
77 struct sdhci_host *host = dev_get_priv(dev);
78
Masahiro Yamadacacd1d22016-04-22 20:59:31 +090079 host->name = dev->name;
Michal Simekd9ae52c2015-11-30 16:13:03 +010080 host->ioaddr = (void *)dev_get_addr(dev);
81
82 return 0;
83}
84
Simon Glass329a4492016-07-05 17:10:15 -060085static int arasan_sdhci_bind(struct udevice *dev)
86{
87 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
Simon Glass329a4492016-07-05 17:10:15 -060088
Masahiro Yamada24f5aec2016-09-06 22:17:32 +090089 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
Simon Glass329a4492016-07-05 17:10:15 -060090}
91
Michal Simekd9ae52c2015-11-30 16:13:03 +010092static const struct udevice_id arasan_sdhci_ids[] = {
93 { .compatible = "arasan,sdhci-8.9a" },
94 { }
95};
96
97U_BOOT_DRIVER(arasan_sdhci_drv) = {
98 .name = "arasan_sdhci",
99 .id = UCLASS_MMC,
100 .of_match = arasan_sdhci_ids,
101 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
Simon Glass329a4492016-07-05 17:10:15 -0600102 .ops = &sdhci_ops,
103 .bind = arasan_sdhci_bind,
Michal Simekd9ae52c2015-11-30 16:13:03 +0100104 .probe = arasan_sdhci_probe,
105 .priv_auto_alloc_size = sizeof(struct sdhci_host),
Simon Glass329a4492016-07-05 17:10:15 -0600106 .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
Michal Simekd9ae52c2015-11-30 16:13:03 +0100107};