blob: 72288fe4e810627453528d6818ca32999f1696b8 [file] [log] [blame]
Matthias Weisser18a056a2010-08-09 13:31:51 +02001/*
2 * (c) 2010 Graf-Syteco, Matthias Weisser
3 * <weisserm@arcor.de>
4 *
5 * (C) Copyright 2007, mycable GmbH
6 * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <netdev.h>
26#include <asm/io.h>
27#include <asm/arch/mb86r0x.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
31/*
32 * Miscellaneous platform dependent initialisations
33 */
34int board_init(void)
35{
36 struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
37 MB86R0x_CCNT_BASE;
38
39 /* We select mode 0 for group 2 and mode 1 for group 4 */
40 writel(0x00000010, &ccnt->cmux_md);
41
42 gd->flags = 0;
Matthias Weisser18a056a2010-08-09 13:31:51 +020043 gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
44
45 icache_enable();
Matthias Weissera91916f2011-06-29 02:08:07 +000046 dcache_enable();
Matthias Weisser18a056a2010-08-09 13:31:51 +020047
48 return 0;
49}
50
51static void setup_display_power(uint32_t pwr_bit, char *pwm_opts,
52 unsigned long pwm_base)
53{
54 struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
55 MB86R0x_GPIO_BASE;
56 struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base;
57 const char *e;
58
59 writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2);
60
61 e = getenv(pwm_opts);
62 if (e != NULL) {
63 const char *s;
64 uint32_t freq, init;
65
66 freq = 0;
67 init = 0;
68
69 s = strchr(e, 'f');
70 if (s != NULL)
71 freq = simple_strtol(s + 2, NULL, 0);
72
73 s = strchr(e, 'i');
74 if (s != NULL)
75 init = simple_strtol(s + 2, NULL, 0);
76
77 if (freq > 0) {
78 writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
79 &pwm->bcr);
80 writel(1002, &pwm->tpr);
81 writel(1, &pwm->pr);
82 writel(init * 10 + 1, &pwm->dr);
83 writel(1, &pwm->cr);
84 writel(1, &pwm->sr);
85 }
86 }
87}
88
89int board_late_init(void)
90{
91 struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
92 MB86R0x_GPIO_BASE;
93 uint32_t in_word;
94
95#ifdef CONFIG_VIDEO_MB86R0xGDC
96 /* Check if we have valid display settings and turn on power if so */
97 /* Display 0 */
98 if (getenv("gs_dsp_0_param") || getenv("videomode"))
99 setup_display_power((1 << 3), "gs_dsp_0_pwm",
100 MB86R0x_PWM0_BASE);
101
102 /* The corresponding GPIO is always an output */
103 writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
104
105 /* Display 1 */
106 if (getenv("gs_dsp_1_param") || getenv("videomode1"))
107 setup_display_power((1 << 4), "gs_dsp_1_pwm",
108 MB86R0x_PWM1_BASE);
109
110 /* The corresponding GPIO is always an output */
111 writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
112#endif /* CONFIG_VIDEO_MB86R0xGDC */
113
114 /* 5V enable */
115 writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
116 writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
117
118 /* We have special boot options if told by GPIOs */
119 in_word = readl(&gpio->gpdr1);
120
121 if ((in_word & 0xC0) == 0xC0) {
122 setenv("stdin", "serial");
123 setenv("stdout", "serial");
124 setenv("stderr", "serial");
125 setenv("preboot", "run gs_slow_boot");
126 } else if ((in_word & 0xC0) != 0) {
127 setenv("stdout", "vga");
Matthias Weisser18a056a2010-08-09 13:31:51 +0200128 setenv("preboot", "run gs_slow_boot");
129 } else {
130 setenv("stdin", "serial");
131 setenv("stdout", "serial");
132 setenv("stderr", "serial");
133 if (getenv("gs_devel")) {
134 setenv("preboot", "run gs_slow_boot");
135 } else {
Matthias Weisser18a056a2010-08-09 13:31:51 +0200136 setenv("preboot", "run gs_fast_boot");
137 }
138 }
139
140 return 0;
141}
142
143int misc_init_r(void)
144{
145 return 0;
146}
147
148/*
149 * DRAM configuration
150 */
151int dram_init(void)
152{
Matthias Weisserb9d74b42010-09-21 15:37:44 +0200153 /* dram_init must store complete ramsize in gd->ram_size */
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +0000154 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
Matthias Weisserb9d74b42010-09-21 15:37:44 +0200155 PHYS_SDRAM_SIZE);
Matthias Weisser18a056a2010-08-09 13:31:51 +0200156
157 return 0;
158}
159
Matthias Weisserb9d74b42010-09-21 15:37:44 +0200160void dram_init_banksize(void)
161{
162 gd->bd->bi_dram[0].start = PHYS_SDRAM;
163 gd->bd->bi_dram[0].size = gd->ram_size;
164}
165
Matthias Weisser18a056a2010-08-09 13:31:51 +0200166int board_eth_init(bd_t *bis)
167{
168 int rc = 0;
169#ifdef CONFIG_SMC911X
170 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
171#endif
172 return rc;
173}