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Simon Glass1f8f7732015-08-30 16:55:27 -06001/*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * (C) Copyright 2008-2014 Rockchip Electronics
5 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <dm.h>
Simon Glass48647822016-01-21 19:44:09 -070012#include <syscon.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090013#include <linux/errno.h>
Simon Glass1f8f7732015-08-30 16:55:27 -060014#include <asm/gpio.h>
15#include <asm/io.h>
Simon Glass48647822016-01-21 19:44:09 -070016#include <asm/arch/clock.h>
17#include <dm/pinctrl.h>
Simon Glass48647822016-01-21 19:44:09 -070018#include <dt-bindings/clock/rk3288-cru.h>
Simon Glass1f8f7732015-08-30 16:55:27 -060019
20enum {
21 ROCKCHIP_GPIOS_PER_BANK = 32,
22};
23
24#define OFFSET_TO_BIT(bit) (1UL << (bit))
25
26struct rockchip_gpio_priv {
27 struct rockchip_gpio_regs *regs;
Simon Glass48647822016-01-21 19:44:09 -070028 struct udevice *pinctrl;
29 int bank;
Simon Glass1f8f7732015-08-30 16:55:27 -060030 char name[2];
31};
32
33static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
34{
35 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
36 struct rockchip_gpio_regs *regs = priv->regs;
37
38 clrbits_le32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
39
40 return 0;
41}
42
43static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
44 int value)
45{
46 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
47 struct rockchip_gpio_regs *regs = priv->regs;
48 int mask = OFFSET_TO_BIT(offset);
49
50 clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
51 setbits_le32(&regs->swport_ddr, mask);
52
53 return 0;
54}
55
56static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
57{
58 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
59 struct rockchip_gpio_regs *regs = priv->regs;
60
Simon Glass7d0c2c32016-01-21 19:44:08 -070061 return readl(&regs->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0;
Simon Glass1f8f7732015-08-30 16:55:27 -060062}
63
64static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
65 int value)
66{
67 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
68 struct rockchip_gpio_regs *regs = priv->regs;
69 int mask = OFFSET_TO_BIT(offset);
70
71 clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
72
73 return 0;
74}
75
76static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
77{
Simon Glass48647822016-01-21 19:44:09 -070078#ifdef CONFIG_SPL_BUILD
79 return -ENODATA;
80#else
81 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
82 struct rockchip_gpio_regs *regs = priv->regs;
83 bool is_output;
84 int ret;
85
86 ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
87 if (ret)
88 return ret;
89
90 /* If it's not 0, then it is not a GPIO */
91 if (ret)
92 return GPIOF_FUNC;
93 is_output = readl(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
94
95 return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
96#endif
Simon Glass1f8f7732015-08-30 16:55:27 -060097}
98
Simon Glass1f8f7732015-08-30 16:55:27 -060099static int rockchip_gpio_probe(struct udevice *dev)
100{
101 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
102 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
103 char *end;
Simon Glass48647822016-01-21 19:44:09 -0700104 int ret;
Simon Glass1f8f7732015-08-30 16:55:27 -0600105
Simon Glass48647822016-01-21 19:44:09 -0700106 /* This only supports RK3288 at present */
Simon Glass1f8f7732015-08-30 16:55:27 -0600107 priv->regs = (struct rockchip_gpio_regs *)dev_get_addr(dev);
Simon Glass3f603cb2016-02-11 13:23:26 -0700108 ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
Simon Glass48647822016-01-21 19:44:09 -0700109 if (ret)
110 return ret;
Simon Glass48647822016-01-21 19:44:09 -0700111
Simon Glass1f8f7732015-08-30 16:55:27 -0600112 uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
113 end = strrchr(dev->name, '@');
Simon Glass48647822016-01-21 19:44:09 -0700114 priv->bank = trailing_strtoln(dev->name, end);
115 priv->name[0] = 'A' + priv->bank;
Simon Glass1f8f7732015-08-30 16:55:27 -0600116 uc_priv->bank_name = priv->name;
117
118 return 0;
119}
120
121static const struct dm_gpio_ops gpio_rockchip_ops = {
122 .direction_input = rockchip_gpio_direction_input,
123 .direction_output = rockchip_gpio_direction_output,
124 .get_value = rockchip_gpio_get_value,
125 .set_value = rockchip_gpio_set_value,
126 .get_function = rockchip_gpio_get_function,
Simon Glass1f8f7732015-08-30 16:55:27 -0600127};
128
129static const struct udevice_id rockchip_gpio_ids[] = {
130 { .compatible = "rockchip,gpio-bank" },
131 { }
132};
133
134U_BOOT_DRIVER(gpio_rockchip) = {
135 .name = "gpio_rockchip",
136 .id = UCLASS_GPIO,
137 .of_match = rockchip_gpio_ids,
138 .ops = &gpio_rockchip_ops,
139 .priv_auto_alloc_size = sizeof(struct rockchip_gpio_priv),
140 .probe = rockchip_gpio_probe,
141};