| wdenk | 2d1a537 | 2004-02-23 19:30:57 +0000 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-armnommu/arch-netarm/netarm_eth_module.h |
| 3 | * |
| 4 | * Copyright (C) 2000 NETsilicon, Inc. |
| 5 | * Copyright (C) 2000 WireSpeed Communications Corporation |
| 6 | * |
| 7 | * This software is copyrighted by WireSpeed. LICENSEE agrees that |
| 8 | * it will not delete this copyright notice, trademarks or protective |
| 9 | * notices from any copy made by LICENSEE. |
| 10 | * |
| 11 | * This software is provided "AS-IS" and any express or implied |
| 12 | * warranties or conditions, including but not limited to any |
| 13 | * implied warranties of merchantability and fitness for a particular |
| 14 | * purpose regarding this software. In no event shall WireSpeed |
| 15 | * be liable for any indirect, consequential, or incidental damages, |
| 16 | * loss of profits or revenue, loss of use or data, or interruption |
| 17 | * of business, whether the alleged damages are labeled in contract, |
| 18 | * tort, or indemnity. |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License as published by |
| 22 | * the Free Software Foundation; either version 2 of the License, or |
| 23 | * (at your option) any later version. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 28 | * |
| 29 | * author(s) : Jackie Smith Cashion |
| 30 | * David Smith |
| 31 | */ |
| 32 | |
| 33 | #ifndef __NETARM_ETH_MODULE_REGISTERS_H |
| 34 | #define __NETARM_ETH_MODULE_REGISTERS_H |
| 35 | |
| 36 | /* ETH unit register offsets */ |
| 37 | |
| 38 | #define NETARM_ETH_MODULE_BASE (0xFF800000) |
| 39 | |
| 40 | #define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c))) |
| 41 | |
| 42 | #define NETARM_ETH_GEN_CTRL (0x000) /* Ethernet Gen Control Reg */ |
| 43 | #define NETARM_ETH_GEN_STAT (0x004) /* Ethernet Gen Status Reg */ |
| 44 | #define NETARM_ETH_FIFO_DAT1 (0x008) /* Fifo Data Reg 1 */ |
| 45 | #define NETARM_ETH_FIFO_DAT2 (0x00C) /* Fifo Data Reg 2 */ |
| 46 | #define NETARM_ETH_TX_STAT (0x010) /* Transmit Status Reg */ |
| 47 | #define NETARM_ETH_RX_STAT (0x014) /* Receive Status Reg */ |
| 48 | |
| 49 | #define NETARM_ETH_MAC_CFG (0x400) /* MAC Configuration Reg */ |
| 50 | #define NETARM_ETH_PCS_CFG (0x408) /* PCS Configuration Reg */ |
| 51 | #define NETARM_ETH_STL_CFG (0x410) /* STL Configuration Reg */ |
| 52 | #define NETARM_ETH_B2B_IPG_GAP_TMR (0x440) /* Back-to-back IPG |
| 53 | Gap Timer Reg */ |
| 54 | #define NETARM_ETH_NB2B_IPG_GAP_TMR (0x444) /* Non Back-to-back |
| 55 | IPG Gap Timer Reg */ |
| 56 | #define NETARM_ETH_MII_CMD (0x540) /* MII (PHY) Command Reg */ |
| 57 | #define NETARM_ETH_MII_ADDR (0x544) /* MII Address Reg */ |
| 58 | #define NETARM_ETH_MII_WRITE (0x548) /* MII Write Data Reg */ |
| 59 | #define NETARM_ETH_MII_READ (0x54C) /* MII Read Data Reg */ |
| 60 | #define NETARM_ETH_MII_IND (0x550) /* MII Indicators Reg */ |
| 61 | #define NETARM_ETH_MIB_CRCEC (0x580) /* (MIB) CRC Error Counter */ |
| 62 | #define NETARM_ETH_MIB_AEC (0x584) /* Alignment Error Counter */ |
| 63 | #define NETARM_ETH_MIB_CEC (0x588) /* Code Error Counter */ |
| 64 | #define NETARM_ETH_MIB_LFC (0x58C) /* Long Frame Counter */ |
| 65 | #define NETARM_ETH_MIB_SFC (0x590) /* Short Frame Counter */ |
| 66 | #define NETARM_ETH_MIB_LCC (0x594) /* Late Collision Counter */ |
| 67 | #define NETARM_ETH_MIB_EDC (0x598) /* Excessive Deferral |
| 68 | Counter */ |
| 69 | #define NETARM_ETH_MIB_MCC (0x59C) /* Maximum Collision Counter */ |
| 70 | #define NETARM_ETH_SAL_FILTER (0x5C0) /* SAL Station Address |
| 71 | Filter Reg */ |
| 72 | #define NETARM_ETH_SAL_STATION_ADDR_1 (0x5C4) /* SAL Station Address |
| 73 | Reg */ |
| 74 | #define NETARM_ETH_SAL_STATION_ADDR_2 (0x5C8) |
| 75 | #define NETARM_ETH_SAL_STATION_ADDR_3 (0x5CC) |
| 76 | #define NETARM_ETH_SAL_HASH_TBL_1 (0x5D0) /* SAL Multicast Hash Table*/ |
| 77 | #define NETARM_ETH_SAL_HASH_TBL_2 (0x5D4) |
| 78 | #define NETARM_ETH_SAL_HASH_TBL_3 (0x5D8) |
| 79 | #define NETARM_ETH_SAL_HASH_TBL_4 (0x5DC) |
| 80 | |
| 81 | /* select bitfield defintions */ |
| 82 | |
| 83 | /* Ethernet General Control Register (0xFF80_0000) */ |
| 84 | |
| 85 | #define NETARM_ETH_GCR_ERX (0x80000000) /* Enable Receive FIFO */ |
| 86 | #define NETARM_ETH_GCR_ERXDMA (0x40000000) /* Enable Receive DMA */ |
| 87 | #define NETARM_ETH_GCR_ETX (0x00800000) /* Enable Transmit FIFO */ |
| 88 | #define NETARM_ETH_GCR_ETXDMA (0x00400000) /* Enable Transmit DMA */ |
| 89 | #define NETARM_ETH_GCR_ETXWM_50 (0x00100000) /* Transmit FIFO Water |
| 90 | Mark. Start transmit |
| 91 | when FIFO is 50% |
| 92 | full. */ |
| 93 | #define NETARM_ETH_GCR_PNA (0x00000400) /* pSOS pNA Buffer |
| 94 | Descriptor Format */ |
| 95 | |
| 96 | /* Ethernet General Status Register (0xFF80_0004) */ |
| 97 | |
| 98 | #define NETARM_ETH_GST_RXFDB (0x30000000) |
| 99 | #define NETARM_ETH_GST_RXREGR (0x08000000) /* Receive Register |
| 100 | Ready */ |
| 101 | #define NETARM_ETH_GST_RXFIFOH (0x04000000) |
| 102 | #define NETARM_ETH_GST_RXBR (0x02000000) |
| 103 | #define NETARM_ETH_GST_RXSKIP (0x01000000) |
| 104 | |
| 105 | #define NETARM_ETH_GST_TXBC (0x00020000) |
| 106 | |
| 107 | |
| 108 | /* Ethernet Transmit Status Register (0xFF80_0010) */ |
| 109 | |
| 110 | #define NETARM_ETH_TXSTAT_TXOK (0x00008000) |
| 111 | |
| 112 | |
| 113 | /* Ethernet Receive Status Register (0xFF80_0014) */ |
| 114 | |
| 115 | #define NETARM_ETH_RXSTAT_SIZE (0xFFFF0000) |
| 116 | #define NETARM_ETH_RXSTAT_RXOK (0x00002000) |
| 117 | |
| 118 | |
| 119 | /* PCS Configuration Register (0xFF80_0408) */ |
| 120 | |
| 121 | #define NETARM_ETH_PCSC_NOCFR (0x1) /* Disable Ciphering */ |
| 122 | #define NETARM_ETH_PCSC_ENJAB (0x2) /* Enable Jabber Protection */ |
| 123 | #define NETARM_ETH_PCSC_CLKS_25M (0x0) /* 25 MHz Clock Speed Select */ |
| 124 | #define NETARM_ETH_PCSC_CLKS_33M (0x4) /* 33 MHz Clock Speed Select */ |
| 125 | |
| 126 | /* STL Configuration Register (0xFF80_0410) */ |
| 127 | |
| 128 | #define NETARM_ETH_STLC_RXEN (0x2) /* Enable Packet Receiver */ |
| 129 | #define NETARM_ETH_STLC_AUTOZ (0x4) /* Auto Zero Statistics */ |
| 130 | |
| 131 | /* MAC Configuration Register (0xFF80_0400) */ |
| 132 | |
| 133 | #define NETARM_ETH_MACC_HUGEN (0x1) /* Enable Unlimited Transmit |
| 134 | Frame Sizes */ |
| 135 | #define NETARM_ETH_MACC_PADEN (0x4) /* Automatic Pad Fill Frames |
| 136 | to 64 Bytes */ |
| 137 | #define NETARM_ETH_MACC_CRCEN (0x8) /* Append CRC to Transmit |
| 138 | Frames */ |
| 139 | |
| 140 | /* MII (PHY) Command Register (0xFF80_0540) */ |
| 141 | |
| 142 | #define NETARM_ETH_MIIC_RSTAT (0x1) /* Single Scan for Read Data */ |
| 143 | |
| 144 | /* MII Indicators Register (0xFF80_0550) */ |
| 145 | |
| 146 | #define NETARM_ETH_MIII_BUSY (0x1) /* MII I/F Busy with |
| 147 | Read/Write */ |
| 148 | |
| 149 | /* SAL Station Address Filter Register (0xFF80_05C0) */ |
| 150 | |
| 151 | #define NETARM_ETH_SALF_PRO (0x8) /* Enable Promiscuous Mode */ |
| 152 | #define NETARM_ETH_SALF_PRM (0x4) /* Accept All Multicast |
| 153 | Packets */ |
| 154 | #define NETARM_ETH_SALF_PRA (0x2) /* Accept Mulitcast Packets |
| 155 | using Hash Table */ |
| 156 | #define NETARM_ETH_SALF_BROAD (0x1) /* Accept All Broadcast |
| 157 | Packets */ |
| 158 | |
| 159 | |
| 160 | #endif /* __NETARM_GEN_MODULE_REGISTERS_H */ |