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wdenkf12e5682003-07-07 20:07:54 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
38
39#ifdef CONFIG_LCD /* with LCD controller ? */
wdenkfd3103b2003-11-25 16:55:19 +000040/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
wdenkf12e5682003-07-07 20:07:54 +000041#endif
42
43#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
44#undef CONFIG_8xx_CONS_SMC2
45#undef CONFIG_8xx_CONS_NONE
46#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf12e5682003-07-07 20:07:54 +000047
wdenkae3af052003-08-07 22:18:11 +000048#define CONFIG_BOOTCOUNT_LIMIT
49
50#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000051
52#define CONFIG_BOARD_TYPES 1 /* support board types */
53
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010054#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf12e5682003-07-07 20:07:54 +000055
56#undef CONFIG_BOOTARGS
57
58#define CONFIG_EXTRA_ENV_SETTINGS \
59 "netdev=eth0\0" \
60 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010061 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000062 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010063 "addip=setenv bootargs ${bootargs} " \
64 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
65 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000066 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010067 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000068 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010069 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
70 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000071 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020072 "hostname=TQM823M\0" \
73 "bootfile=TQM823M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020074 "fdt_addr=40080000\0" \
75 "kernel_addr=400A0000\0" \
76 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020077 "u-boot=TQM823M/u-image.bin\0" \
78 "load=tftp 200000 ${u-boot}\0" \
79 "update=prot off 40000000 +${filesize};" \
80 "era 40000000 +${filesize};" \
81 "cp.b 200000 40000000 ${filesize};" \
82 "sete filesize;save\0" \
wdenkf12e5682003-07-07 20:07:54 +000083 ""
84#define CONFIG_BOOTCOMMAND "run flash_self"
85
86#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
87#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
88
89#undef CONFIG_WATCHDOG /* watchdog disabled */
90
91#ifdef CONFIG_LCD
92# undef CONFIG_STATUS_LED /* disturbs display */
93#else
94# define CONFIG_STATUS_LED 1 /* Status LED enabled */
95#endif /* CONFIG_LCD */
96
97#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
98
Jon Loeliger37d4bb72007-07-09 21:38:02 -050099/*
100 * BOOTP options
101 */
102#define CONFIG_BOOTP_SUBNETMASK
103#define CONFIG_BOOTP_GATEWAY
104#define CONFIG_BOOTP_HOSTNAME
105#define CONFIG_BOOTP_BOOTPATH
106#define CONFIG_BOOTP_BOOTFILESIZE
107
wdenkf12e5682003-07-07 20:07:54 +0000108
109#define CONFIG_MAC_PARTITION
110#define CONFIG_DOS_PARTITION
111
112#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
113
wdenkf12e5682003-07-07 20:07:54 +0000114
Jon Loeliger26946902007-07-04 22:30:50 -0500115/*
116 * Command line configuration.
117 */
118#include <config_cmd_default.h>
119
120#define CONFIG_CMD_ASKENV
121#define CONFIG_CMD_DATE
122#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200123#define CONFIG_CMD_ELF
Jon Loeliger26946902007-07-04 22:30:50 -0500124#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200125#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500126#define CONFIG_CMD_NFS
127#define CONFIG_CMD_SNTP
128
wdenkf12e5682003-07-07 20:07:54 +0000129
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200130#define CONFIG_NETCONSOLE
131
132
wdenkf12e5682003-07-07 20:07:54 +0000133/*
134 * Miscellaneous configurable options
135 */
136#define CFG_LONGHELP /* undef to save memory */
137#define CFG_PROMPT "=> " /* Monitor Command Prompt */
138
Wolfgang Denk2751a952006-10-28 02:29:14 +0200139#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
140#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf12e5682003-07-07 20:07:54 +0000141#ifdef CFG_HUSH_PARSER
142#define CFG_PROMPT_HUSH_PS2 "> "
143#endif
144
Jon Loeliger26946902007-07-04 22:30:50 -0500145#if defined(CONFIG_CMD_KGDB)
wdenkf12e5682003-07-07 20:07:54 +0000146#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
147#else
148#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
149#endif
150#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
151#define CFG_MAXARGS 16 /* max number of command args */
152#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
153
154#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
155#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
156
157#define CFG_LOAD_ADDR 0x100000 /* default load address */
158
159#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
160
161#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
162
163/*
164 * Low Level Configuration Settings
165 * (address mappings, register initial values, etc.)
166 * You should know what you are doing if you make changes here.
167 */
168/*-----------------------------------------------------------------------
169 * Internal Memory Mapped Register
170 */
171#define CFG_IMMR 0xFFF00000
172
173/*-----------------------------------------------------------------------
174 * Definitions for initial stack pointer and data area (in DPRAM)
175 */
176#define CFG_INIT_RAM_ADDR CFG_IMMR
177#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
178#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
179#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
180#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
181
182/*-----------------------------------------------------------------------
183 * Start addresses for the final memory configuration
184 * (Set up by the startup code)
185 * Please note that CFG_SDRAM_BASE _must_ start at 0
186 */
187#define CFG_SDRAM_BASE 0x00000000
188#define CFG_FLASH_BASE 0x40000000
189#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
190#define CFG_MONITOR_BASE CFG_FLASH_BASE
191#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
192
193/*
194 * For booting Linux, the board info and command line data
195 * have to be in the first 8 MB of memory, since this is
196 * the maximum mapped by the Linux kernel during initialization.
197 */
198#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
199
200/*-----------------------------------------------------------------------
201 * FLASH organization
202 */
wdenkf12e5682003-07-07 20:07:54 +0000203
Martin Krausee318d9e2007-09-27 11:10:08 +0200204/* use CFI flash driver */
205#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200206#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Martin Krausee318d9e2007-09-27 11:10:08 +0200207#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
208#define CFG_FLASH_EMPTY_INFO
209#define CFG_FLASH_USE_BUFFER_WRITE 1
210#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
211#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000212
213#define CFG_ENV_IS_IN_FLASH 1
214#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
Martin Krausee318d9e2007-09-27 11:10:08 +0200215#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */
wdenkf12e5682003-07-07 20:07:54 +0000216#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
217
218/* Address and size of Redundant Environment Sector */
219#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
220#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
221
Wolfgang Denk67c31032007-09-16 17:10:04 +0200222#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
223
wdenkf12e5682003-07-07 20:07:54 +0000224/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200225 * Dynamic MTD partition support
226 */
227#define CONFIG_JFFS2_CMDLINE
228#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
229
230#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
231 "128k(dtb)," \
232 "1920k(kernel)," \
233 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200234 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200235
236/*-----------------------------------------------------------------------
wdenkf12e5682003-07-07 20:07:54 +0000237 * Hardware Information Block
238 */
239#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
240#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
241#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
242
243/*-----------------------------------------------------------------------
244 * Cache Configuration
245 */
246#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500247#if defined(CONFIG_CMD_KGDB)
wdenkf12e5682003-07-07 20:07:54 +0000248#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
249#endif
250
251/*-----------------------------------------------------------------------
252 * SYPCR - System Protection Control 11-9
253 * SYPCR can only be written once after reset!
254 *-----------------------------------------------------------------------
255 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
256 */
257#if defined(CONFIG_WATCHDOG)
258#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
259 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
260#else
261#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
262#endif
263
264/*-----------------------------------------------------------------------
265 * SIUMCR - SIU Module Configuration 11-6
266 *-----------------------------------------------------------------------
267 * PCMCIA config., multi-function pin tri-state
268 */
269#ifndef CONFIG_CAN_DRIVER
270#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
271#else /* we must activate GPL5 in the SIUMCR for CAN */
272#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
273#endif /* CONFIG_CAN_DRIVER */
274
275/*-----------------------------------------------------------------------
276 * TBSCR - Time Base Status and Control 11-26
277 *-----------------------------------------------------------------------
278 * Clear Reference Interrupt Status, Timebase freezing enabled
279 */
280#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
281
282/*-----------------------------------------------------------------------
283 * RTCSC - Real-Time Clock Status and Control Register 11-27
284 *-----------------------------------------------------------------------
285 */
286#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
287
288/*-----------------------------------------------------------------------
289 * PISCR - Periodic Interrupt Status and Control 11-31
290 *-----------------------------------------------------------------------
291 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
292 */
293#define CFG_PISCR (PISCR_PS | PISCR_PITF)
294
295/*-----------------------------------------------------------------------
296 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
297 *-----------------------------------------------------------------------
298 * Reset PLL lock status sticky bit, timer expired status bit and timer
299 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000300 */
wdenkf12e5682003-07-07 20:07:54 +0000301#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000302
303/*-----------------------------------------------------------------------
304 * SCCR - System Clock and reset Control Register 15-27
305 *-----------------------------------------------------------------------
306 * Set clock output, timebase and RTC source and divider,
307 * power management and some other internal clocks
308 */
309#define SCCR_MASK SCCR_EBDF11
wdenke9132ea2004-04-24 23:23:30 +0000310#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000311 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
312 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000313
314/*-----------------------------------------------------------------------
315 * PCMCIA stuff
316 *-----------------------------------------------------------------------
317 *
318 */
319#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
320#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
321#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
322#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
323#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
324#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
325#define CFG_PCMCIA_IO_ADDR (0xEC000000)
326#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
327
328/*-----------------------------------------------------------------------
329 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
330 *-----------------------------------------------------------------------
331 */
332
333#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
334
335#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
336#undef CONFIG_IDE_LED /* LED for ide not supported */
337#undef CONFIG_IDE_RESET /* reset for ide not supported */
338
339#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
340#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
341
342#define CFG_ATA_IDE0_OFFSET 0x0000
343
344#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
345
346/* Offset for data I/O */
347#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
348
349/* Offset for normal register accesses */
350#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
351
352/* Offset for alternate registers */
353#define CFG_ATA_ALT_OFFSET 0x0100
354
355/*-----------------------------------------------------------------------
356 *
357 *-----------------------------------------------------------------------
358 *
359 */
360#define CFG_DER 0
361
362/*
363 * Init Memory Controller:
364 *
365 * BR0/1 and OR0/1 (FLASH)
366 */
367
368#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
369#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
370
371/* used to re-map FLASH both when starting from SRAM or FLASH:
372 * restrict access enough to keep SRAM working (if any)
373 * but not too much to meddle with FLASH accesses
374 */
375#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
376#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
377
378/*
379 * FLASH timing:
380 */
wdenkf12e5682003-07-07 20:07:54 +0000381#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
382 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000383
384#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
385#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
386#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
387
388#define CFG_OR1_REMAP CFG_OR0_REMAP
389#define CFG_OR1_PRELIM CFG_OR0_PRELIM
390#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
391
392/*
393 * BR2/3 and OR2/3 (SDRAM)
394 *
395 */
396#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
397#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
398#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
399
400/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
401#define CFG_OR_TIMING_SDRAM 0x00000A00
402
403#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
404#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
405
406#ifndef CONFIG_CAN_DRIVER
407#define CFG_OR3_PRELIM CFG_OR2_PRELIM
408#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
409#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
410#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
411#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
412#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
413#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
414 BR_PS_8 | BR_MS_UPMB | BR_V )
415#endif /* CONFIG_CAN_DRIVER */
416
417/*
418 * Memory Periodic Timer Prescaler
419 *
420 * The Divider for PTA (refresh timer) configuration is based on an
421 * example SDRAM configuration (64 MBit, one bank). The adjustment to
422 * the number of chip selects (NCS) and the actually needed refresh
423 * rate is done by setting MPTPR.
424 *
425 * PTA is calculated from
426 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
427 *
428 * gclk CPU clock (not bus clock!)
429 * Trefresh Refresh cycle * 4 (four word bursts used)
430 *
431 * 4096 Rows from SDRAM example configuration
432 * 1000 factor s -> ms
433 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
434 * 4 Number of refresh cycles per period
435 * 64 Refresh cycle in ms per number of rows
436 * --------------------------------------------
437 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
438 *
439 * 50 MHz => 50.000.000 / Divider = 98
440 * 66 Mhz => 66.000.000 / Divider = 129
441 * 80 Mhz => 80.000.000 / Divider = 156
442 */
wdenke9132ea2004-04-24 23:23:30 +0000443
444#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
445#define CFG_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000446
447/*
448 * For 16 MBit, refresh rates could be 31.3 us
449 * (= 64 ms / 2K = 125 / quad bursts).
450 * For a simpler initialization, 15.6 us is used instead.
451 *
452 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
453 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
454 */
455#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
456#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
457
458/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
459#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
460#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
461
462/*
463 * MAMR settings for SDRAM
464 */
465
466/* 8 column SDRAM */
467#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
468 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
469 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
470/* 9 column SDRAM */
471#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
472 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
473 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
474
475
476/*
477 * Internal Definitions
478 *
479 * Boot Flags
480 */
481#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
482#define BOOTFLAG_WARM 0x02 /* Software reboot */
483
484#endif /* __CONFIG_H */