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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/***********************************************************
32 * High Level Configuration Options
33 * (easy to change)
34 ***********************************************************/
35#define CONFIG_405GP 1 /* This is a PPC405 CPU */
36#define CONFIG_4xx 1 /* ...member of PPC4xx family */
37#define CONFIG_PIP405 1 /* ...on a PIP405 board */
38/***********************************************************
39 * Clock
40 ***********************************************************/
41#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
42
Jon Loeligeracf02692007-07-08 14:49:44 -050043
44/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050045 * BOOTP options
46 */
47#define CONFIG_BOOTP_BOOTFILESIZE
48#define CONFIG_BOOTP_BOOTPATH
49#define CONFIG_BOOTP_GATEWAY
50#define CONFIG_BOOTP_HOSTNAME
51
52
53/*
Jon Loeligeracf02692007-07-08 14:49:44 -050054 * Command line configuration.
55 */
56#include <config_cmd_default.h>
57
58#define CONFIG_CMD_IDE
59#define CONFIG_CMD_DHCP
60#define CONFIG_CMD_PCI
61#define CONFIG_CMD_CACHE
62#define CONFIG_CMD_IRQ
63#define CONFIG_CMD_EEPROM
64#define CONFIG_CMD_I2C
65#define CONFIG_CMD_REGINFO
66#define CONFIG_CMD_FDC
67#define CONFIG_CMD_SCSI
68#define CONFIG_CMD_FAT
69#define CONFIG_CMD_DATE
70#define CONFIG_CMD_ELF
71#define CONFIG_CMD_USB
72#define CONFIG_CMD_MII
73#define CONFIG_CMD_SDRAM
74#define CONFIG_CMD_DOC
75#define CONFIG_CMD_PING
76#define CONFIG_CMD_SAVES
77#define CONFIG_CMD_BSP
78
wdenkc6097192002-11-03 00:24:07 +000079
Jean-Christophe PLAGNIOL-VILLARDcc4a0ce2008-08-13 01:40:43 +020080#define CONFIG_NAND_LEGACY
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +010081
wdenkc6097192002-11-03 00:24:07 +000082#define CFG_HUSH_PARSER
83#define CFG_PROMPT_HUSH_PS2 "> "
84/**************************************************************
85 * I2C Stuff:
86 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
87 * 0x53.
88 * Caution: on the same bus is the SPD (Serial Presens Detect
89 * EEPROM of the SDRAM
90 * The Atmel EEPROM uses 16Bit addressing.
91 ***************************************************************/
92#define CONFIG_HARD_I2C /* I2c with hardware support */
93#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
94#define CFG_I2C_SLAVE 0x7F
95
96#define CFG_I2C_EEPROM_ADDR 0x53
97#define CFG_I2C_EEPROM_ADDR_LEN 2
98#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
99#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
100#define CFG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
101
102#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
103#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
104 /* 64 byte page write mode using*/
105 /* last 6 bits of the address */
106#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
107#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
108
109
110/***************************************************************
111 * Definitions for Serial Presence Detect EEPROM address
112 * (to get SDRAM settings)
113 ***************************************************************/
114#define SPD_EEPROM_ADDRESS 0x50
115
wdenkc837dcb2004-01-20 23:12:12 +0000116#define CONFIG_BOARD_EARLY_INIT_F
wdenkc6097192002-11-03 00:24:07 +0000117/**************************************************************
118 * Environment definitions
119 **************************************************************/
120#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
121
122
123#define CONFIG_BOOTDELAY 5
124/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
Wolfgang Denk2afbe4e2005-08-13 02:04:37 +0200125/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200126#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
wdenkc6097192002-11-03 00:24:07 +0000127
128
wdenk3e386912003-04-05 00:53:31 +0000129#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
wdenkc6097192002-11-03 00:24:07 +0000130#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
131
132#define CONFIG_IPADDR 10.0.0.100
133#define CONFIG_SERVERIP 10.0.0.1
134#define CONFIG_PREBOOT
135/***************************************************************
136 * defines if the console is stored in the environment
137 ***************************************************************/
138#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
139/***************************************************************
140 * defines if an overwrite_console function exists
141 *************************************************************/
142#define CFG_CONSOLE_OVERWRITE_ROUTINE
143#define CFG_CONSOLE_INFO_QUIET
144/***************************************************************
145 * defines if the overwrite_console should be stored in the
146 * environment
147 **************************************************************/
148#undef CFG_CONSOLE_ENV_OVERWRITE
149
150/**************************************************************
151 * loads config
152 *************************************************************/
153#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
154#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
155
wdenk7205e402003-09-10 22:30:53 +0000156#define CONFIG_MISC_INIT_R
wdenkc6097192002-11-03 00:24:07 +0000157/***********************************************************
158 * Miscellaneous configurable options
159 **********************************************************/
160#define CFG_LONGHELP /* undef to save memory */
161#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligeracf02692007-07-08 14:49:44 -0500162#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000163#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
164#else
165#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
166#endif
167#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
168#define CFG_MAXARGS 16 /* max number of command args */
169#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
170
171#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
172#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
173
174#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
175#define CFG_BASE_BAUD 691200
176
177/* The following table includes the supported baudrates */
178#define CFG_BAUDRATE_TABLE \
179 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
180 57600, 115200, 230400, 460800, 921600 }
181
wdenk3e386912003-04-05 00:53:31 +0000182#define CFG_LOAD_ADDR 0x400000 /* default load address */
wdenkc6097192002-11-03 00:24:07 +0000183#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
184
185#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
186
187/*-----------------------------------------------------------------------
188 * PCI stuff
189 *-----------------------------------------------------------------------
190 */
191#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
192#define PCI_HOST_FORCE 1 /* configure as pci host */
193#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
194
195#define CONFIG_PCI /* include pci support */
196#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
197#define CONFIG_PCI_PNP /* pci plug-and-play */
198 /* resource configuration */
199#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
200#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
201#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
202#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
203#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
204#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
205#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
206#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
207
208/*-----------------------------------------------------------------------
209 * Start addresses for the final memory configuration
210 * (Set up by the startup code)
211 * Please note that CFG_SDRAM_BASE _must_ start at 0
212 */
213#define CFG_SDRAM_BASE 0x00000000
214#define CFG_FLASH_BASE 0xFFF80000
215#define CFG_MONITOR_BASE CFG_FLASH_BASE
216#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
wdenka2663ea2003-12-07 18:32:37 +0000217#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000218
219/*
220 * For booting Linux, the board info and command line data
221 * have to be in the first 8 MB of memory, since this is
222 * the maximum mapped by the Linux kernel during initialization.
223 */
224#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
225/*-----------------------------------------------------------------------
226 * FLASH organization
227 */
228#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
229#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
230
231#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
232#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
233
wdenkc6097192002-11-03 00:24:07 +0000234/*
235 * Init Memory Controller:
236 */
wdenk7205e402003-09-10 22:30:53 +0000237#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
238#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
239/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
240#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
wdenkc6097192002-11-03 00:24:07 +0000241
wdenkc837dcb2004-01-20 23:12:12 +0000242#define CONFIG_BOARD_EARLY_INIT_F
wdenkc6097192002-11-03 00:24:07 +0000243
244/* Configuration Port location */
245#define CONFIG_PORT_ADDR 0xF4000000
246#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
247
248
wdenkc6097192002-11-03 00:24:07 +0000249/*-----------------------------------------------------------------------
250 * Definitions for initial stack pointer and data area (in On Chip SRAM)
251 */
252#define CFG_TEMP_STACK_OCM 1
253#define CFG_OCM_DATA_ADDR 0xF0000000
254#define CFG_OCM_DATA_SIZE 0x1000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200255#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
wdenkc6097192002-11-03 00:24:07 +0000256#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
257#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
258#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
259#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
260
261/*
262 * Internal Definitions
263 *
264 * Boot Flags
265 */
266#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
267#define BOOTFLAG_WARM 0x02 /* Software reboot */
268
269
270/***********************************************************************
271 * External peripheral base address
272 ***********************************************************************/
273#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
274
275/***********************************************************************
276 * Last Stage Init
277 ***********************************************************************/
278#define CONFIG_LAST_STAGE_INIT
279/************************************************************
280 * Ethernet Stuff
281 ***********************************************************/
282#define CONFIG_MII 1 /* MII PHY management */
283#define CONFIG_PHY_ADDR 1 /* PHY address */
284#define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */
285/************************************************************
286 * RTC
287 ***********************************************************/
288#define CONFIG_RTC_MC146818
289#undef CONFIG_WATCHDOG /* watchdog disabled */
290
291/************************************************************
292 * IDE/ATA stuff
293 ************************************************************/
294#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
295#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
296
297#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
298#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
299#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
300#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
301#define CFG_ATA_REG_OFFSET 0 /* reg offset */
302#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
303
304#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
305#undef CONFIG_IDE_LED /* no led for ide supported */
306#define CONFIG_IDE_RESET /* reset for ide supported... */
307#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
wdenk7205e402003-09-10 22:30:53 +0000308#define CONFIG_SUPPORT_VFAT
wdenkc6097192002-11-03 00:24:07 +0000309
310/************************************************************
311 * ATAPI support (experimental)
312 ************************************************************/
313#define CONFIG_ATAPI /* enable ATAPI Support */
314
315/************************************************************
316 * SCSI support (experimental) only SYM53C8xx supported
317 ************************************************************/
318#define CONFIG_SCSI_SYM53C8XX
319#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
320#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
321#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
322#define CFG_SCSI_SPIN_UP_TIME 2
323
324/************************************************************
325 * Disk-On-Chip configuration
326 ************************************************************/
327#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
328#define CFG_DOC_SHORT_TIMEOUT
329#define CFG_DOC_SUPPORT_2000
330#define CFG_DOC_SUPPORT_MILLENNIUM
331
332/************************************************************
333 * DISK Partition support
334 ************************************************************/
335#define CONFIG_DOS_PARTITION
336#define CONFIG_MAC_PARTITION
337#define CONFIG_ISO_PARTITION /* Experimental */
338
339/************************************************************
340 * Keyboard support
341 ************************************************************/
342#define CONFIG_ISA_KEYBOARD
343
344/************************************************************
345 * Video support
346 ************************************************************/
347#define CONFIG_VIDEO /*To enable video controller support */
348#define CONFIG_VIDEO_CT69000
349#define CONFIG_CFB_CONSOLE
350#define CONFIG_VIDEO_LOGO
351#define CONFIG_CONSOLE_EXTRA_INFO
352#define CONFIG_VGA_AS_SINGLE_DEVICE
353#define CONFIG_VIDEO_SW_CURSOR
354#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
355
356/************************************************************
357 * USB support
358 ************************************************************/
359#define CONFIG_USB_UHCI
360#define CONFIG_USB_KEYBOARD
361#define CONFIG_USB_STORAGE
362
363/* Enable needed helper functions */
364#define CFG_DEVICE_DEREGISTER /* needs device_deregister */
365
366/************************************************************
367 * Debug support
368 ************************************************************/
Jon Loeligeracf02692007-07-08 14:49:44 -0500369#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000370#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
371#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
372#endif
373
374/************************************************************
wdenka2663ea2003-12-07 18:32:37 +0000375 * support BZIP2 compression
376 ************************************************************/
377#define CONFIG_BZIP2 1
378
379/************************************************************
wdenkc6097192002-11-03 00:24:07 +0000380 * Ident
381 ************************************************************/
382#define VERSION_TAG "released"
wdenkf3e0de62003-06-04 15:05:30 +0000383#define CONFIG_ISO_STRING "MEV-10066-001"
384#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
wdenkc6097192002-11-03 00:24:07 +0000385
386
387#endif /* __CONFIG_H */