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wdenkc6097192002-11-03 00:24:07 +00001/*
stroesea20b27a2004-12-16 18:05:42 +00002 * (C) Copyright 2001-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
wdenkc6097192002-11-03 00:24:07 +000038#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
wdenkc837dcb2004-01-20 23:12:12 +000039#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020040#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
wdenkc6097192002-11-03 00:24:07 +000041
wdenkc837dcb2004-01-20 23:12:12 +000042#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkc6097192002-11-03 00:24:07 +000043
stroesea20b27a2004-12-16 18:05:42 +000044#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000045
46#define CONFIG_BAUDRATE 9600
47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48
wdenkc6097192002-11-03 00:24:07 +000049#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000050#undef CONFIG_BOOTCOMMAND
51
52#define CONFIG_PREBOOT /* enable preboot variable */
wdenkc6097192002-11-03 00:24:07 +000053
54#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
55#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
56
57#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000058#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000059#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020060#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
61
62#define CONFIG_NET_MULTI 1
63#undef CONFIG_HAS_ETH1
wdenkc6097192002-11-03 00:24:07 +000064
65#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
66
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050067/*
68 * BOOTP options
69 */
70#define CONFIG_BOOTP_SUBNETMASK
71#define CONFIG_BOOTP_GATEWAY
72#define CONFIG_BOOTP_HOSTNAME
73#define CONFIG_BOOTP_BOOTPATH
74#define CONFIG_BOOTP_DNS
75#define CONFIG_BOOTP_DNS2
76#define CONFIG_BOOTP_SEND_HOSTNAME
stroese9919f132003-05-23 11:38:22 +000077
wdenkc6097192002-11-03 00:24:07 +000078
Jon Loeliger49cf7e82007-07-05 19:52:35 -050079/*
80 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83
84#define CONFIG_CMD_DHCP
85#define CONFIG_CMD_PCI
86#define CONFIG_CMD_IRQ
87#define CONFIG_CMD_IDE
88#define CONFIG_CMD_FAT
89#define CONFIG_CMD_ELF
90#define CONFIG_CMD_DATE
Jon Loeliger49cf7e82007-07-05 19:52:35 -050091#define CONFIG_CMD_I2C
92#define CONFIG_CMD_MII
93#define CONFIG_CMD_PING
94#define CONFIG_CMD_BSP
95#define CONFIG_CMD_EEPROM
96
wdenkc6097192002-11-03 00:24:07 +000097#define CONFIG_MAC_PARTITION
98#define CONFIG_DOS_PARTITION
99
stroesea20b27a2004-12-16 18:05:42 +0000100#define CONFIG_SUPPORT_VFAT
101
wdenkc837dcb2004-01-20 23:12:12 +0000102#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +0000103
wdenkc837dcb2004-01-20 23:12:12 +0000104#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +0000105
106/*
107 * Miscellaneous configurable options
108 */
109#define CFG_LONGHELP /* undef to save memory */
110#define CFG_PROMPT "=> " /* Monitor Command Prompt */
111
112#undef CFG_HUSH_PARSER /* use "hush" command parser */
113#ifdef CFG_HUSH_PARSER
wdenkc837dcb2004-01-20 23:12:12 +0000114#define CFG_PROMPT_HUSH_PS2 "> "
wdenkc6097192002-11-03 00:24:07 +0000115#endif
116
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500117#if defined(CONFIG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +0000118#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000119#else
wdenkc837dcb2004-01-20 23:12:12 +0000120#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000121#endif
122#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
123#define CFG_MAXARGS 16 /* max number of command args */
124#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
125
wdenkc837dcb2004-01-20 23:12:12 +0000126#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
wdenkc6097192002-11-03 00:24:07 +0000127
wdenkc837dcb2004-01-20 23:12:12 +0000128#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +0000129
stroesea20b27a2004-12-16 18:05:42 +0000130#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
131
wdenkc6097192002-11-03 00:24:07 +0000132#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
133#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
134
wdenkc837dcb2004-01-20 23:12:12 +0000135#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
136#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
137#define CFG_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000138
139/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000140#define CFG_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000141 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
142 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000143
144#define CFG_LOAD_ADDR 0x100000 /* default load address */
145#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
146
wdenkc837dcb2004-01-20 23:12:12 +0000147#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000148
stroesea20b27a2004-12-16 18:05:42 +0000149#define CONFIG_LOOPW 1 /* enable loopw command */
150
wdenkc6097192002-11-03 00:24:07 +0000151#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
152
wdenkc837dcb2004-01-20 23:12:12 +0000153#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese9e7d5eb2003-04-04 16:48:07 +0000154
wdenkc837dcb2004-01-20 23:12:12 +0000155#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese53cf9432003-06-05 15:39:44 +0000156
wdenkc6097192002-11-03 00:24:07 +0000157/*-----------------------------------------------------------------------
158 * PCI stuff
159 *-----------------------------------------------------------------------
160 */
stroesea20b27a2004-12-16 18:05:42 +0000161#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
162#define PCI_HOST_FORCE 1 /* configure as pci host */
163#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000164
stroesea20b27a2004-12-16 18:05:42 +0000165#define CONFIG_PCI /* include pci support */
166#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
167#define CONFIG_PCI_PNP /* do pci plug-and-play */
168 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000169
stroesea20b27a2004-12-16 18:05:42 +0000170#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000171
stroesea20b27a2004-12-16 18:05:42 +0000172#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
stroesead10dd92003-02-14 11:21:23 +0000173
stroesea20b27a2004-12-16 18:05:42 +0000174#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
175
176#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
177#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
178#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
179#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
Stefan Roese2076d0a2006-01-18 20:03:15 +0100180#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
181#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
stroesea20b27a2004-12-16 18:05:42 +0000182#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
183#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
184#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
185#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000186
187/*-----------------------------------------------------------------------
188 * IDE/ATA stuff
189 *-----------------------------------------------------------------------
190 */
wdenkc837dcb2004-01-20 23:12:12 +0000191#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
192#undef CONFIG_IDE_LED /* no led for ide supported */
wdenkc6097192002-11-03 00:24:07 +0000193#define CONFIG_IDE_RESET 1 /* reset for ide supported */
194
wdenkc837dcb2004-01-20 23:12:12 +0000195#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
196#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000197
wdenkc837dcb2004-01-20 23:12:12 +0000198#define CFG_ATA_BASE_ADDR 0xF0100000
199#define CFG_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000200
201#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
wdenkc837dcb2004-01-20 23:12:12 +0000202#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
wdenkc6097192002-11-03 00:24:07 +0000203#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
204
205/*-----------------------------------------------------------------------
206 * Start addresses for the final memory configuration
207 * (Set up by the startup code)
208 * Please note that CFG_SDRAM_BASE _must_ start at 0
209 */
210#define CFG_SDRAM_BASE 0x00000000
211#define CFG_FLASH_BASE 0xFFFC0000
212#define CFG_MONITOR_BASE CFG_FLASH_BASE
213#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
214#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
215
216/*
217 * For booting Linux, the board info and command line data
218 * have to be in the first 8 MB of memory, since this is
219 * the maximum mapped by the Linux kernel during initialization.
220 */
221#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
222/*-----------------------------------------------------------------------
223 * FLASH organization
224 */
225#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
226#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
227
228#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
229#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
230
wdenkc837dcb2004-01-20 23:12:12 +0000231#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
232#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
233#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000234/*
235 * The following defines are added for buggy IOP480 byte interface.
236 * All other boards should use the standard values (CPCI405 etc.)
237 */
wdenkc837dcb2004-01-20 23:12:12 +0000238#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
239#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
240#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000241
wdenkc837dcb2004-01-20 23:12:12 +0000242#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000243
wdenkc6097192002-11-03 00:24:07 +0000244#if 0 /* Use NVRAM for environment variables */
245/*-----------------------------------------------------------------------
246 * NVRAM organization
247 */
248#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
249#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
250#define CFG_ENV_ADDR \
251 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */
252
253#else /* Use EEPROM for environment variables */
254
wdenkc837dcb2004-01-20 23:12:12 +0000255#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
256#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
257#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
wdenk8bde7f72003-06-27 21:31:46 +0000258 /* total size of a CAT24WC16 is 2048 bytes */
wdenkc6097192002-11-03 00:24:07 +0000259#endif
260
261#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
262#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
stroesea20b27a2004-12-16 18:05:42 +0000263#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
wdenkc6097192002-11-03 00:24:07 +0000264
265/*-----------------------------------------------------------------------
266 * I2C EEPROM (CAT24WC16) for environment
267 */
268#define CONFIG_HARD_I2C /* I2c with hardware support */
269#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
270#define CFG_I2C_SLAVE 0x7F
271
272#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
wdenkc837dcb2004-01-20 23:12:12 +0000273#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
274/* mask of address bits that overflow into the "EEPROM chip address" */
wdenkc6097192002-11-03 00:24:07 +0000275#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
276#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
277 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000278 /* last 4 bits of the address */
wdenkc6097192002-11-03 00:24:07 +0000279#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
280#define CFG_EEPROM_PAGE_WRITE_ENABLE
281
wdenkc6097192002-11-03 00:24:07 +0000282/*
283 * Init Memory Controller:
284 *
285 * BR0/1 and OR0/1 (FLASH)
286 */
287
288#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
289#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
290
291/*-----------------------------------------------------------------------
292 * External Bus Controller (EBC) Setup
293 */
294
wdenkc837dcb2004-01-20 23:12:12 +0000295/* Memory Bank 0 (Flash Bank 0) initialization */
296#define CFG_EBC_PB0AP 0x92015480
297#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000298
wdenkc837dcb2004-01-20 23:12:12 +0000299/* Memory Bank 1 (Flash Bank 1) initialization */
300#define CFG_EBC_PB1AP 0x92015480
301#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000302
wdenkc837dcb2004-01-20 23:12:12 +0000303/* Memory Bank 2 (CAN0, 1) initialization */
304#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
305#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
306#define CFG_LED_ADDR 0xF0000380
wdenkc6097192002-11-03 00:24:07 +0000307
wdenkc837dcb2004-01-20 23:12:12 +0000308/* Memory Bank 3 (CompactFlash IDE) initialization */
309#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
310#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000311
wdenkc837dcb2004-01-20 23:12:12 +0000312/* Memory Bank 4 (NVRAM/RTC) initialization */
313/*#define CFG_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
314#define CFG_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
315#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000316
wdenkc837dcb2004-01-20 23:12:12 +0000317/* Memory Bank 5 (optional Quart) initialization */
318#define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
319#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000320
wdenkc837dcb2004-01-20 23:12:12 +0000321/* Memory Bank 6 (FPGA internal) initialization */
322#define CFG_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
323#define CFG_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
324#define CFG_FPGA_BASE_ADDR 0xF0400000
wdenkc6097192002-11-03 00:24:07 +0000325
326/*-----------------------------------------------------------------------
327 * FPGA stuff
328 */
329/* FPGA internal regs */
wdenkc837dcb2004-01-20 23:12:12 +0000330#define CFG_FPGA_MODE 0x00
331#define CFG_FPGA_STATUS 0x02
332#define CFG_FPGA_TS 0x04
333#define CFG_FPGA_TS_LOW 0x06
334#define CFG_FPGA_TS_CAP0 0x10
335#define CFG_FPGA_TS_CAP0_LOW 0x12
336#define CFG_FPGA_TS_CAP1 0x14
337#define CFG_FPGA_TS_CAP1_LOW 0x16
338#define CFG_FPGA_TS_CAP2 0x18
339#define CFG_FPGA_TS_CAP2_LOW 0x1a
340#define CFG_FPGA_TS_CAP3 0x1c
341#define CFG_FPGA_TS_CAP3_LOW 0x1e
wdenkc6097192002-11-03 00:24:07 +0000342
343/* FPGA Mode Reg */
wdenkc837dcb2004-01-20 23:12:12 +0000344#define CFG_FPGA_MODE_CF_RESET 0x0001
stroese6f4474e2003-03-20 15:31:19 +0000345#define CFG_FPGA_MODE_DUART_RESET 0x0002
346#define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
wdenkc6097192002-11-03 00:24:07 +0000347#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
348#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
wdenkc837dcb2004-01-20 23:12:12 +0000349#define CFG_FPGA_MODE_TS_CLEAR 0x2000
wdenkc6097192002-11-03 00:24:07 +0000350
351/* FPGA Status Reg */
wdenkc837dcb2004-01-20 23:12:12 +0000352#define CFG_FPGA_STATUS_DIP0 0x0001
353#define CFG_FPGA_STATUS_DIP1 0x0002
354#define CFG_FPGA_STATUS_DIP2 0x0004
355#define CFG_FPGA_STATUS_FLASH 0x0008
356#define CFG_FPGA_STATUS_TS_IRQ 0x1000
wdenkc6097192002-11-03 00:24:07 +0000357
wdenkc837dcb2004-01-20 23:12:12 +0000358#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
359#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
wdenkc6097192002-11-03 00:24:07 +0000360
361/* FPGA program pin configuration */
wdenkc837dcb2004-01-20 23:12:12 +0000362#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
363#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
364#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
365#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
366#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
wdenkc6097192002-11-03 00:24:07 +0000367
368/*-----------------------------------------------------------------------
369 * Definitions for initial stack pointer and data area (in data cache)
370 */
wdenkc837dcb2004-01-20 23:12:12 +0000371#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
wdenkc6097192002-11-03 00:24:07 +0000372
wdenkc837dcb2004-01-20 23:12:12 +0000373#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
374#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
wdenkc6097192002-11-03 00:24:07 +0000375#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
376#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000377#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000378
379
380/*
381 * Internal Definitions
382 *
383 * Boot Flags
384 */
385#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
386#define BOOTFLAG_WARM 0x02 /* Software reboot */
387
388#endif /* __CONFIG_H */