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wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2003
3 * Texas Instruments.
4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
6 *
7 * (C) Copyright 2004
8 * ARM Ltd.
9 * Philippe Robin, <philippe.robin@arm.com>
10 * Configuration for Versatile PB.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +020038#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
wdenk3d3befa2004-03-14 15:06:13 +000039#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +020040#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
wdenk3d3befa2004-03-14 15:06:13 +000041
Jean-Christophe PLAGNIOL-VILLARDd6e8ed82009-05-02 11:53:49 +020042#ifndef CONFIG_ARCH_VERSATILE_AB /* AB */
43#define CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
44#endif
45
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +020046#define CONFIG_SYS_MEMTEST_START 0x100000
47#define CONFIG_SYS_MEMTEST_END 0x10000000
48#define CONFIG_SYS_HZ (1000000 / 256)
49#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */
wdenk3d3befa2004-03-14 15:06:13 +000050
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_TIMER_INTERVAL 10000
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +020052#define CONFIG_SYS_TIMER_RELOAD (CONFIG_SYS_TIMER_INTERVAL >> 4)
53#define CONFIG_SYS_TIMER_CTRL 0x84 /* Enable, Clock / 16 */
wdenk3d3befa2004-03-14 15:06:13 +000054
55/*
56 * control registers
57 */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +020058#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
wdenk3d3befa2004-03-14 15:06:13 +000059
60/*
61 * System controller bit assignment
62 */
63#define VERSATILE_REFCLK 0
64#define VERSATILE_TIMCLK 1
65
66#define VERSATILE_TIMER1_EnSel 15
67#define VERSATILE_TIMER2_EnSel 17
68#define VERSATILE_TIMER3_EnSel 19
69#define VERSATILE_TIMER4_EnSel 21
70
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +020071#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenk3d3befa2004-03-14 15:06:13 +000072#define CONFIG_SETUP_MEMORY_TAGS 1
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +020073#define CONFIG_MISC_INIT_R 1
wdenk3d3befa2004-03-14 15:06:13 +000074/*
75 * Size of malloc() pool
76 */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +020077#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
78/* size in bytes reserved for initial data */
79#define CONFIG_SYS_GBL_DATA_SIZE 128
wdenk3d3befa2004-03-14 15:06:13 +000080
81/*
82 * Hardware drivers
83 */
84
Ben Warren7194ab82009-10-04 22:37:03 -070085#define CONFIG_NET_MULTI
86#define CONFIG_SMC91111
wdenk3d3befa2004-03-14 15:06:13 +000087#define CONFIG_SMC_USE_32_BIT
Wolfgang Denk53677ef2008-05-20 16:00:29 +020088#define CONFIG_SMC91111_BASE 0x10010000
wdenk3d3befa2004-03-14 15:06:13 +000089#undef CONFIG_SMC91111_EXT_PHY
90
91/*
92 * NS16550 Configuration
93 */
Andreas Engel48d01922008-09-08 14:30:53 +020094#define CONFIG_PL011_SERIAL
wdenk6705d812004-08-02 23:22:59 +000095#define CONFIG_PL011_CLOCK 24000000
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +020096#define CONFIG_PL01x_PORTS \
97 {(void *)CONFIG_SYS_SERIAL0, \
98 (void *)CONFIG_SYS_SERIAL1 }
wdenk3d3befa2004-03-14 15:06:13 +000099#define CONFIG_CONS_INDEX 0
wdenk6705d812004-08-02 23:22:59 +0000100
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200101#define CONFIG_BAUDRATE 38400
102#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_SERIAL0 0x101F1000
104#define CONFIG_SYS_SERIAL1 0x101F2000
wdenk3d3befa2004-03-14 15:06:13 +0000105
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500106/*
107 * Command line configuration.
108 */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200109#define CONFIG_CMD_BDI
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500110#define CONFIG_CMD_DHCP
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200111#define CONFIG_CMD_FLASH
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500112#define CONFIG_CMD_IMI
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200113#define CONFIG_CMD_MEMORY
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500114#define CONFIG_CMD_NET
115#define CONFIG_CMD_PING
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500116#define CONFIG_CMD_SAVEENV
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500117
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500118/*
119 * BOOTP options
120 */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200121#define CONFIG_BOOTP_BOOTPATH
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500122#define CONFIG_BOOTP_GATEWAY
123#define CONFIG_BOOTP_HOSTNAME
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200124#define CONFIG_BOOTP_SUBNETMASK
wdenk3d3befa2004-03-14 15:06:13 +0000125
wdenk3d3befa2004-03-14 15:06:13 +0000126#define CONFIG_BOOTDELAY 2
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200127#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\
128 "netdev=25,0,0xf1010000,0xf1010010,eth0"
wdenk3d3befa2004-03-14 15:06:13 +0000129
130/*
131 * Static configuration when assigning fixed address
132 */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200133#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */
wdenk3d3befa2004-03-14 15:06:13 +0000134
135/*
136 * Miscellaneous configurable options
137 */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200138#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200139#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jean-Christophe PLAGNIOL-VILLARDd6e8ed82009-05-02 11:53:49 +0200140/* Monitor Command Prompt */
141#ifdef CONFIG_ARCH_VERSATILE_AB
142# define CONFIG_SYS_PROMPT "VersatileAB # "
143#else
144# define CONFIG_SYS_PROMPT "VersatilePB # "
145#endif
wdenk3d3befa2004-03-14 15:06:13 +0000146/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200147#define CONFIG_SYS_PBSIZE \
148 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
149#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk3d3befa2004-03-14 15:06:13 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */
wdenk3d3befa2004-03-14 15:06:13 +0000153
154/*-----------------------------------------------------------------------
155 * Stack sizes
156 *
157 * The stack sizes are set up in start.S using the settings below
158 */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200159#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
wdenk3d3befa2004-03-14 15:06:13 +0000160#ifdef CONFIG_USE_IRQ
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200161#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
162#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
wdenk3d3befa2004-03-14 15:06:13 +0000163#endif
164
165/*-----------------------------------------------------------------------
166 * Physical Memory Map
167 */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200168#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
169#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
170#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
Jean-Christophe PLAGNIOL-VILLARD98692272009-05-02 11:53:50 +0200171#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
wdenk3d3befa2004-03-14 15:06:13 +0000172
173/*-----------------------------------------------------------------------
174 * FLASH and environment organization
175 */
Jean-Christophe PLAGNIOL-VILLARD98692272009-05-02 11:53:50 +0200176/*
177 * Use the CFI flash driver for ease of use
178 */
179#define CONFIG_SYS_FLASH_CFI
180#define CONFIG_FLASH_CFI_DRIVER
181#define CONFIG_ENV_IS_IN_FLASH 1
182/*
183 * System control register
184 */
Jean-Christophe PLAGNIOL-VILLARD2600b852009-06-20 11:02:17 +0200185#define VERSATILE_SYS_BASE 0x10000000
186#define VERSATILE_SYS_FLASH_OFFSET 0x4C
187#define VERSATILE_FLASHCTRL \
188 (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
189/* Enable writing to flash */
190#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0)
wdenkd407bf52004-10-11 22:51:13 +0000191
wdenk3d3befa2004-03-14 15:06:13 +0000192/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD98692272009-05-02 11:53:50 +0200193#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
194#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
wdenk3d3befa2004-03-14 15:06:13 +0000195
Jean-Christophe PLAGNIOL-VILLARD98692272009-05-02 11:53:50 +0200196/*
197 * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block
198 * i.e.
199 * the bottom "sector" (bottom boot), or top "sector"
200 * (top boot), is a seperate erase region divided into
201 * 4 (equal) smaller sectors. This, notionally, allows
202 * quicker erase/rewrire of the most frequently changed
203 * area......
204 * CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4
205 */
wdenk3d3befa2004-03-14 15:06:13 +0000206
Jean-Christophe PLAGNIOL-VILLARD98692272009-05-02 11:53:50 +0200207#ifdef CONFIG_ARCH_VERSATILE_AB
208#define FLASH_SECTOR_SIZE 0x00020000 /* 128 KB sectors */
209#define CONFIG_ENV_SECT_SIZE (2 * FLASH_SECTOR_SIZE)
210#define CONFIG_SYS_MAX_FLASH_SECT (520)
211#endif
wdenkd407bf52004-10-11 22:51:13 +0000212
Jean-Christophe PLAGNIOL-VILLARD98692272009-05-02 11:53:50 +0200213#ifdef CONFIG_ARCH_VERSATILE_PB /* Versatile PB is default */
214#define FLASH_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
215#define CONFIG_ENV_SECT_SIZE FLASH_SECTOR_SIZE
216#define CONFIG_SYS_MAX_FLASH_SECT (260)
217#endif
218
219#define CONFIG_SYS_FLASH_BASE 0x34000000
220#define CONFIG_SYS_MAX_FLASH_BANKS 1
221
222#define CONFIG_SYS_MONITOR_LEN (4 * CONFIG_ENV_SECT_SIZE)
223
224/* The ARM Boot Monitor is shipped in the lowest sector of flash */
225
226#define FLASH_TOP (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE)
227#define CONFIG_ENV_SIZE 8192
228#define CONFIG_ENV_ADDR (FLASH_TOP - CONFIG_ENV_SECT_SIZE)
229#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
230#define CONFIG_SYS_MONITOR_BASE (CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN)
231
232#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
233#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
234
235#endif /* __CONFIG_H */