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wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * (C) Copyright 2002
3 * Lineo, Inc <www.lineo.com>
4 * Bernhard Kuhn <bkuhn@lineo.com>
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Marius Groeger <mgroeger@sysgo.de>
9 *
10 * (C) Copyright 2002
11 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
12 * Alex Zuepke <azu@sysgo.de>
13 *
14 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 *
30 */
31
32#include <common.h>
Jens Scharsig0cf0b932010-02-03 22:46:58 +010033
34#ifndef CONFIG_AT91_LEGACY
wdenk85ec0bc2003-03-31 16:34:49 +000035#include <asm/io.h>
wdenkb783eda2003-06-25 22:26:29 +000036#include <asm/arch/hardware.h>
Jens Scharsig0cf0b932010-02-03 22:46:58 +010037#define CONFIG_AT91_LEGACY
38#include <asm/arch-at91rm9200/AT91RM9200.h>
39#warning Please update to use C structur SoC access !
40#else
41#include <asm/arch/AT91RM9200.h>
42#endif
wdenkdc7c9a12003-03-26 06:55:25 +000043
Wolfgang Denkd87080b2006-03-31 18:32:53 +020044DECLARE_GLOBAL_DATA_PTR;
45
wdenk2cbe5712004-10-10 17:05:18 +000046#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
47#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
wdenk4734cb72004-09-21 23:33:32 +000048#endif
49
wdenkdc7c9a12003-03-26 06:55:25 +000050/* ggi thunder */
wdenk4734cb72004-09-21 23:33:32 +000051#ifdef CONFIG_DBGU
wdenkdc7c9a12003-03-26 06:55:25 +000052AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
wdenk4734cb72004-09-21 23:33:32 +000053#endif
wdenk2cbe5712004-10-10 17:05:18 +000054#ifdef CONFIG_USART0
55AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US0;
56#endif
wdenk4734cb72004-09-21 23:33:32 +000057#ifdef CONFIG_USART1
58AT91PS_USART us = (AT91PS_USART) AT91C_BASE_US1;
59#endif
wdenkdc7c9a12003-03-26 06:55:25 +000060
wdenkd9df1f42004-03-15 09:00:01 +000061void serial_setbrg (void)
62{
wdenkd9df1f42004-03-15 09:00:01 +000063 int baudrate;
wdenkdc7c9a12003-03-26 06:55:25 +000064
wdenk2cbe5712004-10-10 17:05:18 +000065 if ((baudrate = gd->baudrate) <= 0)
wdenkd9df1f42004-03-15 09:00:01 +000066 baudrate = CONFIG_BAUDRATE;
wdenkec0ca732005-04-20 12:36:05 +000067 /* MASTER_CLOCK/(16 * baudrate) */
Wolfgang Denk8d4ba3d2005-08-12 22:35:59 +020068 us->US_BRGR = (AT91C_MASTER_CLOCK >> 4) / (unsigned)baudrate;
wdenkd9df1f42004-03-15 09:00:01 +000069}
wdenkdc7c9a12003-03-26 06:55:25 +000070
wdenkd9df1f42004-03-15 09:00:01 +000071int serial_init (void)
72{
73 /* make any port initializations specific to this port */
wdenk4734cb72004-09-21 23:33:32 +000074#ifdef CONFIG_DBGU
wdenkd9df1f42004-03-15 09:00:01 +000075 *AT91C_PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; /* PA 31 & 30 */
76 *AT91C_PMC_PCER = 1 << AT91C_ID_SYS; /* enable clock */
wdenk4734cb72004-09-21 23:33:32 +000077#endif
wdenk2cbe5712004-10-10 17:05:18 +000078#ifdef CONFIG_USART0
79 *AT91C_PIOA_PDR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0;
80 *AT91C_PMC_PCER |= 1 << AT91C_ID_USART0; /* enable clock */
81#endif
wdenk4734cb72004-09-21 23:33:32 +000082#ifdef CONFIG_USART1
83 *AT91C_PIOB_PDR = AT91C_PB21_TXD1 | AT91C_PB20_RXD1;
84 *AT91C_PMC_PCER |= 1 << AT91C_ID_USART1; /* enable clock */
85#endif
wdenkd9df1f42004-03-15 09:00:01 +000086 serial_setbrg ();
wdenkdc7c9a12003-03-26 06:55:25 +000087
wdenkd9df1f42004-03-15 09:00:01 +000088 us->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX;
89 us->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
90 us->US_MR =
91 (AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS |
92 AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT);
93 us->US_IMR = ~0ul;
94 return (0);
95}
wdenkdc7c9a12003-03-26 06:55:25 +000096
Jean-Christophe PLAGNIOL-VILLARD35240492009-03-27 23:26:43 +010097void serial_exit (void)
98{
99 us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
100}
101
wdenkd9df1f42004-03-15 09:00:01 +0000102void serial_putc (const char c)
103{
104 if (c == '\n')
105 serial_putc ('\r');
106 while ((us->US_CSR & AT91C_US_TXRDY) == 0);
107 us->US_THR = c;
108}
wdenkdc7c9a12003-03-26 06:55:25 +0000109
wdenkd9df1f42004-03-15 09:00:01 +0000110void serial_puts (const char *s)
111{
112 while (*s) {
113 serial_putc (*s++);
114 }
115}
wdenkdc7c9a12003-03-26 06:55:25 +0000116
wdenkd9df1f42004-03-15 09:00:01 +0000117int serial_getc (void)
118{
119 while ((us->US_CSR & AT91C_US_RXRDY) == 0);
120 return us->US_RHR;
121}
wdenkdc7c9a12003-03-26 06:55:25 +0000122
wdenkd9df1f42004-03-15 09:00:01 +0000123int serial_tstc (void)
124{
125 return ((us->US_CSR & AT91C_US_RXRDY) == AT91C_US_RXRDY);
126}