| Neil Armstrong | afef205 | 2020-12-29 14:58:58 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2013 NVIDIA Corporation |
| 4 | * Copyright (C) 2018 Cadence Design Systems Inc. |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <div64.h> |
| 9 | |
| 10 | #include <phy-mipi-dphy.h> |
| 11 | |
| 12 | #define PSEC_PER_SEC 1000000000000LL |
| 13 | |
| 14 | /* |
| 15 | * Minimum D-PHY timings based on MIPI D-PHY specification. Derived |
| 16 | * from the valid ranges specified in Section 6.9, Table 14, Page 41 |
| 17 | * of the D-PHY specification (v2.1). |
| 18 | */ |
| 19 | int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, |
| 20 | unsigned int bpp, |
| 21 | unsigned int lanes, |
| 22 | struct phy_configure_opts_mipi_dphy *cfg) |
| 23 | { |
| 24 | unsigned long long hs_clk_rate; |
| 25 | unsigned long long ui; |
| 26 | |
| 27 | if (!cfg) |
| 28 | return -EINVAL; |
| 29 | |
| 30 | hs_clk_rate = pixel_clock * bpp; |
| 31 | do_div(hs_clk_rate, lanes); |
| 32 | |
| 33 | ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); |
| 34 | do_div(ui, hs_clk_rate); |
| 35 | |
| 36 | cfg->clk_miss = 0; |
| 37 | cfg->clk_post = 60000 + 52 * ui; |
| 38 | cfg->clk_pre = 8000; |
| 39 | cfg->clk_prepare = 38000; |
| 40 | cfg->clk_settle = 95000; |
| 41 | cfg->clk_term_en = 0; |
| 42 | cfg->clk_trail = 60000; |
| 43 | cfg->clk_zero = 262000; |
| 44 | cfg->d_term_en = 0; |
| 45 | cfg->eot = 0; |
| 46 | cfg->hs_exit = 100000; |
| 47 | cfg->hs_prepare = 40000 + 4 * ui; |
| 48 | cfg->hs_zero = 105000 + 6 * ui; |
| 49 | cfg->hs_settle = 85000 + 6 * ui; |
| 50 | cfg->hs_skip = 40000; |
| 51 | |
| 52 | /* |
| 53 | * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) |
| 54 | * contains this formula as: |
| 55 | * |
| 56 | * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) |
| 57 | * |
| 58 | * where n = 1 for forward-direction HS mode and n = 4 for reverse- |
| 59 | * direction HS mode. There's only one setting and this function does |
| 60 | * not parameterize on anything other that ui, so this code will |
| 61 | * assumes that reverse-direction HS mode is supported and uses n = 4. |
| 62 | */ |
| 63 | cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); |
| 64 | |
| 65 | cfg->init = 100; |
| 66 | cfg->lpx = 60000; |
| 67 | cfg->ta_get = 5 * cfg->lpx; |
| 68 | cfg->ta_go = 4 * cfg->lpx; |
| 69 | cfg->ta_sure = 2 * cfg->lpx; |
| 70 | cfg->wakeup = 1000; |
| 71 | |
| 72 | cfg->hs_clk_rate = hs_clk_rate; |
| 73 | cfg->lanes = lanes; |
| 74 | |
| 75 | return 0; |
| 76 | } |
| 77 | |
| 78 | /* |
| 79 | * Validate D-PHY configuration according to MIPI D-PHY specification |
| 80 | * (v1.2, Section Section 6.9 "Global Operation Timing Parameters"). |
| 81 | */ |
| 82 | int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg) |
| 83 | { |
| 84 | unsigned long long ui; |
| 85 | |
| 86 | if (!cfg) |
| 87 | return -EINVAL; |
| 88 | |
| 89 | ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate); |
| 90 | do_div(ui, cfg->hs_clk_rate); |
| 91 | |
| 92 | if (cfg->clk_miss > 60000) |
| 93 | return -EINVAL; |
| 94 | |
| 95 | if (cfg->clk_post < (60000 + 52 * ui)) |
| 96 | return -EINVAL; |
| 97 | |
| 98 | if (cfg->clk_pre < 8000) |
| 99 | return -EINVAL; |
| 100 | |
| 101 | if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000) |
| 102 | return -EINVAL; |
| 103 | |
| 104 | if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000) |
| 105 | return -EINVAL; |
| 106 | |
| 107 | if (cfg->clk_term_en > 38000) |
| 108 | return -EINVAL; |
| 109 | |
| 110 | if (cfg->clk_trail < 60000) |
| 111 | return -EINVAL; |
| 112 | |
| 113 | if ((cfg->clk_prepare + cfg->clk_zero) < 300000) |
| 114 | return -EINVAL; |
| 115 | |
| 116 | if (cfg->d_term_en > (35000 + 4 * ui)) |
| 117 | return -EINVAL; |
| 118 | |
| 119 | if (cfg->eot > (105000 + 12 * ui)) |
| 120 | return -EINVAL; |
| 121 | |
| 122 | if (cfg->hs_exit < 100000) |
| 123 | return -EINVAL; |
| 124 | |
| 125 | if (cfg->hs_prepare < (40000 + 4 * ui) || |
| 126 | cfg->hs_prepare > (85000 + 6 * ui)) |
| 127 | return -EINVAL; |
| 128 | |
| 129 | if ((cfg->hs_prepare + cfg->hs_zero) < (145000 + 10 * ui)) |
| 130 | return -EINVAL; |
| 131 | |
| 132 | if ((cfg->hs_settle < (85000 + 6 * ui)) || |
| 133 | (cfg->hs_settle > (145000 + 10 * ui))) |
| 134 | return -EINVAL; |
| 135 | |
| 136 | if (cfg->hs_skip < 40000 || cfg->hs_skip > (55000 + 4 * ui)) |
| 137 | return -EINVAL; |
| 138 | |
| 139 | if (cfg->hs_trail < max(8 * ui, 60000 + 4 * ui)) |
| 140 | return -EINVAL; |
| 141 | |
| 142 | if (cfg->init < 100) |
| 143 | return -EINVAL; |
| 144 | |
| 145 | if (cfg->lpx < 50000) |
| 146 | return -EINVAL; |
| 147 | |
| 148 | if (cfg->ta_get != (5 * cfg->lpx)) |
| 149 | return -EINVAL; |
| 150 | |
| 151 | if (cfg->ta_go != (4 * cfg->lpx)) |
| 152 | return -EINVAL; |
| 153 | |
| 154 | if (cfg->ta_sure < cfg->lpx || cfg->ta_sure > (2 * cfg->lpx)) |
| 155 | return -EINVAL; |
| 156 | |
| 157 | if (cfg->wakeup < 1000) |
| 158 | return -EINVAL; |
| 159 | |
| 160 | return 0; |
| 161 | } |