| Tom Warren | 2fc65e2 | 2013-01-28 13:32:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | |
| 17 | #ifndef _TEGRA114_FLOW_H_ |
| 18 | #define _TEGRA114_FLOW_H_ |
| 19 | |
| 20 | struct flow_ctlr { |
| 21 | u32 halt_cpu_events; |
| 22 | u32 halt_cop_events; |
| 23 | u32 cpu_csr; |
| 24 | u32 cop_csr; |
| 25 | u32 xrq_events; |
| 26 | u32 halt_cpu1_events; |
| 27 | u32 cpu1_csr; |
| 28 | u32 halt_cpu2_events; |
| 29 | u32 cpu2_csr; |
| 30 | u32 halt_cpu3_events; |
| 31 | u32 cpu3_csr; |
| 32 | u32 cluster_control; |
| 33 | }; |
| 34 | |
| 35 | #endif /* _TEGRA114_FLOW_H_ */ |