blob: 83d97d7829f562cec055d76abcee2952bbb17149 [file] [log] [blame]
Akshay Bhatf9162b12016-01-29 15:16:40 -05001/*
2 * Copyright 2015 Timesys Corporation
3 * Copyright 2015 General Electric Company
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <asm/arch/clock.h>
10#include <asm/arch/imx-regs.h>
11#include <asm/arch/iomux.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/errno.h>
14#include <asm/gpio.h>
15#include <asm/imx-common/mxc_i2c.h>
16#include <asm/imx-common/iomux-v3.h>
17#include <asm/imx-common/boot_mode.h>
18#include <asm/imx-common/video.h>
19#include <mmc.h>
20#include <fsl_esdhc.h>
21#include <miiphy.h>
22#include <netdev.h>
23#include <asm/arch/mxc_hdmi.h>
24#include <asm/arch/crm_regs.h>
25#include <asm/io.h>
26#include <asm/arch/sys_proto.h>
27#include <i2c.h>
28DECLARE_GLOBAL_DATA_PTR;
29
Justin Waters7d0b8cf2016-04-13 17:03:18 -040030#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
31 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
32 PAD_CTL_HYS)
33
Akshay Bhatf9162b12016-01-29 15:16:40 -050034#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
35 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
36 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
37
38#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
39 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
40 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41
42#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
43 PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
44
45#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
46 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
47
48#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
49 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
50
51#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
52 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
53
54#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
55 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
56 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
57
58#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
59
60int dram_init(void)
61{
62 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
63
64 return 0;
65}
66
67static iomux_v3_cfg_t const uart3_pads[] = {
68 MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
69 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
70 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
71 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
72};
73
74static iomux_v3_cfg_t const uart4_pads[] = {
75 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
76 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
77};
78
79static iomux_v3_cfg_t const enet_pads[] = {
80 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
81 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
82 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
83 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
89 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
90 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
91 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
92 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
93 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
94 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
95 /* AR8033 PHY Reset */
96 MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
97};
98
99static void setup_iomux_enet(void)
100{
101 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
102
103 /* Reset AR8033 PHY */
104 gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
105 udelay(500);
106 gpio_set_value(IMX_GPIO_NR(1, 28), 1);
107}
108
109static iomux_v3_cfg_t const usdhc2_pads[] = {
110 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
111 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
113 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
117};
118
119static iomux_v3_cfg_t const usdhc3_pads[] = {
120 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131};
132
133static iomux_v3_cfg_t const usdhc4_pads[] = {
134 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
137 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
138 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
139 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
140 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
141 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
142 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
145 MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
146};
147
148static iomux_v3_cfg_t const ecspi1_pads[] = {
149 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
150 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
151 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
152 MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
153};
154
155static struct i2c_pads_info i2c_pad_info1 = {
156 .scl = {
157 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
158 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
159 .gp = IMX_GPIO_NR(5, 27)
160 },
161 .sda = {
162 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
163 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
164 .gp = IMX_GPIO_NR(5, 26)
165 }
166};
167
168static struct i2c_pads_info i2c_pad_info2 = {
169 .scl = {
170 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
171 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
172 .gp = IMX_GPIO_NR(4, 12)
173 },
174 .sda = {
175 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
176 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
177 .gp = IMX_GPIO_NR(4, 13)
178 }
179};
180
181static struct i2c_pads_info i2c_pad_info3 = {
182 .scl = {
183 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
184 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
185 .gp = IMX_GPIO_NR(1, 3)
186 },
187 .sda = {
188 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
189 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
190 .gp = IMX_GPIO_NR(1, 6)
191 }
192};
193
194#ifdef CONFIG_MXC_SPI
195int board_spi_cs_gpio(unsigned bus, unsigned cs)
196{
197 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
198}
199
200static void setup_spi(void)
201{
202 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
203}
204#endif
205
206static iomux_v3_cfg_t const pcie_pads[] = {
207 MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
208 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
209};
210
211static void setup_pcie(void)
212{
213 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
214}
215
216static void setup_iomux_uart(void)
217{
218 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
219 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
220}
221
222#ifdef CONFIG_FSL_ESDHC
223struct fsl_esdhc_cfg usdhc_cfg[3] = {
224 {USDHC2_BASE_ADDR},
225 {USDHC3_BASE_ADDR},
226 {USDHC4_BASE_ADDR},
227};
228
229#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
230#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
231
232int board_mmc_getcd(struct mmc *mmc)
233{
234 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
235 int ret = 0;
236
237 switch (cfg->esdhc_base) {
238 case USDHC2_BASE_ADDR:
239 ret = !gpio_get_value(USDHC2_CD_GPIO);
240 break;
241 case USDHC3_BASE_ADDR:
242 ret = 1; /* eMMC is always present */
243 break;
244 case USDHC4_BASE_ADDR:
245 ret = !gpio_get_value(USDHC4_CD_GPIO);
246 break;
247 }
248
249 return ret;
250}
251
252int board_mmc_init(bd_t *bis)
253{
254 int ret;
255 int i;
256
257 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
258 switch (i) {
259 case 0:
260 imx_iomux_v3_setup_multiple_pads(
261 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
262 gpio_direction_input(USDHC2_CD_GPIO);
263 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
264 break;
265 case 1:
266 imx_iomux_v3_setup_multiple_pads(
267 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
268 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
269 break;
270 case 2:
271 imx_iomux_v3_setup_multiple_pads(
272 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
273 gpio_direction_input(USDHC4_CD_GPIO);
274 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
275 break;
276 default:
277 printf("Warning: you configured more USDHC controllers\n"
278 "(%d) then supported by the board (%d)\n",
279 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
280 return -EINVAL;
281 }
282
283 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
284 if (ret)
285 return ret;
286 }
287
288 return 0;
289}
290#endif
291
292static int mx6_rgmii_rework(struct phy_device *phydev)
293{
294 /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
295 /* set device address 0x7 */
296 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
297 /* offset 0x8016: CLK_25M Clock Select */
298 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
299 /* enable register write, no post increment, address 0x7 */
300 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
301 /* set to 125 MHz from local PLL source */
302 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
303
304 /* rgmii tx clock delay enable */
305 /* set debug port address: SerDes Test and System Mode Control */
306 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
307 /* enable rgmii tx clock delay */
308 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
309
310 return 0;
311}
312
313int board_phy_config(struct phy_device *phydev)
314{
315 mx6_rgmii_rework(phydev);
316
317 if (phydev->drv->config)
318 phydev->drv->config(phydev);
319
320 return 0;
321}
322
323#if defined(CONFIG_VIDEO_IPUV3)
324static iomux_v3_cfg_t const backlight_pads[] = {
325 /* Power for LVDS Display */
326 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
327#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
328 /* Backlight enable for LVDS display */
329 MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
330#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
331};
332
333static void do_enable_hdmi(struct display_info_t const *dev)
334{
335 imx_enable_hdmi_phy();
336}
337
338int board_cfb_skip(void)
339{
340 gpio_direction_output(LVDS_POWER_GP, 1);
341
342 return 0;
343}
344
345static int detect_baseboard(struct display_info_t const *dev)
346{
347 if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
348 IS_ENABLED(CONFIG_TARGET_GE_B650V3))
349 return 1;
350
351 return 0;
352}
353
354struct display_info_t const displays[] = {{
355 .bus = -1,
356 .addr = -1,
357 .pixfmt = IPU_PIX_FMT_RGB24,
358 .detect = detect_baseboard,
359 .enable = NULL,
360 .mode = {
361 .name = "G121X1-L03",
362 .refresh = 60,
363 .xres = 1024,
364 .yres = 768,
365 .pixclock = 15385,
366 .left_margin = 20,
367 .right_margin = 300,
368 .upper_margin = 30,
369 .lower_margin = 8,
370 .hsync_len = 1,
371 .vsync_len = 1,
372 .sync = FB_SYNC_EXT,
373 .vmode = FB_VMODE_NONINTERLACED
374} }, {
375 .bus = -1,
376 .addr = 3,
377 .pixfmt = IPU_PIX_FMT_RGB24,
378 .detect = detect_hdmi,
379 .enable = do_enable_hdmi,
380 .mode = {
381 .name = "HDMI",
382 .refresh = 60,
383 .xres = 1024,
384 .yres = 768,
385 .pixclock = 15385,
386 .left_margin = 220,
387 .right_margin = 40,
388 .upper_margin = 21,
389 .lower_margin = 7,
390 .hsync_len = 60,
391 .vsync_len = 10,
392 .sync = FB_SYNC_EXT,
393 .vmode = FB_VMODE_NONINTERLACED
394} } };
395size_t display_count = ARRAY_SIZE(displays);
396
Akshay Bhatde708da2016-04-12 18:13:57 -0400397static void setup_display_b850v3(void)
Akshay Bhatf9162b12016-01-29 15:16:40 -0500398{
399 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
400 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
Akshay Bhatf9162b12016-01-29 15:16:40 -0500401
Akshay Bhatde708da2016-04-12 18:13:57 -0400402 /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
403 clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
404
Akshay Bhatf9162b12016-01-29 15:16:40 -0500405 imx_setup_hdmi();
406
Akshay Bhatde708da2016-04-12 18:13:57 -0400407 /* Set LDB_DI0 as clock source for IPU_DI0 */
408 clrsetbits_le32(&mxc_ccm->chsccdr,
409 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
410 (CHSCCDR_CLK_SEL_LDB_DI0 <<
411 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
Akshay Bhatf9162b12016-01-29 15:16:40 -0500412
Akshay Bhatde708da2016-04-12 18:13:57 -0400413 /* Turn on IPU LDB DI0 clocks */
414 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
Akshay Bhatf9162b12016-01-29 15:16:40 -0500415
Akshay Bhatde708da2016-04-12 18:13:57 -0400416 enable_ipu_clock();
Akshay Bhatf9162b12016-01-29 15:16:40 -0500417
Akshay Bhatde708da2016-04-12 18:13:57 -0400418 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
419 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
420 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
421 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
422 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
423 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
424 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
425 IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
426 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
427 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
428 &iomux->gpr[2]);
Akshay Bhatf9162b12016-01-29 15:16:40 -0500429
Akshay Bhatde708da2016-04-12 18:13:57 -0400430 clrbits_le32(&iomux->gpr[3],
431 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
432 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
433 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
434}
Akshay Bhatf9162b12016-01-29 15:16:40 -0500435
Akshay Bhatde708da2016-04-12 18:13:57 -0400436static void setup_display_bx50v3(void)
437{
438 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
439 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
440
441 /* IPU1 DI0 clock is 480/7 = 68.5 MHz */
442 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
443
444 /* Set LDB_DI0 as clock source for IPU_DI0 */
445 clrsetbits_le32(&mxc_ccm->chsccdr,
446 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
447 (CHSCCDR_CLK_SEL_LDB_DI0 <<
448 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
449
450 /* Turn on IPU LDB DI0 clocks */
451 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
452
453 enable_ipu_clock();
454
455 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
456 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
457 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
458 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
459 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
460 &iomux->gpr[2]);
461
462 clrsetbits_le32(&iomux->gpr[3],
463 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
464 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
465 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
Akshay Bhatf9162b12016-01-29 15:16:40 -0500466
467 /* backlights off until needed */
468 imx_iomux_v3_setup_multiple_pads(backlight_pads,
469 ARRAY_SIZE(backlight_pads));
470 gpio_direction_input(LVDS_POWER_GP);
471 gpio_direction_input(LVDS_BACKLIGHT_GP);
472}
473#endif /* CONFIG_VIDEO_IPUV3 */
474
475/*
476 * Do not overwrite the console
477 * Use always serial for U-Boot console
478 */
479int overwrite_console(void)
480{
481 return 1;
482}
483
484int board_eth_init(bd_t *bis)
485{
486 setup_iomux_enet();
487 setup_pcie();
488
489 return cpu_eth_init(bis);
490}
491
492static iomux_v3_cfg_t const misc_pads[] = {
493 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
Justin Waters7d0b8cf2016-04-13 17:03:18 -0400494 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
495 MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
496 MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
497 MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
498 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
499 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
Akshay Bhatf9162b12016-01-29 15:16:40 -0500500};
501#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
502#define WIFI_EN IMX_GPIO_NR(6, 14)
503
504int board_early_init_f(void)
505{
506 imx_iomux_v3_setup_multiple_pads(misc_pads,
507 ARRAY_SIZE(misc_pads));
508
509 setup_iomux_uart();
510
Akshay Bhatf9162b12016-01-29 15:16:40 -0500511 return 0;
512}
513
514int board_init(void)
515{
516 gpio_direction_output(SUS_S3_OUT, 1);
517 gpio_direction_output(WIFI_EN, 1);
518#if defined(CONFIG_VIDEO_IPUV3)
Akshay Bhatde708da2016-04-12 18:13:57 -0400519 if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
520 setup_display_b850v3();
521 else
522 setup_display_bx50v3();
Akshay Bhatf9162b12016-01-29 15:16:40 -0500523#endif
524 /* address of boot parameters */
525 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
526
527#ifdef CONFIG_MXC_SPI
528 setup_spi();
529#endif
530 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
531 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
532 setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
533
534 return 0;
535}
536
537#ifdef CONFIG_CMD_BMODE
538static const struct boot_mode board_boot_modes[] = {
539 /* 4 bit bus width */
540 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
541 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
542 {NULL, 0},
543};
544#endif
545
546int board_late_init(void)
547{
548#ifdef CONFIG_CMD_BMODE
549 add_board_boot_modes(board_boot_modes);
550#endif
551 /* We need at least 200ms between power on and backlight on
552 * as per specifications from CHI MEI */
553 mdelay(250);
554
555 /* Backlight Power */
556 gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
557
558 return 0;
559}
560
561int checkboard(void)
562{
563 printf("BOARD: %s\n", CONFIG_BOARD_NAME);
564 return 0;
565}