| Ed Swarthout | 63cec58 | 2007-08-02 14:09:49 -0500 | [diff] [blame] | 1 | /* (C) Copyright 2007 Freescale Semiconductor, Inc. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or |
| 4 | * modify it under the terms of the GNU General Public License as |
| 5 | * published by the Free Software Foundation; either version 2 of |
| 6 | * the License, or (at your option) any later version. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program; if not, write to the Free Software |
| 15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 16 | * MA 02111-1307 USA |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #ifndef __IMMAP_85xx_fsl_pci__ |
| 21 | #define __IMMAP_85xx_fsl_pci__ |
| 22 | |
| 23 | /* |
| 24 | * Common PCI/PCIE Register structure for mpc85xx and mpc86xx |
| 25 | */ |
| 26 | |
| 27 | /* |
| 28 | * PCI Translation Registers |
| 29 | */ |
| 30 | typedef struct pci_outbound_window { |
| 31 | u32 potar; /* 0x00 - Address */ |
| 32 | u32 potear; /* 0x04 - Address Extended */ |
| 33 | u32 powbar; /* 0x08 - Window Base Address */ |
| 34 | u32 res1; |
| 35 | u32 powar; /* 0x10 - Window Attributes */ |
| 36 | #define POWAR_EN 0x80000000 |
| 37 | #define POWAR_IO_READ 0x00080000 |
| 38 | #define POWAR_MEM_READ 0x00040000 |
| 39 | #define POWAR_IO_WRITE 0x00008000 |
| 40 | #define POWAR_MEM_WRITE 0x00004000 |
| 41 | u32 res2[3]; |
| 42 | } pot_t; |
| 43 | |
| 44 | typedef struct pci_inbound_window { |
| 45 | u32 pitar; /* 0x00 - Address */ |
| 46 | u32 res1; |
| 47 | u32 piwbar; /* 0x08 - Window Base Address */ |
| 48 | u32 piwbear; /* 0x0c - Window Base Address Extended */ |
| 49 | u32 piwar; /* 0x10 - Window Attributes */ |
| 50 | #define PIWAR_EN 0x80000000 |
| 51 | #define PIWAR_PF 0x20000000 |
| 52 | #define PIWAR_LOCAL 0x00f00000 |
| 53 | #define PIWAR_READ_SNOOP 0x00050000 |
| 54 | #define PIWAR_WRITE_SNOOP 0x00005000 |
| 55 | u32 res2[3]; |
| 56 | } pit_t; |
| 57 | |
| 58 | /* PCI/PCI Express Registers */ |
| 59 | typedef struct ccsr_pci { |
| 60 | u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */ |
| 61 | u32 cfg_data; /* 0x004 - PCI Configuration Data Register */ |
| 62 | u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */ |
| 63 | u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ |
| 64 | u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ |
| 65 | u32 config; /* 0x014 - PCIE CONFIG Register */ |
| 66 | char res2[8]; |
| 67 | u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ |
| 68 | u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ |
| 69 | u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ |
| 70 | u32 pm_command; /* 0x02c - PCIE PM Command register */ |
| 71 | char res4[3016]; /* (- #xbf8 #x30)3016 */ |
| 72 | u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ |
| 73 | u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ |
| 74 | |
| 75 | pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ |
| 76 | u32 res5[64]; |
| 77 | pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */ |
| 78 | #define PIT3 0 |
| 79 | #define PIT2 1 |
| 80 | #define PIT1 2 |
| 81 | |
| 82 | #if 0 |
| 83 | u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */ |
| 84 | u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */ |
| 85 | char res5[8]; |
| 86 | u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */ |
| 87 | char res6[12]; |
| 88 | u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */ |
| 89 | u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */ |
| 90 | u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */ |
| 91 | char res7[4]; |
| 92 | u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */ |
| 93 | char res8[12]; |
| 94 | u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */ |
| 95 | u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */ |
| 96 | u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */ |
| 97 | char res9[4]; |
| 98 | u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */ |
| 99 | char res10[12]; |
| 100 | u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */ |
| 101 | u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */ |
| 102 | u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */ |
| 103 | char res11[4]; |
| 104 | u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */ |
| 105 | char res12[12]; |
| 106 | u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */ |
| 107 | u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */ |
| 108 | u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */ |
| 109 | char res13[4]; |
| 110 | u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */ |
| 111 | char res14[268]; |
| 112 | u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */ |
| 113 | char res15[4]; |
| 114 | u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */ |
| 115 | u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */ |
| 116 | u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */ |
| 117 | char res16[12]; |
| 118 | u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */ |
| 119 | char res17[4]; |
| 120 | u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */ |
| 121 | u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */ |
| 122 | u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */ |
| 123 | char res18[12]; |
| 124 | u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */ |
| 125 | char res19[4]; |
| 126 | u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */ |
| 127 | char res20[4]; |
| 128 | u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */ |
| 129 | char res21[12]; |
| 130 | #endif |
| 131 | u32 pedr; /* 0xe00 - PCI Error Detect Register */ |
| 132 | u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */ |
| 133 | u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */ |
| 134 | u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */ |
| 135 | u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */ |
| 136 | /* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */ |
| 137 | u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */ |
| 138 | u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */ |
| 139 | u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */ |
| 140 | u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */ |
| 141 | /* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */ |
| 142 | char res22[4]; |
| 143 | u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */ |
| 144 | u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ |
| 145 | u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ |
| 146 | u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ |
| 147 | char res23[456]; /* (- #x1000 #xe38) 456 */ |
| 148 | } ccsr_fsl_pci_t; |
| 149 | |
| 150 | #endif /*__IMMAP_fsl_pci__*/ |