blob: 2a731a637ba6ed32895ecef899abcec80e0e913b [file] [log] [blame]
Stefan Roese273ed032010-05-19 11:11:15 +02001/*
2 * (C) Copyright 2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21/*
22 * t3corp.h - configuration for T3CORP (460GT)
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 */
30#define CONFIG_460GT 1 /* Specific PPC460GT */
31#define CONFIG_440 1
32#define CONFIG_4xx 1 /* ... PPC4xx family */
33
Wolfgang Denk2ae18242010-10-06 09:05:45 +020034#ifndef CONFIG_SYS_TEXT_BASE
35#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
36#endif
37
Stefan Roese273ed032010-05-19 11:11:15 +020038#define CONFIG_HOSTNAME t3corp
39
40/*
41 * Include common defines/options for all AMCC/APM eval boards
42 */
43#include "amcc-common.h"
44
45#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
46
47#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
48#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
49#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
50#define CONFIG_BOARD_TYPES 1 /* support board types */
51#define CONFIG_FIT
52#define CFG_ALT_MEMTEST
53
54/*
55 * Base addresses -- Note these are effective addresses where the
56 * actual resources get mapped (not physical addresses)
57 */
58#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
59#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
60#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
61
62#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe mem */
63#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe */
64#define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
65
66#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
67#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
68#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
69#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
70
71#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit phys addr */
72
73/* base address of inbound PCIe window */
74#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit phys addr */
75
76/* EBC stuff */
77#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */
78#define CONFIG_SYS_FLASH_SIZE (64 << 20)
79
80#define CONFIG_SYS_FPGA1_BASE 0xe0000000
Stefan Roese5bf39a92010-07-19 14:24:22 +020081#define CONFIG_SYS_FPGA2_BASE 0xe2000000
82#define CONFIG_SYS_FPGA3_BASE 0xe4000000
Stefan Roese273ed032010-05-19 11:11:15 +020083
84#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
85#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
86#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
87#define CONFIG_SYS_FLASH_BASE_PHYS \
88 (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
89 | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
90
Stefan Roese5bf39a92010-07-19 14:24:22 +020091#define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */
Stefan Roese273ed032010-05-19 11:11:15 +020092#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
Wolfgang Denkbf560802010-09-10 23:04:05 +020093#define CONFIG_SYS_SRAM_SIZE (256 << 10)
Stefan Roese273ed032010-05-19 11:11:15 +020094#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
95
Stefan Roese273ed032010-05-19 11:11:15 +020096/*
97 * Initial RAM & stack pointer (placed in OCM)
98 */
99#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200100#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Stefan Roese273ed032010-05-19 11:11:15 +0200101#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200102 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Stefan Roese273ed032010-05-19 11:11:15 +0200103#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
104
105/*
106 * Serial Port
107 */
Stefan Roese550650d2010-09-20 16:05:31 +0200108#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese273ed032010-05-19 11:11:15 +0200109
110/*
111 * Environment
112 */
113/*
114 * Define here the location of the environment variables (flash).
115 */
116#define CONFIG_ENV_IS_IN_FLASH /* use flash for environment vars */
117
118/*
119 * Flash related
120 */
121#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
122#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roesecf1971c2010-10-25 18:32:08 +0200123#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
124#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
Stefan Roese5bf39a92010-07-19 14:24:22 +0200125#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
Stefan Roesecf1971c2010-10-25 18:32:08 +0200126#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
Stefan Roese273ed032010-05-19 11:11:15 +0200127
Stefan Roesecf1971c2010-10-25 18:32:08 +0200128#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
129 (CONFIG_SYS_FPGA1_BASE + 0x01000000) }
130#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff, /* don't set */ \
131 0xbddf } /* set async read mode */
132#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
Stefan Roese273ed032010-05-19 11:11:15 +0200133#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/
134
135#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/
136#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms*/
137
138#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buff'd writes (20x faster)*/
139#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
140
141#define CONFIG_ENV_SECT_SIZE 0x20000 /* sector size */
142#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - \
143 CONFIG_ENV_SECT_SIZE)
144#define CONFIG_ENV_SIZE 0x4000 /* env sector size */
145
146/* Address and size of Redundant Environment Sector */
147#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
148#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
149
150/*
151 * DDR2 SDRAM
152 */
Stefan Roese5bf39a92010-07-19 14:24:22 +0200153#define CONFIG_SYS_MBYTES_SDRAM 256
154#define CONFIG_DDR_ECC
Stefan Roese273ed032010-05-19 11:11:15 +0200155#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
156#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
157#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
158#undef CONFIG_PPC4xx_DDR_METHOD_A
Stefan Roese5bf39a92010-07-19 14:24:22 +0200159#define CONFIG_DDR_RFDC_FIXED 0x000001D7 /* optimal value */
Stefan Roese273ed032010-05-19 11:11:15 +0200160
161/* DDR1/2 SDRAM Device Control Register Data Values */
162/* Memory Queue */
163#define CONFIG_SYS_SDRAM_R0BAS (SDRAM_RXBAS_SDBA_ENCODE(0) | \
164 SDRAM_RXBAS_SDSZ_256)
165#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
166#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
167#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
168#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
169#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
170#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00
171#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
172#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
173
Stefan Roese273ed032010-05-19 11:11:15 +0200174#define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK
175
176/* DDR1/2 SDRAM Device Control Register Data Values */
177#define CONFIG_SYS_SDRAM0_MB0CF (SDRAM_RXBAS_SDAM_MODE7 | \
178 SDRAM_RXBAS_SDBE_ENABLE)
179#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
180#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
181#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
182#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_MCHK_GEN | \
183 SDRAM_MCOPT1_PMU_OPEN | \
184 SDRAM_MCOPT1_DMWD_32 | \
185 SDRAM_MCOPT1_8_BANKS | \
186 SDRAM_MCOPT1_DDR2_TYPE | \
187 SDRAM_MCOPT1_QDEP | \
188 SDRAM_MCOPT1_RWOO_DISABLED | \
189 SDRAM_MCOPT1_WOOO_DISABLED | \
190 SDRAM_MCOPT1_DREF_NORMAL)
191#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
192#define CONFIG_SYS_SDRAM0_MODT0 SDRAM_MODT_EB0W_ENABLE
193#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
194#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
195#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
196#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
197 SDRAM_CODT_DQS_1_8_V_DDR2 | \
198 SDRAM_CODT_IO_NMODE)
199#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
200#define CONFIG_SYS_SDRAM0_INITPLR0 \
201 (SDRAM_INITPLR_ENABLE | \
202 SDRAM_INITPLR_IMWT_ENCODE(80) | \
203 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
204#define CONFIG_SYS_SDRAM0_INITPLR1 \
205 (SDRAM_INITPLR_ENABLE | \
206 SDRAM_INITPLR_IMWT_ENCODE(3) | \
207 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
208 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
209 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
210#define CONFIG_SYS_SDRAM0_INITPLR2 \
211 (SDRAM_INITPLR_ENABLE | \
212 SDRAM_INITPLR_IMWT_ENCODE(2) | \
213 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
214 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
215 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
216#define CONFIG_SYS_SDRAM0_INITPLR3 \
217 (SDRAM_INITPLR_ENABLE | \
218 SDRAM_INITPLR_IMWT_ENCODE(2) | \
219 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
220 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
221 SDRAM_INITPLR_IMA_ENCODE(0))
222#define CONFIG_SYS_SDRAM0_INITPLR4 \
223 (SDRAM_INITPLR_ENABLE | \
224 SDRAM_INITPLR_IMWT_ENCODE(2) | \
225 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
226 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
227 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE | \
228 JEDEC_MA_EMR_RTT_150OHM))
229#define CONFIG_SYS_SDRAM0_INITPLR5 \
230 (SDRAM_INITPLR_ENABLE | \
231 SDRAM_INITPLR_IMWT_ENCODE(200) | \
232 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
233 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
234 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
235 CAS_LATENCY | \
236 JEDEC_MA_MR_BLEN_4 | \
237 JEDEC_MA_MR_DLL_RESET))
238#define CONFIG_SYS_SDRAM0_INITPLR6 \
239 (SDRAM_INITPLR_ENABLE | \
240 SDRAM_INITPLR_IMWT_ENCODE(3) | \
241 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
242 SDRAM_INITPLR_IBA_ENCODE(0x0) | \
243 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
244#define CONFIG_SYS_SDRAM0_INITPLR7 \
245 (SDRAM_INITPLR_ENABLE | \
246 SDRAM_INITPLR_IMWT_ENCODE(26) | \
247 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
248#define CONFIG_SYS_SDRAM0_INITPLR8 \
249 (SDRAM_INITPLR_ENABLE | \
250 SDRAM_INITPLR_IMWT_ENCODE(26) | \
251 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
252#define CONFIG_SYS_SDRAM0_INITPLR9 \
253 (SDRAM_INITPLR_ENABLE | \
254 SDRAM_INITPLR_IMWT_ENCODE(26) | \
255 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
256#define CONFIG_SYS_SDRAM0_INITPLR10 \
257 (SDRAM_INITPLR_ENABLE | \
258 SDRAM_INITPLR_IMWT_ENCODE(26) | \
259 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
260#define CONFIG_SYS_SDRAM0_INITPLR11 \
261 (SDRAM_INITPLR_ENABLE | \
262 SDRAM_INITPLR_IMWT_ENCODE(2) | \
263 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
264 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
265 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
266 CAS_LATENCY | \
267 JEDEC_MA_MR_BLEN_4))
268#define CONFIG_SYS_SDRAM0_INITPLR12 \
269 (SDRAM_INITPLR_ENABLE | \
270 SDRAM_INITPLR_IMWT_ENCODE(2) | \
271 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
272 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
273 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
274 JEDEC_MA_EMR_RDQS_DISABLE | \
275 JEDEC_MA_EMR_DQS_ENABLE | \
276 JEDEC_MA_EMR_RTT_150OHM | \
277 JEDEC_MA_EMR_ODS_NORMAL))
278#define CONFIG_SYS_SDRAM0_INITPLR13 \
279 (SDRAM_INITPLR_ENABLE | \
280 SDRAM_INITPLR_IMWT_ENCODE(2) | \
281 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
282 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
283 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
284 JEDEC_MA_EMR_RDQS_DISABLE | \
285 JEDEC_MA_EMR_DQS_ENABLE | \
286 JEDEC_MA_EMR_RTT_150OHM | \
287 JEDEC_MA_EMR_ODS_NORMAL))
288#define CONFIG_SYS_SDRAM0_INITPLR14 SDRAM_INITPLR_DISABLE
289#define CONFIG_SYS_SDRAM0_INITPLR15 SDRAM_INITPLR_DISABLE
290#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
291 SDRAM_RQDC_RQFD_ENCODE(56))
292#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(599)
293#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
294#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
295 SDRAM_DLCR_DLCS_CONT_DONE | \
296 SDRAM_DLCR_DLCV_ENCODE(155))
297#define CONFIG_SYS_SDRAM0_CLKTR SDRAM_CLKTR_CLKP_90_DEG_ADV
298#define CONFIG_SYS_SDRAM0_WRDTR SDRAM_WRDTR_WTR_90_DEG_ADV
299#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
300 SDRAM_SDTR1_RTW_2_CLK | \
301 SDRAM_SDTR1_RTRO_1_CLK)
302#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
303 SDRAM_SDTR2_WTR_2_CLK | \
304 SDRAM_SDTR2_XSNR_32_CLK | \
305 SDRAM_SDTR2_WPC_4_CLK | \
306 SDRAM_SDTR2_RPC_2_CLK | \
307 SDRAM_SDTR2_RP_3_CLK | \
308 SDRAM_SDTR2_RRD_2_CLK)
309#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \
310 SDRAM_SDTR3_RC_ENCODE(11) | \
311 SDRAM_SDTR3_XCS | \
312 SDRAM_SDTR3_RFC_ENCODE(26))
313#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
314 CAS_LATENCY | \
315 SDRAM_MMODE_BLEN_4)
316#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_ENABLE | \
317 SDRAM_MEMODE_RTT_150OHM)
318
319/*
320 * I2C
321 */
322#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
323
324#define CONFIG_SYS_I2C_MULTI_EEPROMS
325#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
326#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
327#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
328#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
329
330/* I2C bootstrap EEPROM */
331#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
332#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
333#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
334
335/*
336 * Ethernet
337 */
338#define CONFIG_IBM_EMAC4_V4 1
339
340#define CONFIG_HAS_ETH0
341
342#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
343#define CONFIG_M88E1111_PHY
344/* Disable fiber since fiber/copper auto-selection doesn't seem to work */
345#define CONFIG_M88E1111_DISABLE_FIBER
346
347#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
348#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
349#define CONFIG_PHY_DYNAMIC_ANEG 1
350
351/*
352 * Default environment variables
353 */
354#define CONFIG_EXTRA_ENV_SETTINGS \
355 CONFIG_AMCC_DEF_ENV \
356 CONFIG_AMCC_DEF_ENV_POWERPC \
357 CONFIG_AMCC_DEF_ENV_NOR_UPD \
358 "kernel_addr=fc000000\0" \
359 "fdt_addr=fc1e0000\0" \
360 "ramdisk_addr=fc200000\0" \
361 "pciconfighost=1\0" \
362 "pcie_mode=RP:RP\0" \
Stefan Roesecf1971c2010-10-25 18:32:08 +0200363 "unlock=yes\0" \
Stefan Roese273ed032010-05-19 11:11:15 +0200364 ""
365
366/*
367 * Commands additional to the ones defined in amcc-common.h
368 */
369#define CONFIG_CMD_CHIP_CONFIG
Stefan Roese1ffcb862010-07-22 19:06:27 +0200370#define CONFIG_CMD_ECCTEST
Stefan Roese273ed032010-05-19 11:11:15 +0200371#define CONFIG_CMD_PCI
372#define CONFIG_CMD_SDRAM
373
374/*
375 * PCI stuff
376 */
377/* General PCI */
378#define CONFIG_PCI /* include pci support */
379#define CONFIG_PCI_PNP /* do pci plug-and-play */
380#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
381#define CONFIG_PCI_CONFIG_HOST_BRIDGE
382
383/* Board-specific PCI, no PCI support, only PCIe */
384#undef CONFIG_SYS_PCI_TARGET_INIT
385#undef CONFIG_SYS_PCI_MASTER_INIT
386
387#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
388#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
389
390
391/*
392 * External Bus Controller (EBC) Setup
393 */
394
395/*
396 * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
397 * boot EBC mapping only supports a maximum of 16MBytes
398 * (4.ff00.0000 - 4.ffff.ffff).
399 * To solve this problem, the flash has to get remapped to another
400 * EBC address which accepts bigger regions:
401 *
402 * 0xfc00.0000 -> 4.cc00.0000
403 */
404
405/* Memory Bank 0 (NOR-flash) */
406#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
407 EBC_BXAP_TWT_ENCODE(16) | \
408 EBC_BXAP_BCE_DISABLE | \
409 EBC_BXAP_BCT_2TRANS | \
410 EBC_BXAP_CSN_ENCODE(1) | \
411 EBC_BXAP_OEN_ENCODE(1) | \
412 EBC_BXAP_WBN_ENCODE(1) | \
413 EBC_BXAP_WBF_ENCODE(1) | \
414 EBC_BXAP_TH_ENCODE(7) | \
415 EBC_BXAP_RE_DISABLED | \
416 EBC_BXAP_SOR_DELAYED | \
417 EBC_BXAP_BEM_WRITEONLY | \
418 EBC_BXAP_PEN_DISABLED)
419#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \
420 EBC_BXCR_BS_16MB | \
421 EBC_BXCR_BU_RW | \
422 EBC_BXCR_BW_16BIT)
423
424/* Memory Bank 1 (FPGA 1) */
425#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
426 EBC_BXAP_TWT_ENCODE(5) | \
427 EBC_BXAP_CSN_ENCODE(0) | \
Stefan Roese5bf39a92010-07-19 14:24:22 +0200428 EBC_BXAP_OEN_ENCODE(3) | \
Stefan Roese273ed032010-05-19 11:11:15 +0200429 EBC_BXAP_WBN_ENCODE(0) | \
430 EBC_BXAP_WBF_ENCODE(0) | \
431 EBC_BXAP_TH_ENCODE(1) | \
Stefan Roesecf1971c2010-10-25 18:32:08 +0200432 EBC_BXAP_RE_ENABLED | \
Stefan Roese273ed032010-05-19 11:11:15 +0200433 EBC_BXAP_SOR_DELAYED | \
434 EBC_BXAP_BEM_RW | \
435 EBC_BXAP_PEN_DISABLED)
436#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
Stefan Roese5bf39a92010-07-19 14:24:22 +0200437 EBC_BXCR_BS_32MB | \
Stefan Roese273ed032010-05-19 11:11:15 +0200438 EBC_BXCR_BU_RW | \
439 EBC_BXCR_BW_32BIT)
440
441/* Memory Bank 2 (FPGA 2) */
442#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
443 EBC_BXAP_TWT_ENCODE(5) | \
444 EBC_BXAP_CSN_ENCODE(0) | \
Stefan Roese5bf39a92010-07-19 14:24:22 +0200445 EBC_BXAP_OEN_ENCODE(3) | \
Stefan Roese273ed032010-05-19 11:11:15 +0200446 EBC_BXAP_WBN_ENCODE(0) | \
447 EBC_BXAP_WBF_ENCODE(0) | \
448 EBC_BXAP_TH_ENCODE(1) | \
Stefan Roesecf1971c2010-10-25 18:32:08 +0200449 EBC_BXAP_RE_ENABLED | \
Stefan Roese273ed032010-05-19 11:11:15 +0200450 EBC_BXAP_SOR_DELAYED | \
451 EBC_BXAP_BEM_RW | \
452 EBC_BXAP_PEN_DISABLED)
453#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
Stefan Roese5bf39a92010-07-19 14:24:22 +0200454 EBC_BXCR_BS_16MB | \
Stefan Roese273ed032010-05-19 11:11:15 +0200455 EBC_BXCR_BU_RW | \
456 EBC_BXCR_BW_32BIT)
457
458/* Memory Bank 3 (FPGA 3) */
459#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \
460 EBC_BXAP_TWT_ENCODE(5) | \
461 EBC_BXAP_CSN_ENCODE(0) | \
Stefan Roese5bf39a92010-07-19 14:24:22 +0200462 EBC_BXAP_OEN_ENCODE(3) | \
Stefan Roese273ed032010-05-19 11:11:15 +0200463 EBC_BXAP_WBN_ENCODE(0) | \
464 EBC_BXAP_WBF_ENCODE(0) | \
465 EBC_BXAP_TH_ENCODE(1) | \
Stefan Roesecf1971c2010-10-25 18:32:08 +0200466 EBC_BXAP_RE_ENABLED | \
Stefan Roese273ed032010-05-19 11:11:15 +0200467 EBC_BXAP_SOR_DELAYED | \
468 EBC_BXAP_BEM_RW | \
469 EBC_BXAP_PEN_DISABLED)
470#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
Stefan Roese5bf39a92010-07-19 14:24:22 +0200471 EBC_BXCR_BS_16MB | \
Stefan Roese273ed032010-05-19 11:11:15 +0200472 EBC_BXCR_BU_RW | \
473 EBC_BXCR_BW_32BIT)
474
475/*
476 * PPC4xx GPIO Configuration
477 */
478
479#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \
480{ \
481/* GPIO Core 0 */ \
482{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
483{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
484{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
485{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
486{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
487{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
488{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
489{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
490{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
491{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
492{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
493{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
494{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
495{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
496{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
497{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
498{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
499{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
500{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
501{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
502{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
503{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
504{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
505{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
506{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
507{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
508{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
509{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
510{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
511{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
512{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
513{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
514}, \
515{ \
516/* GPIO Core 1 */ \
517{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
518{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
519{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
520{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
521{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
522{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
523{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
524{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
525{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
526{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
527{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
528{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
529{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
530{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
531{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
532{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
533{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
534{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
535{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
536{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
537{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
538{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
539{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
540{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
541{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
542{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
543{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
544{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
545{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
546{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
547{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
548{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
549} \
550}
551
552#endif /* __CONFIG_H */