blob: 7eb15ed0ba4b7d867f7f835d3feab4630f042a66 [file] [log] [blame]
Dirk Eibachb9944a72013-06-26 15:55:17 +02001/*
2 * (C) Copyright 2012
3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4 *
Tom Rini9fab4bf2013-07-26 15:32:59 -04005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibachb9944a72013-06-26 15:55:17 +02006 */
7
8/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */
9
10#include <common.h>
11#include <asm/io.h>
12#include <errno.h>
13#include <i2c.h>
14
15static void dp501_setbits(u8 addr, u8 reg, u8 mask)
16{
17 u8 val;
18
19 val = i2c_reg_read(addr, reg);
20 setbits_8(&val, mask);
21 i2c_reg_write(addr, reg, val);
22}
23
24static void dp501_clrbits(u8 addr, u8 reg, u8 mask)
25{
26 u8 val;
27
28 val = i2c_reg_read(addr, reg);
29 clrbits_8(&val, mask);
30 i2c_reg_write(addr, reg, val);
31}
32
33static int dp501_detect_cable_adapter(u8 addr)
34{
35 u8 val = i2c_reg_read(addr, 0x00);
36
37 return !(val & 0x04);
38}
39
40static void dp501_link_training(u8 addr)
41{
42 u8 val;
43
44 val = i2c_reg_read(addr, 0x51);
45 i2c_reg_write(addr, 0x5d, val); /* set link_bw */
46 val = i2c_reg_read(addr, 0x52);
47 i2c_reg_write(addr, 0x5e, val); /* set lane_cnt */
48 val = i2c_reg_read(addr, 0x53);
49 i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */
50
51 i2c_reg_write(addr, 0x5f, 0x0d); /* start training */
52}
53
54void dp501_powerup(u8 addr)
55{
56 dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
Dirk Eibach5568fb42014-07-03 09:28:21 +020057 dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
Dirk Eibachb9944a72013-06-26 15:55:17 +020058 i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
59 dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
60 dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
61 i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
62 dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
63 dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
Dirk Eibachb415fec2014-07-03 09:28:23 +020064 dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */
Dirk Eibachedfe9fe2014-07-03 09:28:17 +020065
66#ifdef CONFIG_SYS_DP501_VCAPCTRL0
67 i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
68#else
Dirk Eibachb9944a72013-06-26 15:55:17 +020069 i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
Dirk Eibachedfe9fe2014-07-03 09:28:17 +020070#endif
71
72#ifdef CONFIG_SYS_DP501_DIFFERENTIAL
73 i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
74 i2c_reg_write(addr + 2, 0x25, 0x04);
75 i2c_reg_write(addr + 2, 0x26, 0x10);
76#else
Dirk Eibachb9944a72013-06-26 15:55:17 +020077 i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
Dirk Eibachedfe9fe2014-07-03 09:28:17 +020078#endif
79
80 i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
81 i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
82 i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
83 i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
84 i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
85 i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
86 dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
87 i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
88 i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
89 i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
Dirk Eibachb9944a72013-06-26 15:55:17 +020090
91 if (dp501_detect_cable_adapter(addr)) {
92 printf("DVI/HDMI cable adapter detected\n");
93 i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */
94 dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
95 } else {
96 printf("no DVI/HDMI cable adapter detected\n");
Dirk Eibachb9944a72013-06-26 15:55:17 +020097 dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
98
99 dp501_link_training(addr);
100 }
101}
102
103void dp501_powerdown(u8 addr)
104{
105 dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */
106}