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Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +09001/*
2 * include/configs/alt.h
3 * This file is alt board configuration.
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 *
7 * SPDX-License-Identifier: GPL-2.0
8 */
9
10#ifndef __ALT_H
11#define __ALT_H
12
13#undef DEBUG
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090014#define CONFIG_R8A7794
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090015#define CONFIG_RMOBILE_BOARD_STRING "Alt"
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090016
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090017#include "rcar-gen2-common.h"
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090018
Nobuhiro Iwamatsuc9b59bf72014-10-31 16:16:28 +090019#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
20#define CONFIG_SYS_TEXT_BASE 0x70000000
21#else
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090022#define CONFIG_SYS_TEXT_BASE 0xE6304000
Nobuhiro Iwamatsuc9b59bf72014-10-31 16:16:28 +090023#endif
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090024
Nobuhiro Iwamatsuc9b59bf72014-10-31 16:16:28 +090025#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
26#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
27#else
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090028#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
Nobuhiro Iwamatsuc9b59bf72014-10-31 16:16:28 +090029#endif
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090030#define STACK_AREA_SIZE 0xC000
31#define LOW_LEVEL_MERAM_STACK \
32 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
33
34/* MEMORY */
Nobuhiro Iwamatsu5ca6dfe2014-11-10 14:34:07 +090035#define RCAR_GEN2_SDRAM_BASE 0x40000000
36#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
37#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090038
39/* SCIF */
40#define CONFIG_SCIF_CONSOLE
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090041
42/* FLASH */
43#define CONFIG_SPI
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090044#define CONFIG_SH_QSPI
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090045#define CONFIG_SPI_FLASH_SPANSION
46#define CONFIG_SPI_FLASH_QUAD
47#define CONFIG_SYS_NO_FLASH
48
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090049/* SH Ether */
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090050#define CONFIG_SH_ETHER
51#define CONFIG_SH_ETHER_USE_PORT 0
52#define CONFIG_SH_ETHER_PHY_ADDR 0x1
53#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
54#define CONFIG_SH_ETHER_CACHE_WRITEBACK
55#define CONFIG_SH_ETHER_CACHE_INVALIDATE
56#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
57#define CONFIG_PHYLIB
58#define CONFIG_PHY_MICREL
59#define CONFIG_BITBANGMII
60#define CONFIG_BITBANGMII_MULTI
61
62/* Board Clock */
63#define RMOBILE_XTAL_CLK 20000000u
64#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
65#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
66#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
67#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090068
69#define CONFIG_SYS_TMU_CLK_DIV 4
70
71/* i2c */
72#define CONFIG_CMD_I2C
73#define CONFIG_SYS_I2C
74#define CONFIG_SYS_I2C_SH
75#define CONFIG_SYS_I2C_SLAVE 0x7F
76#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090077#define CONFIG_SYS_I2C_SH_SPEED0 400000
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090078#define CONFIG_SYS_I2C_SH_SPEED1 400000
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +090079#define CONFIG_SYS_I2C_SH_SPEED2 400000
80#define CONFIG_SH_I2C_DATA_HIGH 4
81#define CONFIG_SH_I2C_DATA_LOW 5
82#define CONFIG_SH_I2C_CLOCK 10000000
83
84#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
85
Nobuhiro Iwamatsu7ffc8df2014-10-31 16:30:26 +090086/* USB */
87#define CONFIG_USB_STORAGE
88#define CONFIG_USB_EHCI
89#define CONFIG_USB_EHCI_RMOBILE
90#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
91
Nobuhiro Iwamatsu2b8c0812014-12-03 15:30:30 +090092/* MMCIF */
93#define CONFIG_MMC
94#define CONFIG_GENERIC_MMC
95#define CONFIG_CMD_MMC
96
97#define CONFIG_SH_MMCIF
98#define CONFIG_SH_MMCIF_ADDR 0xee200000
99#define CONFIG_SH_MMCIF_CLK 48000000
100
Nobuhiro Iwamatsu8e2e5882014-12-02 16:52:24 +0900101/* Module stop status bits */
102/* INTC-RT */
103#define CONFIG_SMSTP0_ENA 0x00400000
104/* MSIF */
105#define CONFIG_SMSTP2_ENA 0x00002000
106/* INTC-SYS, IRQC */
107#define CONFIG_SMSTP4_ENA 0x00000180
108/* SCIF2 */
109#define CONFIG_SMSTP7_ENA 0x00080000
110
Nobuhiro Iwamatsu25f96132014-11-19 14:26:33 +0900111/* SDHI */
112#define CONFIG_SH_SDHI_FREQ 97500000
113
Nobuhiro Iwamatsucff2f5f2014-06-26 10:23:30 +0900114#endif /* __ALT_H */