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Patrice Chotard23661602019-02-12 16:50:38 +01001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright : STMicroelectronics 2018
4 */
5
6#include <dt-bindings/clock/stm32mp1-clksrc.h>
7#include "stm32mp157-u-boot.dtsi"
8#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
9
10/ {
11 aliases {
12 i2c3 = &i2c4;
13 mmc0 = &sdmmc1;
Patrick Delaunayc31000c2019-03-29 15:42:23 +010014 usb0 = &usbotg_hs;
Patrice Chotard23661602019-02-12 16:50:38 +010015 };
16 config {
17 u-boot,boot-led = "heartbeat";
18 u-boot,error-led = "error";
19 st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
Patrick Delaunay9c2214b2019-07-30 19:16:17 +020020 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
21 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
Patrice Chotard23661602019-02-12 16:50:38 +010022 };
23 led {
24 red {
25 label = "error";
26 gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
27 default-state = "off";
28 status = "okay";
29 };
30
31 blue {
32 default-state = "on";
33 };
34 };
35};
36
Patrice Chotard77457fa2019-02-12 16:50:41 +010037&adc {
Patrice Chotard77457fa2019-02-12 16:50:41 +010038 status = "okay";
Patrice Chotard77457fa2019-02-12 16:50:41 +010039};
40
Patrice Chotard23661602019-02-12 16:50:38 +010041&clk_hse {
42 st,digbypass;
43};
44
45&i2c4 {
46 u-boot,dm-pre-reloc;
47};
48
49&i2c4_pins_a {
50 u-boot,dm-pre-reloc;
51 pins {
52 u-boot,dm-pre-reloc;
53 };
54};
55
56&pmic {
57 u-boot,dm-pre-reloc;
58};
59
60&rcc {
61 st,clksrc = <
62 CLK_MPU_PLL1P
63 CLK_AXI_PLL2P
64 CLK_MCU_PLL3P
65 CLK_PLL12_HSE
66 CLK_PLL3_HSE
67 CLK_PLL4_HSE
68 CLK_RTC_LSE
69 CLK_MCO1_DISABLED
70 CLK_MCO2_DISABLED
71 >;
72
73 st,clkdiv = <
74 1 /*MPU*/
75 0 /*AXI*/
76 0 /*MCU*/
77 1 /*APB1*/
78 1 /*APB2*/
79 1 /*APB3*/
80 1 /*APB4*/
81 2 /*APB5*/
82 23 /*RTC*/
83 0 /*MCO1*/
84 0 /*MCO2*/
85 >;
86
87 st,pkcs = <
88 CLK_CKPER_HSE
89 CLK_FMC_ACLK
90 CLK_QSPI_ACLK
91 CLK_ETH_DISABLED
92 CLK_SDMMC12_PLL4P
93 CLK_DSI_DSIPLL
94 CLK_STGEN_HSE
95 CLK_USBPHY_HSE
96 CLK_SPI2S1_PLL3Q
97 CLK_SPI2S23_PLL3Q
98 CLK_SPI45_HSI
99 CLK_SPI6_HSI
100 CLK_I2C46_HSI
101 CLK_SDMMC3_PLL4P
102 CLK_USBO_USBPHY
103 CLK_ADC_CKPER
104 CLK_CEC_LSE
105 CLK_I2C12_HSI
106 CLK_I2C35_HSI
107 CLK_UART1_HSI
108 CLK_UART24_HSI
109 CLK_UART35_HSI
110 CLK_UART6_HSI
111 CLK_UART78_HSI
112 CLK_SPDIF_PLL4P
Antonio Borneodb0cd2d2020-01-28 10:11:01 +0100113 CLK_FDCAN_PLL4R
Patrice Chotard23661602019-02-12 16:50:38 +0100114 CLK_SAI1_PLL3Q
115 CLK_SAI2_PLL3Q
116 CLK_SAI3_PLL3Q
117 CLK_SAI4_PLL3Q
118 CLK_RNG1_LSI
119 CLK_RNG2_LSI
120 CLK_LPTIM1_PCLK1
121 CLK_LPTIM23_PCLK3
122 CLK_LPTIM45_LSE
123 >;
124
125 /* VCO = 1300.0 MHz => P = 650 (CPU) */
126 pll1: st,pll@0 {
127 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
128 frac = < 0x800 >;
129 u-boot,dm-pre-reloc;
130 };
131
132 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
133 pll2: st,pll@1 {
134 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
135 frac = < 0x1400 >;
136 u-boot,dm-pre-reloc;
137 };
138
139 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
140 pll3: st,pll@2 {
141 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
142 frac = < 0x1a04 >;
143 u-boot,dm-pre-reloc;
144 };
145
146 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
147 pll4: st,pll@3 {
148 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
149 u-boot,dm-pre-reloc;
150 };
151};
152
153&sdmmc1 {
154 u-boot,dm-spl;
155};
156
157&sdmmc1_b4_pins_a {
158 u-boot,dm-spl;
159 pins {
160 u-boot,dm-spl;
161 };
162};
163
164&uart4 {
165 u-boot,dm-pre-reloc;
166};
167
168&uart4_pins_a {
169 u-boot,dm-pre-reloc;
170 pins1 {
171 u-boot,dm-pre-reloc;
172 };
173 pins2 {
174 u-boot,dm-pre-reloc;
Patrick Delaunay7acda7e2019-07-30 19:16:18 +0200175 /* pull-up on rx to avoid floating level */
176 bias-pull-up;
Patrice Chotard23661602019-02-12 16:50:38 +0100177 };
178};
179
180&usbotg_hs {
Patrick Delaunay6fe7dd32019-03-29 15:42:24 +0100181 u-boot,force-b-session-valid;
Patrice Chotard23661602019-02-12 16:50:38 +0100182 hnp-srp-disable;
183};