blob: e9671d9b76b5b877d57afdd40c8346f8ff21196a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassff3e0772015-03-05 12:25:25 -07002/*
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
Simon Glassff3e0772015-03-05 12:25:25 -07005 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
Simon Glassff3e0772015-03-05 12:25:25 -070010#include <inttypes.h>
11#include <pci.h>
Simon Glass21d1fe72015-11-29 13:18:03 -070012#include <asm/io.h>
Simon Glassff3e0772015-03-05 12:25:25 -070013#include <dm/device-internal.h>
Simon Glassbf501592017-05-18 20:09:51 -060014#include <dm/lists.h>
Bin Meng348b7442015-08-20 06:40:23 -070015#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
16#include <asm/fsp/fsp_support.h>
17#endif
Simon Glass5e23b8b2015-11-29 13:17:49 -070018#include "pci_internal.h"
Simon Glassff3e0772015-03-05 12:25:25 -070019
20DECLARE_GLOBAL_DATA_PTR;
21
Simon Glassa6eb93b2016-01-18 20:19:14 -070022int pci_get_bus(int busnum, struct udevice **busp)
Simon Glass983c6ba22015-08-31 18:55:35 -060023{
24 int ret;
25
26 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
27
28 /* Since buses may not be numbered yet try a little harder with bus 0 */
29 if (ret == -ENODEV) {
Simon Glass3f603cb2016-02-11 13:23:26 -070030 ret = uclass_first_device_err(UCLASS_PCI, busp);
Simon Glass983c6ba22015-08-31 18:55:35 -060031 if (ret)
32 return ret;
Simon Glass983c6ba22015-08-31 18:55:35 -060033 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
34 }
35
36 return ret;
37}
38
Simon Glass9f60fb02015-11-19 20:27:00 -070039struct udevice *pci_get_controller(struct udevice *dev)
40{
41 while (device_is_on_pci_bus(dev))
42 dev = dev->parent;
43
44 return dev;
45}
46
Simon Glass21ccce12015-11-29 13:17:47 -070047pci_dev_t dm_pci_get_bdf(struct udevice *dev)
Simon Glass4b515e42015-07-06 16:47:46 -060048{
49 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
50 struct udevice *bus = dev->parent;
51
52 return PCI_ADD_BUS(bus->seq, pplat->devfn);
53}
54
Simon Glassff3e0772015-03-05 12:25:25 -070055/**
56 * pci_get_bus_max() - returns the bus number of the last active bus
57 *
58 * @return last bus number, or -1 if no active buses
59 */
60static int pci_get_bus_max(void)
61{
62 struct udevice *bus;
63 struct uclass *uc;
64 int ret = -1;
65
66 ret = uclass_get(UCLASS_PCI, &uc);
67 uclass_foreach_dev(bus, uc) {
68 if (bus->seq > ret)
69 ret = bus->seq;
70 }
71
72 debug("%s: ret=%d\n", __func__, ret);
73
74 return ret;
75}
76
77int pci_last_busno(void)
78{
Bin Meng069155c2015-10-01 00:36:01 -070079 return pci_get_bus_max();
Simon Glassff3e0772015-03-05 12:25:25 -070080}
81
82int pci_get_ff(enum pci_size_t size)
83{
84 switch (size) {
85 case PCI_SIZE_8:
86 return 0xff;
87 case PCI_SIZE_16:
88 return 0xffff;
89 default:
90 return 0xffffffff;
91 }
92}
93
94int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
95 struct udevice **devp)
96{
97 struct udevice *dev;
98
99 for (device_find_first_child(bus, &dev);
100 dev;
101 device_find_next_child(&dev)) {
102 struct pci_child_platdata *pplat;
103
104 pplat = dev_get_parent_platdata(dev);
105 if (pplat && pplat->devfn == find_devfn) {
106 *devp = dev;
107 return 0;
108 }
109 }
110
111 return -ENODEV;
112}
113
Simon Glassf3f1fae2015-11-29 13:17:48 -0700114int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
Simon Glassff3e0772015-03-05 12:25:25 -0700115{
116 struct udevice *bus;
117 int ret;
118
Simon Glass983c6ba22015-08-31 18:55:35 -0600119 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700120 if (ret)
121 return ret;
122 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
123}
124
125static int pci_device_matches_ids(struct udevice *dev,
126 struct pci_device_id *ids)
127{
128 struct pci_child_platdata *pplat;
129 int i;
130
131 pplat = dev_get_parent_platdata(dev);
132 if (!pplat)
133 return -EINVAL;
134 for (i = 0; ids[i].vendor != 0; i++) {
135 if (pplat->vendor == ids[i].vendor &&
136 pplat->device == ids[i].device)
137 return i;
138 }
139
140 return -EINVAL;
141}
142
143int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
144 int *indexp, struct udevice **devp)
145{
146 struct udevice *dev;
147
148 /* Scan all devices on this bus */
149 for (device_find_first_child(bus, &dev);
150 dev;
151 device_find_next_child(&dev)) {
152 if (pci_device_matches_ids(dev, ids) >= 0) {
153 if ((*indexp)-- <= 0) {
154 *devp = dev;
155 return 0;
156 }
157 }
158 }
159
160 return -ENODEV;
161}
162
163int pci_find_device_id(struct pci_device_id *ids, int index,
164 struct udevice **devp)
165{
166 struct udevice *bus;
167
168 /* Scan all known buses */
169 for (uclass_first_device(UCLASS_PCI, &bus);
170 bus;
171 uclass_next_device(&bus)) {
172 if (!pci_bus_find_devices(bus, ids, &index, devp))
173 return 0;
174 }
175 *devp = NULL;
176
177 return -ENODEV;
178}
179
Simon Glass5c0bf642015-11-29 13:17:50 -0700180static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
181 unsigned int device, int *indexp,
182 struct udevice **devp)
183{
184 struct pci_child_platdata *pplat;
185 struct udevice *dev;
186
187 for (device_find_first_child(bus, &dev);
188 dev;
189 device_find_next_child(&dev)) {
190 pplat = dev_get_parent_platdata(dev);
191 if (pplat->vendor == vendor && pplat->device == device) {
192 if (!(*indexp)--) {
193 *devp = dev;
194 return 0;
195 }
196 }
197 }
198
199 return -ENODEV;
200}
201
202int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
203 struct udevice **devp)
204{
205 struct udevice *bus;
206
207 /* Scan all known buses */
208 for (uclass_first_device(UCLASS_PCI, &bus);
209 bus;
210 uclass_next_device(&bus)) {
211 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
212 return device_probe(*devp);
213 }
214 *devp = NULL;
215
216 return -ENODEV;
217}
218
Simon Glassa0eb8352015-11-29 13:17:52 -0700219int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
220{
221 struct udevice *dev;
222
223 /* Scan all known buses */
224 for (pci_find_first_device(&dev);
225 dev;
226 pci_find_next_device(&dev)) {
227 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
228
229 if (pplat->class == find_class && !index--) {
230 *devp = dev;
231 return device_probe(*devp);
232 }
233 }
234 *devp = NULL;
235
236 return -ENODEV;
237}
238
Simon Glassff3e0772015-03-05 12:25:25 -0700239int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
240 unsigned long value, enum pci_size_t size)
241{
242 struct dm_pci_ops *ops;
243
244 ops = pci_get_ops(bus);
245 if (!ops->write_config)
246 return -ENOSYS;
247 return ops->write_config(bus, bdf, offset, value, size);
248}
249
Simon Glass319dba12016-03-06 19:27:52 -0700250int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
251 u32 clr, u32 set)
252{
253 ulong val;
254 int ret;
255
256 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
257 if (ret)
258 return ret;
259 val &= ~clr;
260 val |= set;
261
262 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
263}
264
Simon Glassff3e0772015-03-05 12:25:25 -0700265int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
266 enum pci_size_t size)
267{
268 struct udevice *bus;
269 int ret;
270
Simon Glass983c6ba22015-08-31 18:55:35 -0600271 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700272 if (ret)
273 return ret;
274
Bin Meng4d8615c2015-07-19 00:20:04 +0800275 return pci_bus_write_config(bus, bdf, offset, value, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700276}
277
Simon Glass66afb4e2015-08-10 07:05:03 -0600278int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
279 enum pci_size_t size)
280{
281 struct udevice *bus;
282
Bin Meng1e0f2262015-09-11 03:24:34 -0700283 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600284 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700285 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
286 size);
Simon Glass66afb4e2015-08-10 07:05:03 -0600287}
288
Simon Glassff3e0772015-03-05 12:25:25 -0700289int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
290{
291 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
292}
293
294int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
295{
296 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
297}
298
299int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
300{
301 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
302}
303
Simon Glass66afb4e2015-08-10 07:05:03 -0600304int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
305{
306 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
307}
308
309int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
310{
311 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
312}
313
314int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
315{
316 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
317}
318
Simon Glassff3e0772015-03-05 12:25:25 -0700319int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
320 unsigned long *valuep, enum pci_size_t size)
321{
322 struct dm_pci_ops *ops;
323
324 ops = pci_get_ops(bus);
325 if (!ops->read_config)
326 return -ENOSYS;
327 return ops->read_config(bus, bdf, offset, valuep, size);
328}
329
330int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
331 enum pci_size_t size)
332{
333 struct udevice *bus;
334 int ret;
335
Simon Glass983c6ba22015-08-31 18:55:35 -0600336 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700337 if (ret)
338 return ret;
339
Bin Meng4d8615c2015-07-19 00:20:04 +0800340 return pci_bus_read_config(bus, bdf, offset, valuep, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700341}
342
Simon Glass66afb4e2015-08-10 07:05:03 -0600343int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
344 enum pci_size_t size)
345{
346 struct udevice *bus;
347
Bin Meng1e0f2262015-09-11 03:24:34 -0700348 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600349 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700350 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
Simon Glass66afb4e2015-08-10 07:05:03 -0600351 size);
352}
353
Simon Glassff3e0772015-03-05 12:25:25 -0700354int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
355{
356 unsigned long value;
357 int ret;
358
359 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
360 if (ret)
361 return ret;
362 *valuep = value;
363
364 return 0;
365}
366
367int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
368{
369 unsigned long value;
370 int ret;
371
372 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
373 if (ret)
374 return ret;
375 *valuep = value;
376
377 return 0;
378}
379
380int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
381{
382 unsigned long value;
383 int ret;
384
385 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
386 if (ret)
387 return ret;
388 *valuep = value;
389
390 return 0;
391}
392
Simon Glass66afb4e2015-08-10 07:05:03 -0600393int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
394{
395 unsigned long value;
396 int ret;
397
398 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
399 if (ret)
400 return ret;
401 *valuep = value;
402
403 return 0;
404}
405
406int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
407{
408 unsigned long value;
409 int ret;
410
411 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
412 if (ret)
413 return ret;
414 *valuep = value;
415
416 return 0;
417}
418
419int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
420{
421 unsigned long value;
422 int ret;
423
424 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
425 if (ret)
426 return ret;
427 *valuep = value;
428
429 return 0;
430}
431
Simon Glass319dba12016-03-06 19:27:52 -0700432int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
433{
434 u8 val;
435 int ret;
436
437 ret = dm_pci_read_config8(dev, offset, &val);
438 if (ret)
439 return ret;
440 val &= ~clr;
441 val |= set;
442
443 return dm_pci_write_config8(dev, offset, val);
444}
445
446int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
447{
448 u16 val;
449 int ret;
450
451 ret = dm_pci_read_config16(dev, offset, &val);
452 if (ret)
453 return ret;
454 val &= ~clr;
455 val |= set;
456
457 return dm_pci_write_config16(dev, offset, val);
458}
459
460int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
461{
462 u32 val;
463 int ret;
464
465 ret = dm_pci_read_config32(dev, offset, &val);
466 if (ret)
467 return ret;
468 val &= ~clr;
469 val |= set;
470
471 return dm_pci_write_config32(dev, offset, val);
472}
473
Bin Mengbbbcb522015-10-01 00:36:02 -0700474static void set_vga_bridge_bits(struct udevice *dev)
475{
476 struct udevice *parent = dev->parent;
477 u16 bc;
478
479 while (parent->seq != 0) {
480 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
481 bc |= PCI_BRIDGE_CTL_VGA;
482 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
483 parent = parent->parent;
484 }
485}
486
Simon Glassff3e0772015-03-05 12:25:25 -0700487int pci_auto_config_devices(struct udevice *bus)
488{
489 struct pci_controller *hose = bus->uclass_priv;
Bin Mengbbbcb522015-10-01 00:36:02 -0700490 struct pci_child_platdata *pplat;
Simon Glassff3e0772015-03-05 12:25:25 -0700491 unsigned int sub_bus;
492 struct udevice *dev;
493 int ret;
494
495 sub_bus = bus->seq;
496 debug("%s: start\n", __func__);
497 pciauto_config_init(hose);
498 for (ret = device_find_first_child(bus, &dev);
499 !ret && dev;
500 ret = device_find_next_child(&dev)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700501 unsigned int max_bus;
Simon Glass4d214552015-09-08 17:52:47 -0600502 int ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700503
Simon Glassff3e0772015-03-05 12:25:25 -0700504 debug("%s: device %s\n", __func__, dev->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700505 ret = dm_pciauto_config_device(dev);
Simon Glass4d214552015-09-08 17:52:47 -0600506 if (ret < 0)
507 return ret;
508 max_bus = ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700509 sub_bus = max(sub_bus, max_bus);
Bin Mengbbbcb522015-10-01 00:36:02 -0700510
511 pplat = dev_get_parent_platdata(dev);
512 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
513 set_vga_bridge_bits(dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700514 }
515 debug("%s: done\n", __func__);
516
517 return sub_bus;
518}
519
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +0300520int pci_generic_mmap_write_config(
521 struct udevice *bus,
522 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
523 pci_dev_t bdf,
524 uint offset,
525 ulong value,
526 enum pci_size_t size)
527{
528 void *address;
529
530 if (addr_f(bus, bdf, offset, &address) < 0)
531 return 0;
532
533 switch (size) {
534 case PCI_SIZE_8:
535 writeb(value, address);
536 return 0;
537 case PCI_SIZE_16:
538 writew(value, address);
539 return 0;
540 case PCI_SIZE_32:
541 writel(value, address);
542 return 0;
543 default:
544 return -EINVAL;
545 }
546}
547
548int pci_generic_mmap_read_config(
549 struct udevice *bus,
550 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
551 pci_dev_t bdf,
552 uint offset,
553 ulong *valuep,
554 enum pci_size_t size)
555{
556 void *address;
557
558 if (addr_f(bus, bdf, offset, &address) < 0) {
559 *valuep = pci_get_ff(size);
560 return 0;
561 }
562
563 switch (size) {
564 case PCI_SIZE_8:
565 *valuep = readb(address);
566 return 0;
567 case PCI_SIZE_16:
568 *valuep = readw(address);
569 return 0;
570 case PCI_SIZE_32:
571 *valuep = readl(address);
572 return 0;
573 default:
574 return -EINVAL;
575 }
576}
577
Simon Glass5e23b8b2015-11-29 13:17:49 -0700578int dm_pci_hose_probe_bus(struct udevice *bus)
Simon Glassff3e0772015-03-05 12:25:25 -0700579{
Simon Glassff3e0772015-03-05 12:25:25 -0700580 int sub_bus;
581 int ret;
582
583 debug("%s\n", __func__);
Simon Glassff3e0772015-03-05 12:25:25 -0700584
585 sub_bus = pci_get_bus_max() + 1;
586 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700587 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700588
589 ret = device_probe(bus);
590 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600591 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
Simon Glassff3e0772015-03-05 12:25:25 -0700592 ret);
593 return ret;
594 }
595 if (sub_bus != bus->seq) {
596 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
597 __func__, bus->name, bus->seq, sub_bus);
598 return -EPIPE;
599 }
600 sub_bus = pci_get_bus_max();
Simon Glass5e23b8b2015-11-29 13:17:49 -0700601 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700602
603 return sub_bus;
604}
605
Simon Glassaba92962015-07-06 16:47:44 -0600606/**
607 * pci_match_one_device - Tell if a PCI device structure has a matching
608 * PCI device id structure
609 * @id: single PCI device id structure to match
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800610 * @find: the PCI device id structure to match against
Simon Glassaba92962015-07-06 16:47:44 -0600611 *
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800612 * Returns true if the finding pci_device_id structure matched or false if
613 * there is no match.
Simon Glassaba92962015-07-06 16:47:44 -0600614 */
615static bool pci_match_one_id(const struct pci_device_id *id,
616 const struct pci_device_id *find)
617{
618 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
619 (id->device == PCI_ANY_ID || id->device == find->device) &&
620 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
621 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
622 !((id->class ^ find->class) & id->class_mask))
623 return true;
624
625 return false;
626}
627
628/**
629 * pci_find_and_bind_driver() - Find and bind the right PCI driver
630 *
631 * This only looks at certain fields in the descriptor.
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600632 *
633 * @parent: Parent bus
634 * @find_id: Specification of the driver to find
635 * @bdf: Bus/device/function addreess - see PCI_BDF()
636 * @devp: Returns a pointer to the device created
637 * @return 0 if OK, -EPERM if the device is not needed before relocation and
638 * therefore was not created, other -ve value on error
Simon Glassaba92962015-07-06 16:47:44 -0600639 */
640static int pci_find_and_bind_driver(struct udevice *parent,
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600641 struct pci_device_id *find_id,
642 pci_dev_t bdf, struct udevice **devp)
Simon Glassaba92962015-07-06 16:47:44 -0600643{
644 struct pci_driver_entry *start, *entry;
645 const char *drv;
646 int n_ents;
647 int ret;
648 char name[30], *str;
Bin Meng08fc7b82015-08-20 06:40:17 -0700649 bool bridge;
Simon Glassaba92962015-07-06 16:47:44 -0600650
651 *devp = NULL;
652
653 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
654 find_id->vendor, find_id->device);
655 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
656 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
657 for (entry = start; entry != start + n_ents; entry++) {
658 const struct pci_device_id *id;
659 struct udevice *dev;
660 const struct driver *drv;
661
662 for (id = entry->match;
663 id->vendor || id->subvendor || id->class_mask;
664 id++) {
665 if (!pci_match_one_id(id, find_id))
666 continue;
667
668 drv = entry->driver;
Bin Meng08fc7b82015-08-20 06:40:17 -0700669
670 /*
671 * In the pre-relocation phase, we only bind devices
672 * whose driver has the DM_FLAG_PRE_RELOC set, to save
673 * precious memory space as on some platforms as that
674 * space is pretty limited (ie: using Cache As RAM).
675 */
676 if (!(gd->flags & GD_FLG_RELOC) &&
677 !(drv->flags & DM_FLAG_PRE_RELOC))
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600678 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700679
Simon Glassaba92962015-07-06 16:47:44 -0600680 /*
681 * We could pass the descriptor to the driver as
682 * platdata (instead of NULL) and allow its bind()
683 * method to return -ENOENT if it doesn't support this
684 * device. That way we could continue the search to
685 * find another driver. For now this doesn't seem
686 * necesssary, so just bind the first match.
687 */
688 ret = device_bind(parent, drv, drv->name, NULL, -1,
689 &dev);
690 if (ret)
691 goto error;
692 debug("%s: Match found: %s\n", __func__, drv->name);
Bin Menged698aa2018-08-03 01:14:44 -0700693 dev->driver_data = id->driver_data;
Simon Glassaba92962015-07-06 16:47:44 -0600694 *devp = dev;
695 return 0;
696 }
697 }
698
Bin Meng08fc7b82015-08-20 06:40:17 -0700699 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
700 /*
701 * In the pre-relocation phase, we only bind bridge devices to save
702 * precious memory space as on some platforms as that space is pretty
703 * limited (ie: using Cache As RAM).
704 */
705 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600706 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700707
Simon Glassaba92962015-07-06 16:47:44 -0600708 /* Bind a generic driver so that the device can be used */
Bin Meng4d8615c2015-07-19 00:20:04 +0800709 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
710 PCI_FUNC(bdf));
Simon Glassaba92962015-07-06 16:47:44 -0600711 str = strdup(name);
712 if (!str)
713 return -ENOMEM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700714 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
715
Simon Glassaba92962015-07-06 16:47:44 -0600716 ret = device_bind_driver(parent, drv, str, devp);
717 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600718 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
xypron.glpk@gmx.dec42640c2017-05-08 20:40:16 +0200719 free(str);
Simon Glassaba92962015-07-06 16:47:44 -0600720 return ret;
721 }
722 debug("%s: No match found: bound generic driver instead\n", __func__);
723
724 return 0;
725
726error:
727 debug("%s: No match found: error %d\n", __func__, ret);
728 return ret;
729}
730
Simon Glassff3e0772015-03-05 12:25:25 -0700731int pci_bind_bus_devices(struct udevice *bus)
732{
733 ulong vendor, device;
734 ulong header_type;
Bin Meng4d8615c2015-07-19 00:20:04 +0800735 pci_dev_t bdf, end;
Simon Glassff3e0772015-03-05 12:25:25 -0700736 bool found_multi;
737 int ret;
738
739 found_multi = false;
Bin Meng4d8615c2015-07-19 00:20:04 +0800740 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
741 PCI_MAX_PCI_FUNCTIONS - 1);
Yoshinori Sato6d9f5b02016-04-25 15:41:01 +0900742 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
Bin Meng4d8615c2015-07-19 00:20:04 +0800743 bdf += PCI_BDF(0, 0, 1)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700744 struct pci_child_platdata *pplat;
745 struct udevice *dev;
746 ulong class;
747
Bin Meng64e45f72018-08-03 01:14:37 -0700748 if (!PCI_FUNC(bdf))
749 found_multi = false;
Bin Meng4d8615c2015-07-19 00:20:04 +0800750 if (PCI_FUNC(bdf) && !found_multi)
Simon Glassff3e0772015-03-05 12:25:25 -0700751 continue;
752 /* Check only the first access, we don't expect problems */
Bin Meng4d8615c2015-07-19 00:20:04 +0800753 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
Simon Glassff3e0772015-03-05 12:25:25 -0700754 &header_type, PCI_SIZE_8);
755 if (ret)
756 goto error;
Bin Meng4d8615c2015-07-19 00:20:04 +0800757 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
Simon Glassff3e0772015-03-05 12:25:25 -0700758 PCI_SIZE_16);
759 if (vendor == 0xffff || vendor == 0x0000)
760 continue;
761
Bin Meng4d8615c2015-07-19 00:20:04 +0800762 if (!PCI_FUNC(bdf))
Simon Glassff3e0772015-03-05 12:25:25 -0700763 found_multi = header_type & 0x80;
764
765 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
Bin Meng4d8615c2015-07-19 00:20:04 +0800766 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
767 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
Simon Glassff3e0772015-03-05 12:25:25 -0700768 PCI_SIZE_16);
Bin Meng4d8615c2015-07-19 00:20:04 +0800769 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
Simon Glassaba92962015-07-06 16:47:44 -0600770 PCI_SIZE_32);
771 class >>= 8;
Simon Glassff3e0772015-03-05 12:25:25 -0700772
773 /* Find this device in the device tree */
Bin Meng4d8615c2015-07-19 00:20:04 +0800774 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700775
Simon Glass8bd42522015-11-29 13:18:09 -0700776 /* If nothing in the device tree, bind a device */
Simon Glassff3e0772015-03-05 12:25:25 -0700777 if (ret == -ENODEV) {
Simon Glassaba92962015-07-06 16:47:44 -0600778 struct pci_device_id find_id;
779 ulong val;
Simon Glassff3e0772015-03-05 12:25:25 -0700780
Simon Glassaba92962015-07-06 16:47:44 -0600781 memset(&find_id, '\0', sizeof(find_id));
782 find_id.vendor = vendor;
783 find_id.device = device;
784 find_id.class = class;
785 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
Bin Meng4d8615c2015-07-19 00:20:04 +0800786 pci_bus_read_config(bus, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600787 PCI_SUBSYSTEM_VENDOR_ID,
788 &val, PCI_SIZE_32);
789 find_id.subvendor = val & 0xffff;
790 find_id.subdevice = val >> 16;
791 }
Bin Meng4d8615c2015-07-19 00:20:04 +0800792 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600793 &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700794 }
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600795 if (ret == -EPERM)
796 continue;
797 else if (ret)
Simon Glassff3e0772015-03-05 12:25:25 -0700798 return ret;
799
800 /* Update the platform data */
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600801 pplat = dev_get_parent_platdata(dev);
802 pplat->devfn = PCI_MASK_BUS(bdf);
803 pplat->vendor = vendor;
804 pplat->device = device;
805 pplat->class = class;
Simon Glassff3e0772015-03-05 12:25:25 -0700806 }
807
808 return 0;
809error:
810 printf("Cannot read bus configuration: %d\n", ret);
811
812 return ret;
813}
814
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700815static void decode_regions(struct pci_controller *hose, ofnode parent_node,
816 ofnode node)
Simon Glassff3e0772015-03-05 12:25:25 -0700817{
818 int pci_addr_cells, addr_cells, size_cells;
819 int cells_per_record;
820 const u32 *prop;
821 int len;
822 int i;
823
Masahiro Yamada61e51ba2017-06-22 16:54:05 +0900824 prop = ofnode_get_property(node, "ranges", &len);
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700825 if (!prop) {
826 debug("%s: Cannot decode regions\n", __func__);
827 return;
828 }
829
Simon Glass878d68c2017-06-12 06:21:31 -0600830 pci_addr_cells = ofnode_read_simple_addr_cells(node);
831 addr_cells = ofnode_read_simple_addr_cells(parent_node);
832 size_cells = ofnode_read_simple_size_cells(node);
Simon Glassff3e0772015-03-05 12:25:25 -0700833
834 /* PCI addresses are always 3-cells */
835 len /= sizeof(u32);
836 cells_per_record = pci_addr_cells + addr_cells + size_cells;
837 hose->region_count = 0;
838 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
839 cells_per_record);
840 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
841 u64 pci_addr, addr, size;
842 int space_code;
843 u32 flags;
844 int type;
Simon Glass9526d832015-11-19 20:26:58 -0700845 int pos;
Simon Glassff3e0772015-03-05 12:25:25 -0700846
847 if (len < cells_per_record)
848 break;
849 flags = fdt32_to_cpu(prop[0]);
850 space_code = (flags >> 24) & 3;
851 pci_addr = fdtdec_get_number(prop + 1, 2);
852 prop += pci_addr_cells;
853 addr = fdtdec_get_number(prop, addr_cells);
854 prop += addr_cells;
855 size = fdtdec_get_number(prop, size_cells);
856 prop += size_cells;
857 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
858 ", size=%" PRIx64 ", space_code=%d\n", __func__,
859 hose->region_count, pci_addr, addr, size, space_code);
860 if (space_code & 2) {
861 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
862 PCI_REGION_MEM;
863 } else if (space_code & 1) {
864 type = PCI_REGION_IO;
865 } else {
866 continue;
867 }
Tuomas Tynkkynen52ba9072018-05-14 18:47:50 +0300868
869 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
870 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
871 debug(" - beyond the 32-bit boundary, ignoring\n");
872 continue;
873 }
874
Simon Glass9526d832015-11-19 20:26:58 -0700875 pos = -1;
876 for (i = 0; i < hose->region_count; i++) {
877 if (hose->regions[i].flags == type)
878 pos = i;
879 }
880 if (pos == -1)
881 pos = hose->region_count++;
882 debug(" - type=%d, pos=%d\n", type, pos);
883 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
Simon Glassff3e0772015-03-05 12:25:25 -0700884 }
885
886 /* Add a region for our local memory */
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100887#ifdef CONFIG_NR_DRAM_BANKS
888 bd_t *bd = gd->bd;
889
Bin Meng1eaf7802018-03-27 00:46:05 -0700890 if (!bd)
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700891 return;
Bin Meng1eaf7802018-03-27 00:46:05 -0700892
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100893 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
894 if (bd->bi_dram[i].size) {
895 pci_set_region(hose->regions + hose->region_count++,
896 bd->bi_dram[i].start,
897 bd->bi_dram[i].start,
898 bd->bi_dram[i].size,
899 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
900 }
901 }
902#else
903 phys_addr_t base = 0, size;
904
Simon Glass2084c5a2015-11-19 20:26:57 -0700905 size = gd->ram_size;
906#ifdef CONFIG_SYS_SDRAM_BASE
907 base = CONFIG_SYS_SDRAM_BASE;
908#endif
909 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
910 size = gd->pci_ram_top - base;
Bin Mengee1109b2018-03-27 00:46:06 -0700911 if (size)
912 pci_set_region(hose->regions + hose->region_count++, base,
913 base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100914#endif
Simon Glassff3e0772015-03-05 12:25:25 -0700915
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700916 return;
Simon Glassff3e0772015-03-05 12:25:25 -0700917}
918
919static int pci_uclass_pre_probe(struct udevice *bus)
920{
921 struct pci_controller *hose;
Simon Glassff3e0772015-03-05 12:25:25 -0700922
923 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
924 bus->parent->name);
925 hose = bus->uclass_priv;
926
927 /* For bridges, use the top-level PCI controller */
Paul Burton65f62b12016-09-08 07:47:32 +0100928 if (!device_is_on_pci_bus(bus)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700929 hose->ctlr = bus;
Christian Gmeinerf2825f62018-06-10 06:25:05 -0700930 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
Simon Glassff3e0772015-03-05 12:25:25 -0700931 } else {
932 struct pci_controller *parent_hose;
933
934 parent_hose = dev_get_uclass_priv(bus->parent);
935 hose->ctlr = parent_hose->bus;
936 }
937 hose->bus = bus;
938 hose->first_busno = bus->seq;
939 hose->last_busno = bus->seq;
940
941 return 0;
942}
943
944static int pci_uclass_post_probe(struct udevice *bus)
945{
946 int ret;
947
Simon Glassff3e0772015-03-05 12:25:25 -0700948 debug("%s: probing bus %d\n", __func__, bus->seq);
949 ret = pci_bind_bus_devices(bus);
950 if (ret)
951 return ret;
952
953#ifdef CONFIG_PCI_PNP
954 ret = pci_auto_config_devices(bus);
Simon Glass4d214552015-09-08 17:52:47 -0600955 if (ret < 0)
956 return ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700957#endif
958
Bin Meng348b7442015-08-20 06:40:23 -0700959#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
960 /*
961 * Per Intel FSP specification, we should call FSP notify API to
962 * inform FSP that PCI enumeration has been done so that FSP will
963 * do any necessary initialization as required by the chipset's
964 * BIOS Writer's Guide (BWG).
965 *
966 * Unfortunately we have to put this call here as with driver model,
967 * the enumeration is all done on a lazy basis as needed, so until
968 * something is touched on PCI it won't happen.
969 *
970 * Note we only call this 1) after U-Boot is relocated, and 2)
971 * root bus has finished probing.
972 */
Simon Glass4d214552015-09-08 17:52:47 -0600973 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
Bin Meng348b7442015-08-20 06:40:23 -0700974 ret = fsp_init_phase_pci();
Simon Glass4d214552015-09-08 17:52:47 -0600975 if (ret)
976 return ret;
977 }
Bin Meng348b7442015-08-20 06:40:23 -0700978#endif
979
Simon Glass4d214552015-09-08 17:52:47 -0600980 return 0;
Simon Glassff3e0772015-03-05 12:25:25 -0700981}
982
983static int pci_uclass_child_post_bind(struct udevice *dev)
984{
985 struct pci_child_platdata *pplat;
986 struct fdt_pci_addr addr;
987 int ret;
988
Simon Glassbf501592017-05-18 20:09:51 -0600989 if (!dev_of_valid(dev))
Simon Glassff3e0772015-03-05 12:25:25 -0700990 return 0;
991
Simon Glassff3e0772015-03-05 12:25:25 -0700992 pplat = dev_get_parent_platdata(dev);
Bin Meng1f6b08b2018-08-03 01:14:36 -0700993
994 /* Extract vendor id and device id if available */
995 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
996
997 /* Extract the devfn from fdt_pci_addr */
Simon Glassbf501592017-05-18 20:09:51 -0600998 ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
999 &addr);
Simon Glassff3e0772015-03-05 12:25:25 -07001000 if (ret) {
1001 if (ret != -ENOENT)
1002 return -EINVAL;
1003 } else {
Bin Mengdce54dd2015-08-20 06:40:26 -07001004 pplat->devfn = addr.phys_hi & 0xff00;
Simon Glassff3e0772015-03-05 12:25:25 -07001005 }
1006
1007 return 0;
1008}
1009
Bin Meng4d8615c2015-07-19 00:20:04 +08001010static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
1011 uint offset, ulong *valuep,
1012 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -07001013{
1014 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -07001015
1016 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1017}
1018
Bin Meng4d8615c2015-07-19 00:20:04 +08001019static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1020 uint offset, ulong value,
1021 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -07001022{
1023 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -07001024
1025 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1026}
1027
Simon Glass76c3fbc2015-08-10 07:05:04 -06001028static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1029{
1030 struct udevice *dev;
1031 int ret = 0;
1032
1033 /*
1034 * Scan through all the PCI controllers. On x86 there will only be one
1035 * but that is not necessarily true on other hardware.
1036 */
1037 do {
1038 device_find_first_child(bus, &dev);
1039 if (dev) {
1040 *devp = dev;
1041 return 0;
1042 }
1043 ret = uclass_next_device(&bus);
1044 if (ret)
1045 return ret;
1046 } while (bus);
1047
1048 return 0;
1049}
1050
1051int pci_find_next_device(struct udevice **devp)
1052{
1053 struct udevice *child = *devp;
1054 struct udevice *bus = child->parent;
1055 int ret;
1056
1057 /* First try all the siblings */
1058 *devp = NULL;
1059 while (child) {
1060 device_find_next_child(&child);
1061 if (child) {
1062 *devp = child;
1063 return 0;
1064 }
1065 }
1066
1067 /* We ran out of siblings. Try the next bus */
1068 ret = uclass_next_device(&bus);
1069 if (ret)
1070 return ret;
1071
1072 return bus ? skip_to_next_device(bus, devp) : 0;
1073}
1074
1075int pci_find_first_device(struct udevice **devp)
1076{
1077 struct udevice *bus;
1078 int ret;
1079
1080 *devp = NULL;
1081 ret = uclass_first_device(UCLASS_PCI, &bus);
1082 if (ret)
1083 return ret;
1084
1085 return skip_to_next_device(bus, devp);
1086}
1087
Simon Glass9289db62015-11-19 20:26:59 -07001088ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1089{
1090 switch (size) {
1091 case PCI_SIZE_8:
1092 return (value >> ((offset & 3) * 8)) & 0xff;
1093 case PCI_SIZE_16:
1094 return (value >> ((offset & 2) * 8)) & 0xffff;
1095 default:
1096 return value;
1097 }
1098}
1099
1100ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1101 enum pci_size_t size)
1102{
1103 uint off_mask;
1104 uint val_mask, shift;
1105 ulong ldata, mask;
1106
1107 switch (size) {
1108 case PCI_SIZE_8:
1109 off_mask = 3;
1110 val_mask = 0xff;
1111 break;
1112 case PCI_SIZE_16:
1113 off_mask = 2;
1114 val_mask = 0xffff;
1115 break;
1116 default:
1117 return value;
1118 }
1119 shift = (offset & off_mask) * 8;
1120 ldata = (value & val_mask) << shift;
1121 mask = val_mask << shift;
1122 value = (old & ~mask) | ldata;
1123
1124 return value;
1125}
1126
Simon Glassf9260332015-11-19 20:27:01 -07001127int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1128 struct pci_region **memp, struct pci_region **prefp)
1129{
1130 struct udevice *bus = pci_get_controller(dev);
1131 struct pci_controller *hose = dev_get_uclass_priv(bus);
1132 int i;
1133
1134 *iop = NULL;
1135 *memp = NULL;
1136 *prefp = NULL;
1137 for (i = 0; i < hose->region_count; i++) {
1138 switch (hose->regions[i].flags) {
1139 case PCI_REGION_IO:
1140 if (!*iop || (*iop)->size < hose->regions[i].size)
1141 *iop = hose->regions + i;
1142 break;
1143 case PCI_REGION_MEM:
1144 if (!*memp || (*memp)->size < hose->regions[i].size)
1145 *memp = hose->regions + i;
1146 break;
1147 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1148 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1149 *prefp = hose->regions + i;
1150 break;
1151 }
1152 }
1153
1154 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1155}
1156
Simon Glassbab17cf2015-11-29 13:17:53 -07001157u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1158{
1159 u32 addr;
1160 int bar;
1161
1162 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1163 dm_pci_read_config32(dev, bar, &addr);
1164 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1165 return addr & PCI_BASE_ADDRESS_IO_MASK;
1166 else
1167 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1168}
1169
Simon Glass9d731c82016-01-18 20:19:15 -07001170void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1171{
1172 int bar;
1173
1174 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1175 dm_pci_write_config32(dev, bar, addr);
1176}
1177
Simon Glass21d1fe72015-11-29 13:18:03 -07001178static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1179 pci_addr_t bus_addr, unsigned long flags,
1180 unsigned long skip_mask, phys_addr_t *pa)
1181{
1182 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1183 struct pci_region *res;
1184 int i;
1185
Christian Gmeiner6f95d892018-06-10 06:25:06 -07001186 if (hose->region_count == 0) {
1187 *pa = bus_addr;
1188 return 0;
1189 }
1190
Simon Glass21d1fe72015-11-29 13:18:03 -07001191 for (i = 0; i < hose->region_count; i++) {
1192 res = &hose->regions[i];
1193
1194 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1195 continue;
1196
1197 if (res->flags & skip_mask)
1198 continue;
1199
1200 if (bus_addr >= res->bus_start &&
1201 (bus_addr - res->bus_start) < res->size) {
1202 *pa = (bus_addr - res->bus_start + res->phys_start);
1203 return 0;
1204 }
1205 }
1206
1207 return 1;
1208}
1209
1210phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1211 unsigned long flags)
1212{
1213 phys_addr_t phys_addr = 0;
1214 struct udevice *ctlr;
1215 int ret;
1216
1217 /* The root controller has the region information */
1218 ctlr = pci_get_controller(dev);
1219
1220 /*
1221 * if PCI_REGION_MEM is set we do a two pass search with preference
1222 * on matches that don't have PCI_REGION_SYS_MEMORY set
1223 */
1224 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1225 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1226 flags, PCI_REGION_SYS_MEMORY,
1227 &phys_addr);
1228 if (!ret)
1229 return phys_addr;
1230 }
1231
1232 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1233
1234 if (ret)
1235 puts("pci_hose_bus_to_phys: invalid physical address\n");
1236
1237 return phys_addr;
1238}
1239
1240int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1241 unsigned long flags, unsigned long skip_mask,
1242 pci_addr_t *ba)
1243{
1244 struct pci_region *res;
1245 struct udevice *ctlr;
1246 pci_addr_t bus_addr;
1247 int i;
1248 struct pci_controller *hose;
1249
1250 /* The root controller has the region information */
1251 ctlr = pci_get_controller(dev);
1252 hose = dev_get_uclass_priv(ctlr);
1253
Christian Gmeiner6f95d892018-06-10 06:25:06 -07001254 if (hose->region_count == 0) {
1255 *ba = phys_addr;
1256 return 0;
1257 }
1258
Simon Glass21d1fe72015-11-29 13:18:03 -07001259 for (i = 0; i < hose->region_count; i++) {
1260 res = &hose->regions[i];
1261
1262 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1263 continue;
1264
1265 if (res->flags & skip_mask)
1266 continue;
1267
1268 bus_addr = phys_addr - res->phys_start + res->bus_start;
1269
1270 if (bus_addr >= res->bus_start &&
1271 (bus_addr - res->bus_start) < res->size) {
1272 *ba = bus_addr;
1273 return 0;
1274 }
1275 }
1276
1277 return 1;
1278}
1279
1280pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1281 unsigned long flags)
1282{
1283 pci_addr_t bus_addr = 0;
1284 int ret;
1285
1286 /*
1287 * if PCI_REGION_MEM is set we do a two pass search with preference
1288 * on matches that don't have PCI_REGION_SYS_MEMORY set
1289 */
1290 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1291 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1292 PCI_REGION_SYS_MEMORY, &bus_addr);
1293 if (!ret)
1294 return bus_addr;
1295 }
1296
1297 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1298
1299 if (ret)
1300 puts("pci_hose_phys_to_bus: invalid physical address\n");
1301
1302 return bus_addr;
1303}
1304
1305void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1306{
1307 pci_addr_t pci_bus_addr;
1308 u32 bar_response;
1309
1310 /* read BAR address */
1311 dm_pci_read_config32(dev, bar, &bar_response);
1312 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1313
1314 /*
1315 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1316 * isn't actualy used on any platform because u-boot assumes a static
1317 * linear mapping. In the future, this could read the BAR size
1318 * and pass that as the size if needed.
1319 */
1320 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1321}
1322
Bin Mengdac01fd2018-08-03 01:14:52 -07001323int dm_pci_find_capability(struct udevice *dev, int cap)
1324{
1325 u16 status;
1326 u8 header_type;
1327 int ttl = PCI_FIND_CAP_TTL;
1328 u8 id;
1329 u16 ent;
1330 u8 pos;
1331
1332 dm_pci_read_config16(dev, PCI_STATUS, &status);
1333 if (!(status & PCI_STATUS_CAP_LIST))
1334 return 0;
1335
1336 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1337 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1338 pos = PCI_CB_CAPABILITY_LIST;
1339 else
1340 pos = PCI_CAPABILITY_LIST;
1341
1342 dm_pci_read_config8(dev, pos, &pos);
1343 while (ttl--) {
1344 if (pos < PCI_STD_HEADER_SIZEOF)
1345 break;
1346 pos &= ~3;
1347 dm_pci_read_config16(dev, pos, &ent);
1348
1349 id = ent & 0xff;
1350 if (id == 0xff)
1351 break;
1352 if (id == cap)
1353 return pos;
1354 pos = (ent >> 8);
1355 }
1356
1357 return 0;
1358}
1359
1360int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1361{
1362 u32 header;
1363 int ttl;
1364 int pos = PCI_CFG_SPACE_SIZE;
1365
1366 /* minimum 8 bytes per capability */
1367 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1368
1369 dm_pci_read_config32(dev, pos, &header);
1370 /*
1371 * If we have no capabilities, this is indicated by cap ID,
1372 * cap version and next pointer all being 0.
1373 */
1374 if (header == 0)
1375 return 0;
1376
1377 while (ttl--) {
1378 if (PCI_EXT_CAP_ID(header) == cap)
1379 return pos;
1380
1381 pos = PCI_EXT_CAP_NEXT(header);
1382 if (pos < PCI_CFG_SPACE_SIZE)
1383 break;
1384
1385 dm_pci_read_config32(dev, pos, &header);
1386 }
1387
1388 return 0;
1389}
1390
Simon Glassff3e0772015-03-05 12:25:25 -07001391UCLASS_DRIVER(pci) = {
1392 .id = UCLASS_PCI,
1393 .name = "pci",
Simon Glass2bb02e42015-05-10 21:08:06 -06001394 .flags = DM_UC_FLAG_SEQ_ALIAS,
Simon Glass91195482016-07-05 17:10:10 -06001395 .post_bind = dm_scan_fdt_dev,
Simon Glassff3e0772015-03-05 12:25:25 -07001396 .pre_probe = pci_uclass_pre_probe,
1397 .post_probe = pci_uclass_post_probe,
1398 .child_post_bind = pci_uclass_child_post_bind,
1399 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1400 .per_child_platdata_auto_alloc_size =
1401 sizeof(struct pci_child_platdata),
1402};
1403
1404static const struct dm_pci_ops pci_bridge_ops = {
1405 .read_config = pci_bridge_read_config,
1406 .write_config = pci_bridge_write_config,
1407};
1408
1409static const struct udevice_id pci_bridge_ids[] = {
1410 { .compatible = "pci-bridge" },
1411 { }
1412};
1413
1414U_BOOT_DRIVER(pci_bridge_drv) = {
1415 .name = "pci_bridge_drv",
1416 .id = UCLASS_PCI,
1417 .of_match = pci_bridge_ids,
1418 .ops = &pci_bridge_ops,
1419};
1420
1421UCLASS_DRIVER(pci_generic) = {
1422 .id = UCLASS_PCI_GENERIC,
1423 .name = "pci_generic",
1424};
1425
1426static const struct udevice_id pci_generic_ids[] = {
1427 { .compatible = "pci-generic" },
1428 { }
1429};
1430
1431U_BOOT_DRIVER(pci_generic_drv) = {
1432 .name = "pci_generic_drv",
1433 .id = UCLASS_PCI_GENERIC,
1434 .of_match = pci_generic_ids,
1435};
Stephen Warrene578b922016-01-26 11:10:11 -07001436
1437void pci_init(void)
1438{
1439 struct udevice *bus;
1440
1441 /*
1442 * Enumerate all known controller devices. Enumeration has the side-
1443 * effect of probing them, so PCIe devices will be enumerated too.
1444 */
1445 for (uclass_first_device(UCLASS_PCI, &bus);
1446 bus;
1447 uclass_next_device(&bus)) {
1448 ;
1449 }
1450}