wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000-2002 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <watchdog.h> |
| 10 | |
| 11 | #include <mpc8xx.h> |
| 12 | #include <commproc.h> |
| 13 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 14 | #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS) |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | #endif |
| 17 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 18 | #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ |
| 19 | defined(CONFIG_SYS_SMC_UCODE_PATCH) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 20 | void cpm_load_patch (volatile immap_t * immr); |
| 21 | #endif |
| 22 | |
| 23 | /* |
| 24 | * Breath some life into the CPU... |
| 25 | * |
| 26 | * Set up the memory map, |
| 27 | * initialize a bunch of registers, |
| 28 | * initialize the UPM's |
| 29 | */ |
| 30 | void cpu_init_f (volatile immap_t * immr) |
| 31 | { |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 32 | volatile memctl8xx_t *memctl = &immr->im_memctl; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 33 | # ifdef CONFIG_SYS_PLPRCR |
wdenk | 180d3f7 | 2004-01-04 16:28:35 +0000 | [diff] [blame] | 34 | ulong mfmask; |
wdenk | c178d3d | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 35 | # endif |
wdenk | 3bac351 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 36 | ulong reg; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 37 | |
| 38 | /* SYPCR - contains watchdog control (11-9) */ |
| 39 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 40 | immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 41 | |
| 42 | #if defined(CONFIG_WATCHDOG) |
| 43 | reset_8xx_watchdog (immr); |
| 44 | #endif /* CONFIG_WATCHDOG */ |
| 45 | |
| 46 | /* SIUMCR - contains debug pin configuration (11-6) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 48 | /* initialize timebase status and control register (11-26) */ |
| 49 | /* unlock TBSCRK */ |
| 50 | |
| 51 | immr->im_sitk.sitk_tbscrk = KAPWR_KEY; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 53 | |
| 54 | /* initialize the PIT (11-31) */ |
| 55 | |
| 56 | immr->im_sitk.sitk_piscrk = KAPWR_KEY; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 57 | immr->im_sit.sit_piscr = CONFIG_SYS_PISCR; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 58 | |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 59 | /* System integration timers. Don't change EBDF! (15-27) */ |
| 60 | |
| 61 | immr->im_clkrstk.cark_sccrk = KAPWR_KEY; |
| 62 | reg = immr->im_clkrst.car_sccr; |
| 63 | reg &= SCCR_MASK; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 64 | reg |= CONFIG_SYS_SCCR; |
wdenk | 1cb8e98 | 2003-03-06 21:55:29 +0000 | [diff] [blame] | 65 | immr->im_clkrst.car_sccr = reg; |
| 66 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 67 | /* PLL (CPU clock) settings (15-30) */ |
| 68 | |
| 69 | immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; |
| 70 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 71 | /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to |
| 72 | * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, |
| 73 | * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 74 | * field value. |
wdenk | 180d3f7 | 2004-01-04 16:28:35 +0000 | [diff] [blame] | 75 | * |
| 76 | * For newer (starting MPC866) chips PLPRCR layout is different. |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 77 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 78 | #ifdef CONFIG_SYS_PLPRCR |
wdenk | 180d3f7 | 2004-01-04 16:28:35 +0000 | [diff] [blame] | 79 | if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK) |
| 80 | mfmask = PLPRCR_MFACT_MSK; |
| 81 | else |
| 82 | mfmask = PLPRCR_MF_MSK; |
| 83 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 84 | if ((CONFIG_SYS_PLPRCR & mfmask) != 0) |
| 85 | reg = CONFIG_SYS_PLPRCR; /* reset control bits */ |
wdenk | 180d3f7 | 2004-01-04 16:28:35 +0000 | [diff] [blame] | 86 | else { |
| 87 | reg = immr->im_clkrst.car_plprcr; |
| 88 | reg &= mfmask; /* isolate MF-related fields */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | reg |= CONFIG_SYS_PLPRCR; /* reset control bits */ |
wdenk | 180d3f7 | 2004-01-04 16:28:35 +0000 | [diff] [blame] | 90 | } |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 91 | immr->im_clkrst.car_plprcr = reg; |
wdenk | c178d3d | 2004-01-24 20:25:54 +0000 | [diff] [blame] | 92 | #endif |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 93 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 94 | /* |
| 95 | * Memory Controller: |
| 96 | */ |
| 97 | |
| 98 | /* perform BR0 reset that MPC850 Rev. A can't guarantee */ |
| 99 | reg = memctl->memc_br0; |
| 100 | reg &= BR_PS_MSK; /* Clear everything except Port Size bits */ |
| 101 | reg |= BR_V; /* then add just the "Bank Valid" bit */ |
| 102 | memctl->memc_br0 = reg; |
| 103 | |
| 104 | /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at |
| 105 | * preliminary addresses - these have to be modified later |
| 106 | * when FLASH size has been determined |
| 107 | * |
| 108 | * Depending on the size of the memory region defined by |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the |
| 110 | * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't |
| 111 | * map CONFIG_SYS_MONITOR_BASE. |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 112 | * |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 113 | * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is |
| 114 | * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000. |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 115 | * |
| 116 | * If BR0 wasn't loaded with address base 0xff000000, then BR0's |
| 117 | * base address remains as 0x00000000. However, the address mask |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 118 | * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 119 | * into the Bank0. |
| 120 | * |
| 121 | * This is why CONFIG_IVMS8 and similar boards must load BR0 with |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 122 | * CONFIG_SYS_BR0_PRELIM in advance. |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 123 | * |
| 124 | * [Thanks to Michael Liao for this explanation. |
| 125 | * I owe him a free beer. - wd] |
| 126 | */ |
| 127 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 128 | #if defined(CONFIG_SYS_OR0_REMAP) |
| 129 | memctl->memc_or0 = CONFIG_SYS_OR0_REMAP; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 130 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 131 | #if defined(CONFIG_SYS_OR1_REMAP) |
| 132 | memctl->memc_or1 = CONFIG_SYS_OR1_REMAP; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 133 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 134 | #if defined(CONFIG_SYS_OR5_REMAP) |
| 135 | memctl->memc_or5 = CONFIG_SYS_OR5_REMAP; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 136 | #endif |
| 137 | |
| 138 | /* now restrict to preliminary range */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 139 | memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; |
| 140 | memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 141 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 142 | #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) |
| 143 | memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; |
| 144 | memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 145 | #endif |
| 146 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 147 | #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) |
| 148 | memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; |
| 149 | memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 150 | #endif |
| 151 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 152 | #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) |
| 153 | memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; |
| 154 | memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 155 | #endif |
| 156 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 157 | #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) |
| 158 | memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; |
| 159 | memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 160 | #endif |
| 161 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 162 | #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) |
| 163 | memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; |
| 164 | memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 165 | #endif |
| 166 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 167 | #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) |
| 168 | memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM; |
| 169 | memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 170 | #endif |
| 171 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) |
| 173 | memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM; |
| 174 | memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 175 | #endif |
| 176 | |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 177 | /* |
| 178 | * Reset CPM |
| 179 | */ |
| 180 | immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG; |
| 181 | do { /* Spin until command processed */ |
| 182 | __asm__ ("eieio"); |
| 183 | } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); |
| 184 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 185 | #ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */ |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 186 | /* write config value */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 187 | immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 188 | #endif |
| 189 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 190 | #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \ |
| 191 | defined(CONFIG_SYS_SMC_UCODE_PATCH) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 192 | cpm_load_patch (immr); /* load mpc8xx microcode patch */ |
| 193 | #endif |
| 194 | } |
| 195 | |
| 196 | /* |
| 197 | * initialize higher level parts of CPU like timers |
| 198 | */ |
| 199 | int cpu_init_r (void) |
| 200 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 201 | #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS) |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 202 | bd_t *bd = gd->bd; |
| 203 | volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base); |
| 204 | #endif |
| 205 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 206 | #ifdef CONFIG_SYS_RTCSC |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 207 | /* Unlock RTSC register */ |
| 208 | immr->im_sitk.sitk_rtcsck = KAPWR_KEY; |
| 209 | /* write config value */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 210 | immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 211 | #endif |
| 212 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 213 | #ifdef CONFIG_SYS_RMDS |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 214 | /* write config value */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 215 | immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS; |
wdenk | 4a9cbbe | 2002-08-27 09:48:53 +0000 | [diff] [blame] | 216 | #endif |
| 217 | return (0); |
| 218 | } |