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wdenk54387ac2003-10-08 22:45:44 +00001/*
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +01002 * Copyright (C) 2003-2005 Arabella Software Ltd.
wdenk54387ac2003-10-08 22:45:44 +00003 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
6 * This port was developed and tested on Revision C board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
31#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020032
33#define CONFIG_SYS_TEXT_BASE 0xFE000000
34
wdenk54387ac2003-10-08 22:45:44 +000035#define CPU_ID_STR "MPC8265"
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050036#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk54387ac2003-10-08 22:45:44 +000037
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +010038/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
wdenk54387ac2003-10-08 22:45:44 +000039#define CONFIG_ENV_OVERWRITE
40
41/*
42 * Select serial console configuration
43 *
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
46 * for SCC).
47 */
48#define CONFIG_CONS_ON_SMC /* Console is on SMC */
49#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50#undef CONFIG_CONS_NONE /* It's not on external UART */
51#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
52
53/*
54 * Select ethernet configuration
55 *
56 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
57 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
58 * SCC, 1-3 for FCC)
59 *
60 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
Jon Loeliger639221c2007-07-09 17:15:49 -050061 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
62 * must be unset.
wdenk54387ac2003-10-08 22:45:44 +000063 */
64#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
65#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
66#undef CONFIG_ETHER_NONE /* No external Ethernet */
67
68#ifdef CONFIG_ETHER_ON_FCC
69
70#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */
71
72#if (CONFIG_ETHER_INDEX == 2)
73/*
74 * - Rx clock is CLK13
75 * - Tx clock is CLK14
76 * - Select bus for bd/buffers (see 28-13)
77 * - Full duplex
78 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
80# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
81# define CONFIG_SYS_CPMFCR_RAMTYPE 0
82# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenk54387ac2003-10-08 22:45:44 +000083
wdenk659883c2004-10-09 23:33:42 +000084#endif /* CONFIG_ETHER_INDEX */
wdenk54387ac2003-10-08 22:45:44 +000085
86#define CONFIG_MII /* MII PHY management */
87#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
88/*
89 * GPIO pins used for bit-banged MII communications
90 */
wdenk659883c2004-10-09 23:33:42 +000091#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +020092#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
93 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
94#define MDC_DECLARE MDIO_DECLARE
95
wdenk659883c2004-10-09 23:33:42 +000096#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
97#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
98#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
wdenk54387ac2003-10-08 22:45:44 +000099
wdenk659883c2004-10-09 23:33:42 +0000100#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
101 else iop->pdat &= ~0x00400000
wdenk54387ac2003-10-08 22:45:44 +0000102
wdenk659883c2004-10-09 23:33:42 +0000103#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
104 else iop->pdat &= ~0x00200000
wdenk54387ac2003-10-08 22:45:44 +0000105
wdenk659883c2004-10-09 23:33:42 +0000106#define MIIDELAY udelay(1)
wdenk54387ac2003-10-08 22:45:44 +0000107
108#endif /* CONFIG_ETHER_ON_FCC */
109
110#ifndef CONFIG_8260_CLKIN
111#define CONFIG_8260_CLKIN 66666666 /* in Hz */
112#endif
113
wdenk659883c2004-10-09 23:33:42 +0000114#define CONFIG_BAUDRATE 38400
wdenk54387ac2003-10-08 22:45:44 +0000115
wdenk54387ac2003-10-08 22:45:44 +0000116
Jon Loeligera5562902007-07-08 15:31:57 -0500117/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500118 * BOOTP options
119 */
120#define CONFIG_BOOTP_BOOTFILESIZE
121#define CONFIG_BOOTP_BOOTPATH
122#define CONFIG_BOOTP_GATEWAY
123#define CONFIG_BOOTP_HOSTNAME
124
125
126/*
Jon Loeligera5562902007-07-08 15:31:57 -0500127 * Command line configuration.
128 */
129#include <config_cmd_default.h>
130
131#define CONFIG_CMD_ASKENV
132#define CONFIG_CMD_DHCP
133#define CONFIG_CMD_IMMAP
134#define CONFIG_CMD_MII
135#define CONFIG_CMD_PING
136
wdenk54387ac2003-10-08 22:45:44 +0000137
138#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
139#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */
140#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp"
141
Jon Loeligera5562902007-07-08 15:31:57 -0500142#if defined(CONFIG_CMD_KGDB)
wdenk54387ac2003-10-08 22:45:44 +0000143#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
144#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
145#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
146#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
147#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
148#endif
149
150#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
wdenk659883c2004-10-09 23:33:42 +0000151#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
wdenk54387ac2003-10-08 22:45:44 +0000152
153/*
154 * Miscellaneous configurable options
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_HUSH_PARSER
157#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
158#define CONFIG_SYS_LONGHELP /* undef to save memory */
159#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligera5562902007-07-08 15:31:57 -0500160#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk54387ac2003-10-08 22:45:44 +0000162#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk54387ac2003-10-08 22:45:44 +0000164#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
166#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
167#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk54387ac2003-10-08 22:45:44 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
170#define CONFIG_SYS_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */
wdenk54387ac2003-10-08 22:45:44 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
wdenk54387ac2003-10-08 22:45:44 +0000173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk54387ac2003-10-08 22:45:44 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk54387ac2003-10-08 22:45:44 +0000177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_SDRAM_BASE 0x00000000
179#define CONFIG_SYS_SDRAM_SIZE 64
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +0100180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_IMMR 0xF0000000
182#define CONFIG_SYS_LSDRAM_BASE 0xFC000000
183#define CONFIG_SYS_FLASH_BASE 0xFE000000
184#define CONFIG_SYS_BCSR 0xFEA00000
185#define CONFIG_SYS_EEPROM 0xFEB00000
186#define CONFIG_SYS_FLSIMM_BASE 0xFF000000
wdenk54387ac2003-10-08 22:45:44 +0000187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200189#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
191#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +0100192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLSIMM_BASE }
wdenk54387ac2003-10-08 22:45:44 +0000194
195#define BCSR_PCI_MODE 0x01
196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
198#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
199#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
200#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
201#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk54387ac2003-10-08 22:45:44 +0000202
203/* Hard reset configuration word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +0100205 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
206 HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\
207 HRCW_MODCK_H0111 \
208 ) /* 0x16848207 */
wdenk54387ac2003-10-08 22:45:44 +0000209/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_HRCW_SLAVE1 0
211#define CONFIG_SYS_HRCW_SLAVE2 0
212#define CONFIG_SYS_HRCW_SLAVE3 0
213#define CONFIG_SYS_HRCW_SLAVE4 0
214#define CONFIG_SYS_HRCW_SLAVE5 0
215#define CONFIG_SYS_HRCW_SLAVE6 0
216#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk54387ac2003-10-08 22:45:44 +0000217
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200218#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Peter Tyserd98b0522010-10-14 23:33:24 -0500219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
221#define CONFIG_SYS_RAMBOOT
wdenk54387ac2003-10-08 22:45:44 +0000222#endif
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
225#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
226#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk54387ac2003-10-08 22:45:44 +0000227
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200228#if !defined(CONFIG_ENV_IS_IN_FLASH) && !defined(CONFIG_ENV_IS_IN_NVRAM)
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200229#define CONFIG_ENV_IS_IN_NVRAM 1
wdenk54387ac2003-10-08 22:45:44 +0000230#endif
231
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200232#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200233# define CONFIG_ENV_SECT_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
wdenk54387ac2003-10-08 22:45:44 +0000235#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236# define CONFIG_ENV_ADDR (CONFIG_SYS_EEPROM + 0x400)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200237# define CONFIG_ENV_SIZE 0x1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238# define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
wdenk54387ac2003-10-08 22:45:44 +0000239#endif
240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeligera5562902007-07-08 15:31:57 -0500242#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk54387ac2003-10-08 22:45:44 +0000244#endif
245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_HID0_INIT (HID0_ICFI)
247#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
wdenk54387ac2003-10-08 22:45:44 +0000248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_HID2 0
wdenk54387ac2003-10-08 22:45:44 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_SIUMCR 0x42200000
252#define CONFIG_SYS_SYPCR 0xFFFFFFC3
253#define CONFIG_SYS_BCR 0x90000000
254#define CONFIG_SYS_SCCR SCCR_DFBRG01
wdenk54387ac2003-10-08 22:45:44 +0000255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_RMR RMR_CSRE
257#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
258#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
259#define CONFIG_SYS_RCCR 0
wdenk54387ac2003-10-08 22:45:44 +0000260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_PSDMR /* 0x834DA43B */0x014DA43A
262#define CONFIG_SYS_PSRT 0x0F/* 0x0C */
263#define CONFIG_SYS_LSDMR 0x0085A562
264#define CONFIG_SYS_LSRT 0x0F
265#define CONFIG_SYS_MPTPR 0x4000
wdenk54387ac2003-10-08 22:45:44 +0000266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PSDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
268#define CONFIG_SYS_PSDRAM_OR 0xFC0028C0
269#define CONFIG_SYS_LSDRAM_BR (CONFIG_SYS_LSDRAM_BASE | 0x00001861)
270#define CONFIG_SYS_LSDRAM_OR 0xFF803480
Wolfgang Denkaba9f1a2006-03-12 01:45:44 +0100271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00000801)
273#define CONFIG_SYS_OR0_PRELIM 0xFFE00856
274#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_EEPROM | 0x00000801)
275#define CONFIG_SYS_OR5_PRELIM 0xFFFF03F6
276#define CONFIG_SYS_BR6_PRELIM (CONFIG_SYS_FLSIMM_BASE | 0x00001801)
277#define CONFIG_SYS_OR6_PRELIM 0xFF000856
278#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
279#define CONFIG_SYS_OR7_PRELIM 0xFFFF83F6
wdenk54387ac2003-10-08 22:45:44 +0000280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
wdenk54387ac2003-10-08 22:45:44 +0000282
283#endif /* __CONFIG_H */