blob: 585efe12869c802014c9fd4ee1e368ca850f65e0 [file] [log] [blame]
wdenkc7de8292002-11-19 11:04:11 +00001#ifndef GLUE_H
2#define GLUE_H
3
4typedef unsigned int pci_dev_t;
5
6int mypci_find_device(int vendor, int product, int index);
7int mypci_bus(int device);
8int mypci_devfn(int device);
9unsigned long get_bar_size(pci_dev_t dev, int offset);
10
11u8 mypci_read_cfg_byte(int bus, int devfn, int offset);
12u16 mypci_read_cfg_word(int bus, int devfn, int offset);
13u32 mypci_read_cfg_long(int bus, int devfn, int offset);
14
15void mypci_write_cfg_byte(int bus, int devfn, int offset, u8 value);
16void mypci_write_cfg_word(int bus, int devfn, int offset, u16 value);
17void mypci_write_cfg_long(int bus, int devfn, int offset, u32 value);
18
19void _printf(const char *fmt, ...);
20char *_getenv(char *name);
21
22void *malloc(size_t size);
23void memset(void *addr, int value, size_t size);
24void memcpy(void *to, void *from, size_t numbytes);
25int strcmp(char *, char *);
26
27void enable_compatibility_hole(void);
28void disable_compatibility_hole(void);
29
30void map_rom(pci_dev_t dev, unsigned long address);
31void unmap_rom(pci_dev_t dev);
32int attempt_map_rom(pci_dev_t dev, void *copy_address);
33
34#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
35#define PCI_BASE_ADDRESS_SPACE_IO 0x01
36#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
37#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
38
39#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
40#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
41#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
42#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
43#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
44#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
45#define PCI_BUS(d) (((d) >> 16) & 0xff)
46#define PCI_DEV(d) (((d) >> 11) & 0x1f)
47#define PCI_FUNC(d) (((d) >> 8) & 0x7)
48#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
49
50#define PCI_ANY_ID (~0)
51#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
52#define PCI_ROM_ADDRESS_ENABLE 0x01
53
54#define OFF(addr) ((addr) & 0xFFFF)
55#define SEG(addr) (((addr)>>4) &0xF000)
56
57#endif