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wdenk1cb8e982003-03-06 21:55:29 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <s3c2410.h>
30#include <i2c.h>
31
32#include "vcma9.h"
33#include "../common/common_util.h"
34
Wolfgang Denkd87080b2006-03-31 18:32:53 +020035DECLARE_GLOBAL_DATA_PTR;
wdenk1cb8e982003-03-06 21:55:29 +000036
37#define FCLK_SPEED 1
38
39#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
40#define M_MDIV 0xC3
41#define M_PDIV 0x4
42#define M_SDIV 0x1
43#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
44#define M_MDIV 0xA1
45#define M_PDIV 0x3
46#define M_SDIV 0x1
47#endif
48
49#define USB_CLOCK 1
50
51#if USB_CLOCK==0
52#define U_M_MDIV 0xA1
53#define U_M_PDIV 0x3
54#define U_M_SDIV 0x1
55#elif USB_CLOCK==1
56#define U_M_MDIV 0x48
57#define U_M_PDIV 0x3
58#define U_M_SDIV 0x2
59#endif
60
61static inline void delay(unsigned long loops)
62{
63 __asm__ volatile ("1:\n"
64 "subs %0, %1, #1\n"
65 "bne 1b":"=r" (loops):"0" (loops));
66}
67
68/*
69 * Miscellaneous platform dependent initialisations
70 */
71
72int board_init(void)
73{
wdenk48b42612003-06-19 23:01:32 +000074 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
75 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
wdenk1cb8e982003-03-06 21:55:29 +000076
77 /* to reduce PLL lock time, adjust the LOCKTIME register */
wdenk48b42612003-06-19 23:01:32 +000078 clk_power->LOCKTIME = 0xFFFFFF;
wdenk1cb8e982003-03-06 21:55:29 +000079
80 /* configure MPLL */
wdenk48b42612003-06-19 23:01:32 +000081 clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
wdenk1cb8e982003-03-06 21:55:29 +000082
83 /* some delay between MPLL and UPLL */
84 delay (4000);
85
86 /* configure UPLL */
wdenk48b42612003-06-19 23:01:32 +000087 clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
wdenk1cb8e982003-03-06 21:55:29 +000088
89 /* some delay between MPLL and UPLL */
90 delay (8000);
91
92 /* set up the I/O ports */
wdenk48b42612003-06-19 23:01:32 +000093 gpio->GPACON = 0x007FFFFF;
94 gpio->GPBCON = 0x002AAAAA;
95 gpio->GPBUP = 0x000002BF;
96 gpio->GPCCON = 0xAAAAAAAA;
97 gpio->GPCUP = 0x0000FFFF;
98 gpio->GPDCON = 0xAAAAAAAA;
99 gpio->GPDUP = 0x0000FFFF;
100 gpio->GPECON = 0xAAAAAAAA;
101 gpio->GPEUP = 0x000037F7;
102 gpio->GPFCON = 0x00000000;
103 gpio->GPFUP = 0x00000000;
104 gpio->GPGCON = 0xFFEAFF5A;
105 gpio->GPGUP = 0x0000F0DC;
106 gpio->GPHCON = 0x0028AAAA;
107 gpio->GPHUP = 0x00000656;
wdenk1cb8e982003-03-06 21:55:29 +0000108
109 /* setup correct IRQ modes for NIC */
wdenk48b42612003-06-19 23:01:32 +0000110 gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
111
112 /* select USB port 2 to be host or device (fix to host for now) */
113 gpio->MISCCR |= 0x08;
wdenk1cb8e982003-03-06 21:55:29 +0000114
115 /* init serial */
116 gd->baudrate = CONFIG_BAUDRATE;
117 gd->have_console = 1;
118 serial_init();
119
120 /* arch number of VCMA9-Board */
wdenk731215e2004-10-10 18:41:04 +0000121 gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
wdenk1cb8e982003-03-06 21:55:29 +0000122
123 /* adress of boot parameters */
124 gd->bd->bi_boot_params = 0x30000100;
125
126 icache_enable();
127 dcache_enable();
128
129 return 0;
130}
131
wdenk1cb8e982003-03-06 21:55:29 +0000132/*
wdenk48b42612003-06-19 23:01:32 +0000133 * NAND flash initialization.
134 */
135#if (CONFIG_COMMANDS & CFG_CMD_NAND)
wdenka43278a2003-09-11 19:48:06 +0000136extern ulong
wdenk48b42612003-06-19 23:01:32 +0000137nand_probe(ulong physadr);
138
139
140static inline void NF_Reset(void)
141{
142 int i;
143
144 NF_SetCE(NFCE_LOW);
145 NF_Cmd(0xFF); /* reset command */
146 for(i = 0; i < 10; i++); /* tWB = 100ns. */
147 NF_WaitRB(); /* wait 200~500us; */
148 NF_SetCE(NFCE_HIGH);
149}
150
151
152static inline void NF_Init(void)
153{
wdenk531716e2003-09-13 19:01:12 +0000154#if 0 /* a little bit too optimistic */
wdenk48b42612003-06-19 23:01:32 +0000155#define TACLS 0
156#define TWRPH0 3
157#define TWRPH1 0
wdenk531716e2003-09-13 19:01:12 +0000158#else
159#define TACLS 0
160#define TWRPH0 4
161#define TWRPH1 2
162#endif
163
wdenk48b42612003-06-19 23:01:32 +0000164 NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
wdenk8bde7f72003-06-27 21:31:46 +0000165 /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
166 /* 1 1 1 1, 1 xxx, r xxx, r xxx */
167 /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
wdenk48b42612003-06-19 23:01:32 +0000168
169 NF_Reset();
170}
171
172void
173nand_init(void)
174{
175 S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
176
177 NF_Init();
wdenka43278a2003-09-11 19:48:06 +0000178#ifdef DEBUG
wdenk48b42612003-06-19 23:01:32 +0000179 printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
wdenka43278a2003-09-11 19:48:06 +0000180#endif
wdenk531716e2003-09-13 19:01:12 +0000181 printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
wdenk48b42612003-06-19 23:01:32 +0000182}
183#endif
184
185/*
wdenk1cb8e982003-03-06 21:55:29 +0000186 * Get some Board/PLD Info
187 */
188
wdenk531716e2003-09-13 19:01:12 +0000189static u8 Get_PLD_ID(void)
wdenk1cb8e982003-03-06 21:55:29 +0000190{
wdenk531716e2003-09-13 19:01:12 +0000191 VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
wdenk42d1f032003-10-15 23:53:47 +0000192
wdenk531716e2003-09-13 19:01:12 +0000193 return(pld->ID);
wdenk1cb8e982003-03-06 21:55:29 +0000194}
195
wdenk531716e2003-09-13 19:01:12 +0000196static u8 Get_PLD_BOARD(void)
wdenk1cb8e982003-03-06 21:55:29 +0000197{
wdenk531716e2003-09-13 19:01:12 +0000198 VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
wdenk42d1f032003-10-15 23:53:47 +0000199
wdenk531716e2003-09-13 19:01:12 +0000200 return(pld->BOARD);
wdenk1cb8e982003-03-06 21:55:29 +0000201}
202
wdenk531716e2003-09-13 19:01:12 +0000203static u8 Get_PLD_SDRAM(void)
204{
205 VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
wdenk42d1f032003-10-15 23:53:47 +0000206
wdenk531716e2003-09-13 19:01:12 +0000207 return(pld->SDRAM);
208}
209
210static u8 Get_PLD_Version(void)
wdenk1cb8e982003-03-06 21:55:29 +0000211{
212 return((Get_PLD_ID() >> 4) & 0x0F);
213}
214
wdenk531716e2003-09-13 19:01:12 +0000215static u8 Get_PLD_Revision(void)
wdenk1cb8e982003-03-06 21:55:29 +0000216{
217 return(Get_PLD_ID() & 0x0F);
218}
219
wdenk34b30492003-09-16 21:07:28 +0000220#if 0 /* not used */
wdenk1cb8e982003-03-06 21:55:29 +0000221static int Get_Board_Config(void)
222{
wdenk531716e2003-09-13 19:01:12 +0000223 u8 config = Get_PLD_BOARD() & 0x03;
wdenk1cb8e982003-03-06 21:55:29 +0000224
225 if (config == 3)
226 return 1;
227 else
228 return 0;
229}
wdenk34b30492003-09-16 21:07:28 +0000230#endif
wdenk1cb8e982003-03-06 21:55:29 +0000231
232static uchar Get_Board_PCB(void)
233{
234 return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
235}
236
wdenk531716e2003-09-13 19:01:12 +0000237static u8 Get_SDRAM_ChipNr(void)
238{
239 switch ((Get_PLD_SDRAM() >> 4) & 0x0F) {
240 case 0: return 4;
241 case 1: return 1;
242 case 2: return 2;
243 default: return 0;
244 }
245}
246
247static ulong Get_SDRAM_ChipSize(void)
248{
249 switch (Get_PLD_SDRAM() & 0x0F) {
250 case 0: return 16 * (1024*1024);
251 case 1: return 32 * (1024*1024);
252 case 2: return 8 * (1024*1024);
253 case 3: return 8 * (1024*1024);
254 default: return 0;
wdenk42d1f032003-10-15 23:53:47 +0000255 }
wdenk531716e2003-09-13 19:01:12 +0000256}
257static const char * Get_SDRAM_ChipGeom(void)
258{
259 switch (Get_PLD_SDRAM() & 0x0F) {
260 case 0: return "4Mx8x4";
261 case 1: return "8Mx8x4";
262 case 2: return "2Mx8x4";
263 case 3: return "4Mx8x2";
264 default: return "unknown";
265 }
266}
267
268static void Show_VCMA9_Info(char *board_name, char *serial)
269{
270 printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n",
271 board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision());
272 printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom());
273}
274
275int dram_init(void)
276{
wdenk531716e2003-09-13 19:01:12 +0000277 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
278 gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
279
280 return 0;
281}
282
wdenk1cb8e982003-03-06 21:55:29 +0000283/* ------------------------------------------------------------------------- */
284
285/*
286 * Check Board Identity:
287 */
288
289int checkboard(void)
290{
291 unsigned char s[50];
wdenk1cb8e982003-03-06 21:55:29 +0000292 int i;
293 backup_t *b = (backup_t *) s;
294
wdenk1cb8e982003-03-06 21:55:29 +0000295 i = getenv_r("serial#", s, 32);
296 if ((i < 0) || strncmp (s, "VCMA9", 5)) {
297 get_backup_values (b);
298 if (strncmp (b->signature, "MPL\0", 4) != 0) {
299 puts ("### No HW ID - assuming VCMA9");
300 } else {
301 b->serial_name[5] = 0;
wdenk531716e2003-09-13 19:01:12 +0000302 Show_VCMA9_Info(b->serial_name, &b->serial_name[6]);
wdenk1cb8e982003-03-06 21:55:29 +0000303 }
304 } else {
305 s[5] = 0;
wdenk531716e2003-09-13 19:01:12 +0000306 Show_VCMA9_Info(s, &s[6]);
wdenk1cb8e982003-03-06 21:55:29 +0000307 }
wdenk531716e2003-09-13 19:01:12 +0000308 /*printf("\n");*/
wdenk1cb8e982003-03-06 21:55:29 +0000309 return(0);
310}
311
312
wdenk33149b82003-05-23 11:38:58 +0000313extern void mem_test_reloc(void);
wdenk1cb8e982003-03-06 21:55:29 +0000314
315int last_stage_init(void)
316{
wdenk33149b82003-05-23 11:38:58 +0000317 mem_test_reloc();
wdenk531716e2003-09-13 19:01:12 +0000318 checkboard();
wdenk1cb8e982003-03-06 21:55:29 +0000319 show_stdio_dev();
320 check_env();
321 return 0;
322}
323
324/***************************************************************************
325 * some helping routines
326 */
wdenka2663ea2003-12-07 18:32:37 +0000327#if !CONFIG_USB_KEYBOARD
wdenk1cb8e982003-03-06 21:55:29 +0000328int overwrite_console(void)
329{
330 /* return TRUE if console should be overwritten */
331 return 0;
332}
wdenka2663ea2003-12-07 18:32:37 +0000333#endif
wdenk1cb8e982003-03-06 21:55:29 +0000334
335/************************************************************************
336* Print VCMA9 Info
337************************************************************************/
338void print_vcma9_info(void)
wdenk42d1f032003-10-15 23:53:47 +0000339{
wdenk531716e2003-09-13 19:01:12 +0000340 unsigned char s[50];
341 int i;
wdenk42d1f032003-10-15 23:53:47 +0000342
wdenk531716e2003-09-13 19:01:12 +0000343 if ((i = getenv_r("serial#", s, 32)) < 0) {
344 puts ("### No HW ID - assuming VCMA9");
345 printf("i %d", i*24);
346 } else {
347 s[5] = 0;
348 Show_VCMA9_Info(s, &s[6]);
349 }
wdenk1cb8e982003-03-06 21:55:29 +0000350}