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gerrit.cesnet.cz / github / trini / u-boot / d7dd4fffde5cbf6a047a904fe45a9b41b40054ea / . / board / mx1ads / lowlevel_init.S
blob: d1e472a933cc5e294536e59440a35f6522b97ec7 [file] [log] [blame]
wdenk2d24a3a2004-06-09 21:50:45 +0000[diff] [blame]1/*
wdenk400558b2005-04-02 23:52:25 +0000[diff] [blame]2 * board/mx1ads/lowlevel_init.S
wdenk49822e22004-06-19 21:19:10 +0000[diff] [blame]3 *
wdenk2d24a3a2004-06-09 21:50:45 +0000[diff] [blame]4 * (c) Copyright 2004
5 * Techware Information Technology, Inc.
6 * http://www.techware.com.tw/
7 *
8 * Ming-Len Wu <minglen_wu@techware.com.tw>
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]10 * SPDX-License-Identifier: GPL-2.0+
wdenk2d24a3a2004-06-09 21:50:45 +0000[diff] [blame]11 */
12
13#include <config.h>
14#include <version.h>
15
16#define SDCTL0 0x221000
17#define SDCTL1 0x221004
18
19
20_TEXT_BASE:
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200[diff] [blame]21 .word CONFIG_SYS_TEXT_BASE
wdenk2d24a3a2004-06-09 21:50:45 +0000[diff] [blame]22
wdenk400558b2005-04-02 23:52:25 +0000[diff] [blame]23.globl lowlevel_init
24lowlevel_init:
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]25/* memory controller init */
wdenk2d24a3a2004-06-09 21:50:45 +0000[diff] [blame]26
27 ldr r1, =SDCTL0
28
29/* Set Precharge Command */
30
31 ldr r3, =0x92120200
32/* ldr r3, =0x92120251
33*/
34 str r3, [r1]
35
36/* Issue Precharge All Commad */
37 ldr r3, =0x8200000
38 ldr r2, [r3]
wdenk49822e22004-06-19 21:19:10 +0000[diff] [blame]39
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]40/* Set AutoRefresh Command */
wdenk2d24a3a2004-06-09 21:50:45 +0000[diff] [blame]41 ldr r3, =0xA2120200
42 str r3, [r1]
43
44/* Issue AutoRefresh Command */
45 ldr r3, =0x8000000
46 ldr r2, [r3]
47 ldr r2, [r3]
48 ldr r2, [r3]
49 ldr r2, [r3]
50 ldr r2, [r3]
51 ldr r2, [r3]
52 ldr r2, [r3]
53 ldr r2, [r3]
wdenk49822e22004-06-19 21:19:10 +0000[diff] [blame]54
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]55/* Set Mode Register */
wdenk2d24a3a2004-06-09 21:50:45 +0000[diff] [blame]56 ldr r3, =0xB2120200
57 str r3, [r1]
wdenk49822e22004-06-19 21:19:10 +0000[diff] [blame]58
wdenk2d24a3a2004-06-09 21:50:45 +0000[diff] [blame]59/* Issue Mode Register Command */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]60 ldr r3, =0x08111800 /* Mode Register Value */
wdenk2d24a3a2004-06-09 21:50:45 +0000[diff] [blame]61 ldr r2, [r3]
62
63/* Set Normal Mode */
64 ldr r3, =0x82124200
65 str r3, [r1]
66
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]67/* everything is fine now */
wdenk2d24a3a2004-06-09 21:50:45 +0000[diff] [blame]68 mov pc, lr