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Parthiban Nallathambi10e959a2020-07-27 16:48:41 +02001/* SPDX-License-Identifier: GPL-2.0+
2 *
3 * Copyright (C) 2020 Linumiz
4 * Author: Parthiban Nallathambi <parthiban@linumiz.com>
5 */
6
7#ifndef __MYS_6ULX_H
8#define __MYS_6ULX_H
9
10#include <linux/sizes.h>
11#include "mx6_common.h"
12
13/* SPL options */
14#include "imx6_spl.h"
15
16#define CONFIG_SYS_FSL_USDHC_NUM 1
17
Parthiban Nallathambi10e959a2020-07-27 16:48:41 +020018/* Console configs */
19#define CONFIG_MXC_UART_BASE UART1_BASE
20
21/* MMC Configs */
22#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
23
Parthiban Nallathambi10e959a2020-07-27 16:48:41 +020024/* Physical Memory Map */
25#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
26#define PHYS_SDRAM_SIZE SZ_256M
27
28#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
29#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
30#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
31
32#define CONFIG_SYS_INIT_SP_OFFSET \
33 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
34#define CONFIG_SYS_INIT_SP_ADDR \
35 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
36
37/* NAND */
38#define CONFIG_SYS_MAX_NAND_DEVICE 1
39#define CONFIG_SYS_NAND_BASE 0x40000000
40
41/* USB Configs */
42#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
43#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
44#define CONFIG_MXC_USB_FLAGS 0
45#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
46
Parthiban Nallathambi10e959a2020-07-27 16:48:41 +020047#define CONFIG_EXTRA_ENV_SETTINGS \
48 "console=ttymxc0,115200n8\0" \
49 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
50 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
51 "fdt_addr_r=0x82000000\0" \
52 "fdt_high=0xffffffff\0" \
53 "initrd_high=0xffffffff\0" \
54 "kernel_addr_r=0x81000000\0" \
55 "pxefile_addr_r=0x87100000\0" \
56 "ramdisk_addr_r=0x82100000\0" \
57 "scriptaddr=0x87000000\0" \
58 BOOTENV
59
60#define BOOT_TARGET_DEVICES(func) \
61 func(MMC, mmc, 0) \
62 func(UBIFS, ubifs, 0) \
63 func(PXE, pxe, na) \
64 func(DHCP, dhcp, na)
65
66#include <config_distro_bootcmd.h>
67
68#endif /* __MYS_6ULX_H */