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Felipe Balbi1e4ad742014-11-10 14:02:44 -06001/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
3 *
4 * Author: Felipe Balbi <balbi@ti.com>
5 *
6 * Based on board/ti/dra7xx/evm.c
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12#include <palmas.h>
13#include <sata.h>
14#include <usb.h>
15#include <asm/omap_common.h>
16#include <asm/emif.h>
Lokesh Vutla334bbb32015-06-16 20:36:05 +053017#include <asm/gpio.h>
18#include <asm/arch/gpio.h>
Felipe Balbi1e4ad742014-11-10 14:02:44 -060019#include <asm/arch/clock.h>
Lokesh Vutlaf91e0c42015-06-04 16:42:41 +053020#include <asm/arch/dra7xx_iodelay.h>
Felipe Balbi1e4ad742014-11-10 14:02:44 -060021#include <asm/arch/sys_proto.h>
22#include <asm/arch/mmc_host_def.h>
23#include <asm/arch/sata.h>
24#include <asm/arch/gpio.h>
Kishon Vijay Abraham I7c379aa2015-08-19 14:13:19 +053025#include <asm/arch/omap.h>
Felipe Balbi1e4ad742014-11-10 14:02:44 -060026#include <environment.h>
Kishon Vijay Abraham I7c379aa2015-08-19 14:13:19 +053027#include <usb.h>
28#include <linux/usb/gadget.h>
29#include <dwc3-uboot.h>
30#include <dwc3-omap-uboot.h>
31#include <ti-usb-phy-uboot.h>
Felipe Balbi1e4ad742014-11-10 14:02:44 -060032
Kipisz, Steven212f96f2016-02-24 12:30:58 -060033#include "../common/board_detect.h"
Felipe Balbi1e4ad742014-11-10 14:02:44 -060034#include "mux_data.h"
35
Kipisz, Steven212f96f2016-02-24 12:30:58 -060036#define board_is_x15() board_ti_is("BBRDX15_")
37#define board_is_am572x_evm() board_ti_is("AM572PM_")
Steve Kipiszc020d352016-04-08 17:01:29 -050038#define board_is_am572x_idk() board_ti_is("AM572IDK")
Kipisz, Steven212f96f2016-02-24 12:30:58 -060039
Felipe Balbi1e4ad742014-11-10 14:02:44 -060040#ifdef CONFIG_DRIVER_TI_CPSW
41#include <cpsw.h>
42#endif
43
44DECLARE_GLOBAL_DATA_PTR;
45
Lokesh Vutla334bbb32015-06-16 20:36:05 +053046/* GPIO 7_11 */
47#define GPIO_DDR_VTT_EN 203
48
Kipisz, Steven212f96f2016-02-24 12:30:58 -060049#define SYSINFO_BOARD_NAME_MAX_LEN 45
50
Felipe Balbi1e4ad742014-11-10 14:02:44 -060051const struct omap_sysinfo sysinfo = {
Kipisz, Steven212f96f2016-02-24 12:30:58 -060052 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
Felipe Balbi1e4ad742014-11-10 14:02:44 -060053};
54
55static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
56 .dmm_lisa_map_3 = 0x80740300,
57 .is_ma_present = 0x1
58};
59
60void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
61{
62 *dmm_lisa_regs = &beagle_x15_lisa_regs;
63}
64
65static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
66 .sdram_config_init = 0x61851b32,
67 .sdram_config = 0x61851b32,
Lokesh Vutla11e2b042016-03-08 09:11:35 +053068 .sdram_config2 = 0x08000000,
Lokesh Vutla802bb572015-02-16 10:15:56 +053069 .ref_ctrl = 0x000040F1,
70 .ref_ctrl_final = 0x00001035,
Lokesh Vutla11e2b042016-03-08 09:11:35 +053071 .sdram_tim1 = 0xcccf36ab,
72 .sdram_tim2 = 0x308f7fda,
73 .sdram_tim3 = 0x409f88a8,
Lokesh Vutlaee4dc252015-06-03 16:57:47 +053074 .read_idle_ctrl = 0x00050000,
Lokesh Vutla11e2b042016-03-08 09:11:35 +053075 .zq_config = 0x5007190b,
Felipe Balbi1e4ad742014-11-10 14:02:44 -060076 .temp_alert_config = 0x00000000,
Lokesh Vutla496edff2015-06-03 14:43:22 +053077 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
78 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
Felipe Balbi1e4ad742014-11-10 14:02:44 -060079 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
Lokesh Vutla11e2b042016-03-08 09:11:35 +053080 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
81 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
82 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
83 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
Felipe Balbi1e4ad742014-11-10 14:02:44 -060084 .emif_rd_wr_lvl_rmp_win = 0x00000000,
Lokesh Vutla496edff2015-06-03 14:43:22 +053085 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
Felipe Balbi1e4ad742014-11-10 14:02:44 -060086 .emif_rd_wr_lvl_ctl = 0x00000000,
87 .emif_rd_wr_exec_thresh = 0x00000305
88};
89
Lokesh Vutla6213db72015-06-03 14:43:21 +053090/* Ext phy ctrl regs 1-35 */
Felipe Balbi1e4ad742014-11-10 14:02:44 -060091static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
Lokesh Vutla6213db72015-06-03 14:43:21 +053092 0x10040100,
Lokesh Vutla11e2b042016-03-08 09:11:35 +053093 0x00910091,
94 0x00950095,
95 0x009B009B,
96 0x009E009E,
97 0x00980098,
Felipe Balbi1e4ad742014-11-10 14:02:44 -060098 0x00340034,
Felipe Balbi1e4ad742014-11-10 14:02:44 -060099 0x00350035,
Lokesh Vutla11e2b042016-03-08 09:11:35 +0530100 0x00340034,
101 0x00310031,
102 0x00340034,
103 0x007F007F,
104 0x007F007F,
105 0x007F007F,
106 0x007F007F,
107 0x007F007F,
108 0x00480048,
109 0x004A004A,
110 0x00520052,
111 0x00550055,
112 0x00500050,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600113 0x00000000,
114 0x00600020,
Lokesh Vutla6213db72015-06-03 14:43:21 +0530115 0x40011080,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600116 0x08102040,
Lokesh Vutla11e2b042016-03-08 09:11:35 +0530117 0x0,
118 0x0,
119 0x0,
120 0x0,
121 0x0,
Lokesh Vutla496edff2015-06-03 14:43:22 +0530122 0x0,
123 0x0,
124 0x0,
125 0x0,
126 0x0
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600127};
128
129static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
130 .sdram_config_init = 0x61851b32,
131 .sdram_config = 0x61851b32,
Lokesh Vutla11e2b042016-03-08 09:11:35 +0530132 .sdram_config2 = 0x08000000,
Lokesh Vutla802bb572015-02-16 10:15:56 +0530133 .ref_ctrl = 0x000040F1,
134 .ref_ctrl_final = 0x00001035,
Schuyler Patton5f405e72016-04-08 16:53:44 -0500135 .sdram_tim1 = 0xcccf36b3,
Lokesh Vutla11e2b042016-03-08 09:11:35 +0530136 .sdram_tim2 = 0x308f7fda,
Schuyler Patton5f405e72016-04-08 16:53:44 -0500137 .sdram_tim3 = 0x407f88a8,
Lokesh Vutlaee4dc252015-06-03 16:57:47 +0530138 .read_idle_ctrl = 0x00050000,
Lokesh Vutla11e2b042016-03-08 09:11:35 +0530139 .zq_config = 0x5007190b,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600140 .temp_alert_config = 0x00000000,
Lokesh Vutla496edff2015-06-03 14:43:22 +0530141 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
142 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600143 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
Lokesh Vutla11e2b042016-03-08 09:11:35 +0530144 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
145 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
146 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
147 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600148 .emif_rd_wr_lvl_rmp_win = 0x00000000,
Lokesh Vutla496edff2015-06-03 14:43:22 +0530149 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600150 .emif_rd_wr_lvl_ctl = 0x00000000,
151 .emif_rd_wr_exec_thresh = 0x00000305
152};
153
154static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
Lokesh Vutla6213db72015-06-03 14:43:21 +0530155 0x10040100,
Lokesh Vutla11e2b042016-03-08 09:11:35 +0530156 0x00910091,
157 0x00950095,
158 0x009B009B,
159 0x009E009E,
160 0x00980098,
161 0x00340034,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600162 0x00350035,
Lokesh Vutla11e2b042016-03-08 09:11:35 +0530163 0x00340034,
164 0x00310031,
165 0x00340034,
166 0x007F007F,
167 0x007F007F,
168 0x007F007F,
169 0x007F007F,
170 0x007F007F,
171 0x00480048,
172 0x004A004A,
173 0x00520052,
174 0x00550055,
175 0x00500050,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600176 0x00000000,
177 0x00600020,
Lokesh Vutla6213db72015-06-03 14:43:21 +0530178 0x40011080,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600179 0x08102040,
Lokesh Vutla11e2b042016-03-08 09:11:35 +0530180 0x0,
181 0x0,
182 0x0,
183 0x0,
184 0x0,
Lokesh Vutla496edff2015-06-03 14:43:22 +0530185 0x0,
186 0x0,
187 0x0,
188 0x0,
189 0x0
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600190};
191
192void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
193{
194 switch (emif_nr) {
195 case 1:
196 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
197 break;
198 case 2:
199 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
200 break;
201 }
202}
203
204void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
205{
206 switch (emif_nr) {
207 case 1:
208 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
209 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
210 break;
211 case 2:
212 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
213 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
214 break;
215 }
216}
217
218struct vcores_data beagle_x15_volts = {
Anna, Sumane42523f2016-05-23 13:32:16 -0500219 .mpu.value = VDD_MPU_DRA7,
Anna, Suman27c95962016-05-23 13:32:15 -0500220 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600221 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
222 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
223 .mpu.pmic = &tps659038,
Nishanth Menon3708e782016-04-21 14:34:23 -0500224 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600225
Anna, Sumane42523f2016-05-23 13:32:16 -0500226 .eve.value = VDD_EVE_DRA7,
Anna, Suman27c95962016-05-23 13:32:15 -0500227 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600228 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
229 .eve.addr = TPS659038_REG_ADDR_SMPS45,
230 .eve.pmic = &tps659038,
Nishanth Menone52e3342016-04-21 14:34:25 -0500231 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600232
Anna, Sumane42523f2016-05-23 13:32:16 -0500233 .gpu.value = VDD_GPU_DRA7,
Anna, Suman27c95962016-05-23 13:32:15 -0500234 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600235 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
236 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
237 .gpu.pmic = &tps659038,
Nishanth Menone52e3342016-04-21 14:34:25 -0500238 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600239
Anna, Sumane42523f2016-05-23 13:32:16 -0500240 .core.value = VDD_CORE_DRA7,
Anna, Suman27c95962016-05-23 13:32:15 -0500241 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600242 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
243 .core.addr = TPS659038_REG_ADDR_SMPS6,
244 .core.pmic = &tps659038,
245
Anna, Sumane42523f2016-05-23 13:32:16 -0500246 .iva.value = VDD_IVA_DRA7,
Anna, Suman27c95962016-05-23 13:32:15 -0500247 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600248 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
249 .iva.addr = TPS659038_REG_ADDR_SMPS45,
250 .iva.pmic = &tps659038,
Nishanth Menone52e3342016-04-21 14:34:25 -0500251 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600252};
253
Keerthyd60198d2016-05-24 11:45:06 +0530254struct vcores_data am572x_idk_volts = {
255 .mpu.value = VDD_MPU_DRA7,
256 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
257 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
258 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
259 .mpu.pmic = &tps659038,
260 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
261
262 .eve.value = VDD_EVE_DRA7,
263 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
264 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
265 .eve.addr = TPS659038_REG_ADDR_SMPS45,
266 .eve.pmic = &tps659038,
267 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
268
269 .gpu.value = VDD_GPU_DRA7,
270 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
271 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
272 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
273 .gpu.pmic = &tps659038,
274 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
275
276 .core.value = VDD_CORE_DRA7,
277 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
278 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
279 .core.addr = TPS659038_REG_ADDR_SMPS7,
280 .core.pmic = &tps659038,
281
282 .iva.value = VDD_IVA_DRA7,
283 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
284 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
285 .iva.addr = TPS659038_REG_ADDR_SMPS8,
286 .iva.pmic = &tps659038,
287 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
288};
289
Kipisz, Steven212f96f2016-02-24 12:30:58 -0600290#ifdef CONFIG_SPL_BUILD
291/* No env to setup for SPL */
292static inline void setup_board_eeprom_env(void) { }
293
294/* Override function to read eeprom information */
295void do_board_detect(void)
296{
297 int rc;
298
299 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
300 CONFIG_EEPROM_CHIP_ADDRESS);
301 if (rc)
302 printf("ti_i2c_eeprom_init failed %d\n", rc);
303}
304
305#else /* CONFIG_SPL_BUILD */
306
307/* Override function to read eeprom information: actual i2c read done by SPL*/
308void do_board_detect(void)
309{
310 char *bname = NULL;
311 int rc;
312
313 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
314 CONFIG_EEPROM_CHIP_ADDRESS);
315 if (rc)
316 printf("ti_i2c_eeprom_init failed %d\n", rc);
317
318 if (board_is_x15())
319 bname = "BeagleBoard X15";
320 else if (board_is_am572x_evm())
321 bname = "AM572x EVM";
Steve Kipiszc020d352016-04-08 17:01:29 -0500322 else if (board_is_am572x_idk())
323 bname = "AM572x IDK";
Kipisz, Steven212f96f2016-02-24 12:30:58 -0600324
325 if (bname)
326 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
327 "Board: %s REV %s\n", bname, board_ti_get_rev());
328}
329
330static void setup_board_eeprom_env(void)
331{
332 char *name = "beagle_x15";
333 int rc;
334
335 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
336 CONFIG_EEPROM_CHIP_ADDRESS);
337 if (rc)
338 goto invalid_eeprom;
339
340 if (board_is_am572x_evm())
341 name = "am57xx_evm";
Steve Kipiszc020d352016-04-08 17:01:29 -0500342 else if (board_is_am572x_idk())
343 name = "am572x_idk";
Kipisz, Steven212f96f2016-02-24 12:30:58 -0600344 else
345 printf("Unidentified board claims %s in eeprom header\n",
346 board_ti_get_name());
347
348invalid_eeprom:
349 set_board_info_env(name);
350}
351
352#endif /* CONFIG_SPL_BUILD */
353
Keerthyd60198d2016-05-24 11:45:06 +0530354void vcores_init(void)
355{
356 if (board_is_am572x_idk())
357 *omap_vcores = &am572x_idk_volts;
358 else
359 *omap_vcores = &beagle_x15_volts;
360}
361
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600362void hw_data_init(void)
363{
364 *prcm = &dra7xx_prcm;
365 *dplls_data = &dra7xx_dplls;
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600366 *ctrl = &dra7xx_ctrl;
367}
368
369int board_init(void)
370{
371 gpmc_init();
372 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
373
374 return 0;
375}
376
377int board_late_init(void)
378{
Kipisz, Steven212f96f2016-02-24 12:30:58 -0600379 setup_board_eeprom_env();
380
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600381 /*
382 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
383 * This is the POWERHOLD-in-Low behavior.
384 */
385 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
386 return 0;
387}
388
Paul Kocialkowski3ef56e62016-02-27 19:18:56 +0100389void set_muxconf_regs(void)
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600390{
391 do_set_mux32((*ctrl)->control_padconf_core_base,
Lokesh Vutlaf91e0c42015-06-04 16:42:41 +0530392 early_padconf, ARRAY_SIZE(early_padconf));
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600393}
394
Lokesh Vutlaf91e0c42015-06-04 16:42:41 +0530395#ifdef CONFIG_IODELAY_RECALIBRATION
396void recalibrate_iodelay(void)
397{
Steve Kipiszc020d352016-04-08 17:01:29 -0500398 const struct pad_conf_entry *pconf;
399 const struct iodelay_cfg_entry *iod;
400 int pconf_sz, iod_sz;
401
402 if (board_is_am572x_idk()) {
403 pconf = core_padconf_array_essential_am572x_idk;
404 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
405 iod = iodelay_cfg_array_am572x_idk;
406 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
407 } else {
408 /* Common for X15/GPEVM */
409 pconf = core_padconf_array_essential_x15;
410 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
411 iod = iodelay_cfg_array_x15;
412 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
413 }
414
415 __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
Lokesh Vutlaf91e0c42015-06-04 16:42:41 +0530416}
417#endif
418
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600419#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
420int board_mmc_init(bd_t *bis)
421{
422 omap_mmc_init(0, 0, 0, -1, -1);
423 omap_mmc_init(1, 0, 0, -1, -1);
424 return 0;
425}
426#endif
427
428#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
429int spl_start_uboot(void)
430{
431 /* break into full u-boot on 'c' */
432 if (serial_tstc() && serial_getc() == 'c')
433 return 1;
434
435#ifdef CONFIG_SPL_ENV_SUPPORT
436 env_init();
437 env_relocate_spec();
438 if (getenv_yesno("boot_os") != 1)
439 return 1;
440#endif
441
442 return 0;
443}
444#endif
445
Kishon Vijay Abraham I7c379aa2015-08-19 14:13:19 +0530446#ifdef CONFIG_USB_DWC3
447static struct dwc3_device usb_otg_ss1 = {
448 .maximum_speed = USB_SPEED_SUPER,
449 .base = DRA7_USB_OTG_SS1_BASE,
450 .tx_fifo_resize = false,
451 .index = 0,
452};
453
454static struct dwc3_omap_device usb_otg_ss1_glue = {
455 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
456 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
457 .index = 0,
458};
459
460static struct ti_usb_phy_device usb_phy1_device = {
461 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
462 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
463 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
464 .index = 0,
465};
466
467static struct dwc3_device usb_otg_ss2 = {
468 .maximum_speed = USB_SPEED_HIGH,
469 .base = DRA7_USB_OTG_SS2_BASE,
470 .tx_fifo_resize = false,
471 .index = 1,
472};
473
474static struct dwc3_omap_device usb_otg_ss2_glue = {
475 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
476 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
477 .index = 1,
478};
479
480static struct ti_usb_phy_device usb_phy2_device = {
481 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
482 .index = 1,
483};
484
Kishon Vijay Abraham I7c379aa2015-08-19 14:13:19 +0530485int usb_gadget_handle_interrupts(int index)
486{
487 u32 status;
488
489 status = dwc3_omap_uboot_interrupt_status(index);
490 if (status)
491 dwc3_uboot_handle_interrupt(index);
492
493 return 0;
494}
Roger Quadros55efadd2016-05-23 17:37:48 +0300495#endif /* CONFIG_USB_DWC3 */
496
497#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
498int board_usb_init(int index, enum usb_init_type init)
499{
500 enable_usb_clocks(index);
501 switch (index) {
502 case 0:
503 if (init == USB_INIT_DEVICE) {
504 printf("port %d can't be used as device\n", index);
505 disable_usb_clocks(index);
506 return -EINVAL;
507 }
508 break;
509 case 1:
510 if (init == USB_INIT_DEVICE) {
511#ifdef CONFIG_USB_DWC3
512 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
513 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
514 ti_usb_phy_uboot_init(&usb_phy2_device);
515 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
516 dwc3_uboot_init(&usb_otg_ss2);
Kishon Vijay Abraham I7c379aa2015-08-19 14:13:19 +0530517#endif
Roger Quadros55efadd2016-05-23 17:37:48 +0300518 } else {
519 printf("port %d can't be used as host\n", index);
520 disable_usb_clocks(index);
521 return -EINVAL;
522 }
523
524 break;
525 default:
526 printf("Invalid Controller Index\n");
527 }
528
529 return 0;
530}
531
532int board_usb_cleanup(int index, enum usb_init_type init)
533{
534#ifdef CONFIG_USB_DWC3
535 switch (index) {
536 case 0:
537 case 1:
538 if (init == USB_INIT_DEVICE) {
539 ti_usb_phy_uboot_exit(index);
540 dwc3_uboot_exit(index);
541 dwc3_omap_uboot_exit(index);
542 }
543 break;
544 default:
545 printf("Invalid Controller Index\n");
546 }
547#endif
548 disable_usb_clocks(index);
549 return 0;
550}
551#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
Kishon Vijay Abraham I7c379aa2015-08-19 14:13:19 +0530552
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600553#ifdef CONFIG_DRIVER_TI_CPSW
554
555/* Delay value to add to calibrated value */
556#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
557#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
558#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
559#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
560#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
561#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
562#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
563#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
564#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
565#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
566
567static void cpsw_control(int enabled)
568{
569 /* VTP can be added here */
570}
571
572static struct cpsw_slave_data cpsw_slaves[] = {
573 {
574 .slave_reg_ofs = 0x208,
575 .sliver_reg_ofs = 0xd80,
576 .phy_addr = 1,
577 },
578 {
579 .slave_reg_ofs = 0x308,
580 .sliver_reg_ofs = 0xdc0,
581 .phy_addr = 2,
582 },
583};
584
585static struct cpsw_platform_data cpsw_data = {
586 .mdio_base = CPSW_MDIO_BASE,
587 .cpsw_base = CPSW_BASE,
588 .mdio_div = 0xff,
589 .channels = 8,
590 .cpdma_reg_ofs = 0x800,
591 .slaves = 1,
592 .slave_data = cpsw_slaves,
593 .ale_reg_ofs = 0xd00,
594 .ale_entries = 1024,
595 .host_port_reg_ofs = 0x108,
596 .hw_stats_reg_ofs = 0x900,
597 .bd_ram_ofs = 0x2000,
598 .mac_control = (1 << 5),
599 .control = cpsw_control,
600 .host_port_num = 0,
601 .version = CPSW_CTRL_VERSION_2,
602};
603
Roger Quadros92667e82016-03-18 13:18:12 +0200604static u64 mac_to_u64(u8 mac[6])
605{
606 int i;
607 u64 addr = 0;
608
609 for (i = 0; i < 6; i++) {
610 addr <<= 8;
611 addr |= mac[i];
612 }
613
614 return addr;
615}
616
617static void u64_to_mac(u64 addr, u8 mac[6])
618{
619 mac[5] = addr;
620 mac[4] = addr >> 8;
621 mac[3] = addr >> 16;
622 mac[2] = addr >> 24;
623 mac[1] = addr >> 32;
624 mac[0] = addr >> 40;
625}
626
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600627int board_eth_init(bd_t *bis)
628{
629 int ret;
630 uint8_t mac_addr[6];
631 uint32_t mac_hi, mac_lo;
632 uint32_t ctrl_val;
Roger Quadros92667e82016-03-18 13:18:12 +0200633 int i;
634 u64 mac1, mac2;
635 u8 mac_addr1[6], mac_addr2[6];
636 int num_macs;
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600637
638 /* try reading mac address from efuse */
639 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
640 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
641 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
642 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
643 mac_addr[2] = mac_hi & 0xFF;
644 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
645 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
646 mac_addr[5] = mac_lo & 0xFF;
647
648 if (!getenv("ethaddr")) {
649 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
650
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500651 if (is_valid_ethaddr(mac_addr))
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600652 eth_setenv_enetaddr("ethaddr", mac_addr);
653 }
654
655 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
656 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
657 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
658 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
659 mac_addr[2] = mac_hi & 0xFF;
660 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
661 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
662 mac_addr[5] = mac_lo & 0xFF;
663
664 if (!getenv("eth1addr")) {
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500665 if (is_valid_ethaddr(mac_addr))
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600666 eth_setenv_enetaddr("eth1addr", mac_addr);
667 }
668
669 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
670 ctrl_val |= 0x22;
671 writel(ctrl_val, (*ctrl)->control_core_control_io1);
672
Steve Kipiszc020d352016-04-08 17:01:29 -0500673 /* The phy address for the AM572x IDK are different than x15 */
674 if (board_is_am572x_idk()) {
675 cpsw_data.slave_data[0].phy_addr = 0;
676 cpsw_data.slave_data[1].phy_addr = 1;
677 }
678
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600679 ret = cpsw_register(&cpsw_data);
680 if (ret < 0)
681 printf("Error %d registering CPSW switch\n", ret);
682
Roger Quadros92667e82016-03-18 13:18:12 +0200683 /*
684 * Export any Ethernet MAC addresses from EEPROM.
685 * On AM57xx the 2 MAC addresses define the address range
686 */
687 board_ti_get_eth_mac_addr(0, mac_addr1);
688 board_ti_get_eth_mac_addr(1, mac_addr2);
689
690 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
691 mac1 = mac_to_u64(mac_addr1);
692 mac2 = mac_to_u64(mac_addr2);
693
694 /* must contain an address range */
695 num_macs = mac2 - mac1 + 1;
696 /* <= 50 to protect against user programming error */
697 if (num_macs > 0 && num_macs <= 50) {
698 for (i = 0; i < num_macs; i++) {
699 u64_to_mac(mac1 + i, mac_addr);
700 if (is_valid_ethaddr(mac_addr)) {
701 eth_setenv_enetaddr_by_index("eth",
702 i + 2,
703 mac_addr);
704 }
705 }
706 }
707 }
708
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600709 return ret;
710}
711#endif
Lokesh Vutla334bbb32015-06-16 20:36:05 +0530712
713#ifdef CONFIG_BOARD_EARLY_INIT_F
714/* VTT regulator enable */
715static inline void vtt_regulator_enable(void)
716{
717 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
718 return;
719
720 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
721 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
722}
723
724int board_early_init_f(void)
725{
726 vtt_regulator_enable();
727 return 0;
728}
729#endif
Daniel Allred62a09f02016-05-19 19:10:54 -0500730
731#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
732int ft_board_setup(void *blob, bd_t *bd)
733{
734 ft_cpu_setup(blob, bd);
735
736 return 0;
737}
738#endif