blob: f1a1432d869712cebd13654c72c14dc0f2bea073 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass1938f4a2013-03-11 06:49:53 +00002/*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
Simon Glass1938f4a2013-03-11 06:49:53 +000010 */
11
12#include <common.h>
Simon Glass24b852a2015-11-08 23:47:45 -070013#include <console.h>
Mario Six5d6c61a2018-08-06 10:23:41 +020014#include <cpu.h>
Simon Glassab7cd622014-07-23 06:55:04 -060015#include <dm.h>
Mario Six138181a2018-08-06 10:23:39 +020016#include <environment.h>
Simon Glass1938f4a2013-03-11 06:49:53 +000017#include <fdtdec.h>
Simon Glassf828bf22013-04-20 08:42:41 +000018#include <fs.h>
Simon Glasse4fef6c2013-03-11 14:30:42 +000019#include <i2c.h>
Simon Glass1938f4a2013-03-11 06:49:53 +000020#include <initcall.h>
Simon Glassfb5cf7f2015-02-27 22:06:36 -070021#include <malloc.h>
Joe Hershberger0eb25b62015-03-22 17:08:59 -050022#include <mapmem.h>
Simon Glassa733b062013-04-26 02:53:43 +000023#include <os.h>
Simon Glass1938f4a2013-03-11 06:49:53 +000024#include <post.h>
Simon Glasse47b2d62017-03-31 08:40:38 -060025#include <relocate.h>
Simon Glasse4fef6c2013-03-11 14:30:42 +000026#include <spi.h>
Jeroen Hofsteec5d40012014-06-23 23:20:19 +020027#include <status_led.h>
Mario Six23471ae2018-08-06 10:23:34 +020028#include <sysreset.h>
Simon Glass1057e6c2016-02-24 09:14:50 -070029#include <timer.h>
Simon Glass71c52db2013-06-11 11:14:42 -070030#include <trace.h>
Simon Glass5a541942016-01-18 19:52:21 -070031#include <video.h>
Simon Glasse4fef6c2013-03-11 14:30:42 +000032#include <watchdog.h>
Simon Glassb885d022017-05-17 08:23:01 -060033#ifdef CONFIG_MACH_TYPE
34#include <asm/mach-types.h>
35#endif
Simon Glass1fbf97d2017-03-31 08:40:39 -060036#if defined(CONFIG_MP) && defined(CONFIG_PPC)
37#include <asm/mp.h>
38#endif
Simon Glass1938f4a2013-03-11 06:49:53 +000039#include <asm/io.h>
40#include <asm/sections.h>
Simon Glassab7cd622014-07-23 06:55:04 -060041#include <dm/root.h>
Simon Glass056285f2017-03-31 08:40:35 -060042#include <linux/errno.h>
Simon Glass1938f4a2013-03-11 06:49:53 +000043
44/*
45 * Pointer to initial global data area
46 *
47 * Here we initialize it if needed.
48 */
49#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
50#undef XTRN_DECLARE_GLOBAL_DATA_PTR
51#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
Mario Six16ef1472018-01-15 11:10:02 +010052DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
Simon Glass1938f4a2013-03-11 06:49:53 +000053#else
54DECLARE_GLOBAL_DATA_PTR;
55#endif
56
57/*
Simon Glass4c509342015-04-28 20:25:03 -060058 * TODO(sjg@chromium.org): IMO this code should be
Simon Glass1938f4a2013-03-11 06:49:53 +000059 * refactored to a single function, something like:
60 *
61 * void led_set_state(enum led_colour_t colour, int on);
62 */
63/************************************************************************
64 * Coloured LED functionality
65 ************************************************************************
66 * May be supplied by boards if desired
67 */
Jeroen Hofsteec5d40012014-06-23 23:20:19 +020068__weak void coloured_LED_init(void) {}
69__weak void red_led_on(void) {}
70__weak void red_led_off(void) {}
71__weak void green_led_on(void) {}
72__weak void green_led_off(void) {}
73__weak void yellow_led_on(void) {}
74__weak void yellow_led_off(void) {}
75__weak void blue_led_on(void) {}
76__weak void blue_led_off(void) {}
Simon Glass1938f4a2013-03-11 06:49:53 +000077
78/*
79 * Why is gd allocated a register? Prior to reloc it might be better to
80 * just pass it around to each function in this file?
81 *
82 * After reloc one could argue that it is hardly used and doesn't need
83 * to be in a register. Or if it is it should perhaps hold pointers to all
84 * global data for all modules, so that post-reloc we can avoid the massive
85 * literal pool we get on ARM. Or perhaps just encourage each module to use
86 * a structure...
87 */
88
Sonic Zhangd54d7eb2014-07-17 19:01:34 +080089#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
Simon Glasse4fef6c2013-03-11 14:30:42 +000090static int init_func_watchdog_init(void)
91{
Tom Riniea3310e2017-03-14 11:08:10 -040092# if defined(CONFIG_HW_WATCHDOG) && \
93 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
Prasanthi Chellakumar1473f6a2018-10-09 11:46:40 -070094 defined(CONFIG_SH) || \
Anatolij Gustschin46d7a3b2016-06-13 14:24:23 +020095 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
Stefan Roese14a380a2015-03-10 08:04:36 +010096 defined(CONFIG_IMX_WATCHDOG))
Sonic Zhangd54d7eb2014-07-17 19:01:34 +080097 hw_watchdog_init();
Simon Glasse4fef6c2013-03-11 14:30:42 +000098 puts(" Watchdog enabled\n");
Anatolij Gustschinba169d92016-06-13 14:24:24 +020099# endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000100 WATCHDOG_RESET();
101
102 return 0;
103}
104
105int init_func_watchdog_reset(void)
106{
107 WATCHDOG_RESET();
108
109 return 0;
110}
111#endif /* CONFIG_WATCHDOG */
112
Jeroen Hofsteedd2a6cd2014-10-08 22:57:22 +0200113__weak void board_add_ram_info(int use_default)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000114{
115 /* please define platform specific board_add_ram_info() */
116}
117
Simon Glass1938f4a2013-03-11 06:49:53 +0000118static int init_baud_rate(void)
119{
Simon Glassbfebc8c2017-08-03 12:22:13 -0600120 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
Simon Glass1938f4a2013-03-11 06:49:53 +0000121 return 0;
122}
123
124static int display_text_info(void)
125{
Ben Stoltz9b217492015-07-31 09:31:37 -0600126#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
Daniel Schwierzeck9fdee7d2014-11-15 23:46:53 +0100127 ulong bss_start, bss_end, text_base;
Simon Glass1938f4a2013-03-11 06:49:53 +0000128
Simon Glass632efa72013-03-11 07:06:48 +0000129 bss_start = (ulong)&__bss_start;
130 bss_end = (ulong)&__bss_end;
Albert ARIBAUDb60eff32014-02-22 17:53:43 +0100131
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800132#ifdef CONFIG_SYS_TEXT_BASE
Daniel Schwierzeck9fdee7d2014-11-15 23:46:53 +0100133 text_base = CONFIG_SYS_TEXT_BASE;
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800134#else
Daniel Schwierzeck9fdee7d2014-11-15 23:46:53 +0100135 text_base = CONFIG_SYS_MONITOR_BASE;
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800136#endif
Daniel Schwierzeck9fdee7d2014-11-15 23:46:53 +0100137
138 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
Mario Six16ef1472018-01-15 11:10:02 +0100139 text_base, bss_start, bss_end);
Simon Glassa733b062013-04-26 02:53:43 +0000140#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000141
Simon Glass1938f4a2013-03-11 06:49:53 +0000142 return 0;
143}
144
Mario Six23471ae2018-08-06 10:23:34 +0200145#ifdef CONFIG_SYSRESET
146static int print_resetinfo(void)
147{
148 struct udevice *dev;
149 char status[256];
150 int ret;
151
152 ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
153 if (ret) {
154 debug("%s: No sysreset device found (error: %d)\n",
155 __func__, ret);
156 /* Not all boards have sysreset drivers available during early
157 * boot, so don't fail if one can't be found.
158 */
159 return 0;
160 }
161
162 if (!sysreset_get_status(dev, status, sizeof(status)))
163 printf("%s", status);
164
165 return 0;
166}
167#endif
168
Mario Six5d6c61a2018-08-06 10:23:41 +0200169#if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
170static int print_cpuinfo(void)
171{
172 struct udevice *dev;
173 char desc[512];
174 int ret;
175
176 ret = uclass_first_device_err(UCLASS_CPU, &dev);
177 if (ret) {
178 debug("%s: Could not get CPU device (err = %d)\n",
179 __func__, ret);
180 return ret;
181 }
182
183 ret = cpu_get_desc(dev, desc, sizeof(desc));
184 if (ret) {
185 debug("%s: Could not get CPU description (err = %d)\n",
186 dev->name, ret);
187 return ret;
188 }
189
Bin Mengecfe6632018-10-10 22:06:55 -0700190 printf("CPU: %s\n", desc);
Mario Six5d6c61a2018-08-06 10:23:41 +0200191
192 return 0;
193}
194#endif
195
Simon Glass1938f4a2013-03-11 06:49:53 +0000196static int announce_dram_init(void)
197{
198 puts("DRAM: ");
199 return 0;
200}
201
202static int show_dram_config(void)
203{
York Sunfa39ffe2014-05-02 17:28:05 -0700204 unsigned long long size;
Simon Glass1938f4a2013-03-11 06:49:53 +0000205
206#ifdef CONFIG_NR_DRAM_BANKS
207 int i;
208
209 debug("\nRAM Configuration:\n");
210 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
211 size += gd->bd->bi_dram[i].size;
Bin Meng715f5992015-08-06 01:31:20 -0700212 debug("Bank #%d: %llx ", i,
213 (unsigned long long)(gd->bd->bi_dram[i].start));
Simon Glass1938f4a2013-03-11 06:49:53 +0000214#ifdef DEBUG
215 print_size(gd->bd->bi_dram[i].size, "\n");
216#endif
217 }
218 debug("\nDRAM: ");
219#else
220 size = gd->ram_size;
221#endif
222
Simon Glasse4fef6c2013-03-11 14:30:42 +0000223 print_size(size, "");
224 board_add_ram_info(0);
225 putc('\n');
Simon Glass1938f4a2013-03-11 06:49:53 +0000226
227 return 0;
228}
229
Simon Glass76b00ac2017-03-31 08:40:32 -0600230__weak int dram_init_banksize(void)
Simon Glass1938f4a2013-03-11 06:49:53 +0000231{
232#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
233 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
234 gd->bd->bi_dram[0].size = get_effective_memsize();
235#endif
Simon Glass76b00ac2017-03-31 08:40:32 -0600236
237 return 0;
Simon Glass1938f4a2013-03-11 06:49:53 +0000238}
239
Simon Glass69153982017-05-12 21:09:56 -0600240#if defined(CONFIG_SYS_I2C)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000241static int init_func_i2c(void)
242{
243 puts("I2C: ");
trem815a76f2013-09-21 18:13:34 +0200244#ifdef CONFIG_SYS_I2C
245 i2c_init_all();
246#else
Simon Glasse4fef6c2013-03-11 14:30:42 +0000247 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
trem815a76f2013-09-21 18:13:34 +0200248#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000249 puts("ready\n");
250 return 0;
251}
252#endif
253
Rajesh Bhagat1fab98f2018-01-17 16:13:08 +0530254#if defined(CONFIG_VID)
255__weak int init_func_vid(void)
256{
257 return 0;
258}
259#endif
260
Simon Glasse4fef6c2013-03-11 14:30:42 +0000261#if defined(CONFIG_HARD_SPI)
262static int init_func_spi(void)
263{
264 puts("SPI: ");
265 spi_init();
266 puts("ready\n");
267 return 0;
268}
269#endif
270
Simon Glass1938f4a2013-03-11 06:49:53 +0000271static int setup_mon_len(void)
272{
Michal Simeke945f6d2014-05-08 16:08:44 +0200273#if defined(__ARM__) || defined(__MICROBLAZE__)
Albert ARIBAUDb60eff32014-02-22 17:53:43 +0100274 gd->mon_len = (ulong)&__bss_end - (ulong)_start;
Ben Stoltz9b217492015-07-31 09:31:37 -0600275#elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
Simon Glassa733b062013-04-26 02:53:43 +0000276 gd->mon_len = (ulong)&_end - (ulong)_init;
Tom Riniea3310e2017-03-14 11:08:10 -0400277#elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800278 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
Rick Chen068feb92017-12-26 13:55:58 +0800279#elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
Kun-Hua Huang2e88bb22015-08-24 14:52:35 +0800280 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
Simon Glassb0b35952016-05-14 18:49:28 -0600281#elif defined(CONFIG_SYS_MONITOR_BASE)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000282 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
283 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
Simon Glass632efa72013-03-11 07:06:48 +0000284#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000285 return 0;
286}
287
288__weak int arch_cpu_init(void)
289{
290 return 0;
291}
292
Paul Burton8ebf5062016-09-21 11:18:46 +0100293__weak int mach_cpu_init(void)
294{
295 return 0;
296}
297
Simon Glass1938f4a2013-03-11 06:49:53 +0000298/* Get the top of usable RAM */
299__weak ulong board_get_usable_ram_top(ulong total_size)
300{
Stephen Warren1e4d11a2014-12-23 10:34:49 -0700301#ifdef CONFIG_SYS_SDRAM_BASE
302 /*
Simon Glass4c509342015-04-28 20:25:03 -0600303 * Detect whether we have so much RAM that it goes past the end of our
Stephen Warren1e4d11a2014-12-23 10:34:49 -0700304 * 32-bit address space. If so, clip the usable RAM so it doesn't.
305 */
306 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
307 /*
308 * Will wrap back to top of 32-bit space when reservations
309 * are made.
310 */
311 return 0;
312#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000313 return gd->ram_top;
314}
315
316static int setup_dest_addr(void)
317{
318 debug("Monitor len: %08lX\n", gd->mon_len);
319 /*
320 * Ram is setup, size stored in gd !!
321 */
322 debug("Ram size: %08lX\n", (ulong)gd->ram_size);
York Sun36cc0de2017-03-06 09:02:28 -0800323#if defined(CONFIG_SYS_MEM_TOP_HIDE)
Simon Glass1938f4a2013-03-11 06:49:53 +0000324 /*
325 * Subtract specified amount of memory to hide so that it won't
326 * get "touched" at all by U-Boot. By fixing up gd->ram_size
327 * the Linux kernel should now get passed the now "corrected"
York Sun36cc0de2017-03-06 09:02:28 -0800328 * memory size and won't touch it either. This should work
329 * for arch/ppc and arch/powerpc. Only Linux board ports in
330 * arch/powerpc with bootwrapper support, that recalculate the
331 * memory size from the SDRAM controller setup will have to
332 * get fixed.
Simon Glass1938f4a2013-03-11 06:49:53 +0000333 */
York Sun36cc0de2017-03-06 09:02:28 -0800334 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
335#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000336#ifdef CONFIG_SYS_SDRAM_BASE
Siva Durga Prasad Paladugu1473b122018-07-16 15:56:10 +0530337 gd->ram_base = CONFIG_SYS_SDRAM_BASE;
Simon Glass1938f4a2013-03-11 06:49:53 +0000338#endif
Siva Durga Prasad Paladugu1473b122018-07-16 15:56:10 +0530339 gd->ram_top = gd->ram_base + get_effective_memsize();
Simon Glass1938f4a2013-03-11 06:49:53 +0000340 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000341 gd->relocaddr = gd->ram_top;
Simon Glass1938f4a2013-03-11 06:49:53 +0000342 debug("Ram top: %08lX\n", (ulong)gd->ram_top);
Gabriel Huauec3b4822014-09-03 13:57:54 -0700343#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
Simon Glasse4fef6c2013-03-11 14:30:42 +0000344 /*
345 * We need to make sure the location we intend to put secondary core
346 * boot code is reserved and not used by any part of u-boot
347 */
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000348 if (gd->relocaddr > determine_mp_bootpg(NULL)) {
349 gd->relocaddr = determine_mp_bootpg(NULL);
350 debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
Simon Glasse4fef6c2013-03-11 14:30:42 +0000351 }
352#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000353 return 0;
354}
355
Simon Glass1938f4a2013-03-11 06:49:53 +0000356#ifdef CONFIG_PRAM
357/* reserve protected RAM */
358static int reserve_pram(void)
359{
360 ulong reg;
361
Simon Glassbfebc8c2017-08-03 12:22:13 -0600362 reg = env_get_ulong("pram", 10, CONFIG_PRAM);
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000363 gd->relocaddr -= (reg << 10); /* size is in kB */
Simon Glass1938f4a2013-03-11 06:49:53 +0000364 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000365 gd->relocaddr);
Simon Glass1938f4a2013-03-11 06:49:53 +0000366 return 0;
367}
368#endif /* CONFIG_PRAM */
369
370/* Round memory pointer down to next 4 kB limit */
371static int reserve_round_4k(void)
372{
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000373 gd->relocaddr &= ~(4096 - 1);
Simon Glass1938f4a2013-03-11 06:49:53 +0000374 return 0;
375}
376
Simon Glass80d4bcd2017-03-31 08:40:29 -0600377#ifdef CONFIG_ARM
Siva Durga Prasad Paladugu60873f72017-07-13 19:01:08 +0530378__weak int reserve_mmu(void)
Simon Glass1938f4a2013-03-11 06:49:53 +0000379{
Simon Glass80d4bcd2017-03-31 08:40:29 -0600380#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
Simon Glass1938f4a2013-03-11 06:49:53 +0000381 /* reserve TLB table */
David Fengcce6be72013-12-14 11:47:36 +0800382 gd->arch.tlb_size = PGTABLE_SIZE;
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000383 gd->relocaddr -= gd->arch.tlb_size;
Simon Glass1938f4a2013-03-11 06:49:53 +0000384
385 /* round down to next 64 kB limit */
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000386 gd->relocaddr &= ~(0x10000 - 1);
Simon Glass1938f4a2013-03-11 06:49:53 +0000387
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000388 gd->arch.tlb_addr = gd->relocaddr;
Simon Glass1938f4a2013-03-11 06:49:53 +0000389 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
390 gd->arch.tlb_addr + gd->arch.tlb_size);
York Sun50e93b92016-06-24 16:46:19 -0700391
392#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
393 /*
394 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
395 * with location within secure ram.
396 */
397 gd->arch.tlb_allocated = gd->arch.tlb_addr;
398#endif
Simon Glass80d4bcd2017-03-31 08:40:29 -0600399#endif
York Sun50e93b92016-06-24 16:46:19 -0700400
Simon Glass1938f4a2013-03-11 06:49:53 +0000401 return 0;
402}
403#endif
404
Simon Glass5a541942016-01-18 19:52:21 -0700405static int reserve_video(void)
406{
Simon Glass0f079eb2017-03-31 08:40:30 -0600407#ifdef CONFIG_DM_VIDEO
Simon Glass5a541942016-01-18 19:52:21 -0700408 ulong addr;
409 int ret;
410
411 addr = gd->relocaddr;
412 ret = video_reserve(&addr);
413 if (ret)
414 return ret;
415 gd->relocaddr = addr;
Simon Glass0f079eb2017-03-31 08:40:30 -0600416#elif defined(CONFIG_LCD)
Simon Glass5a541942016-01-18 19:52:21 -0700417# ifdef CONFIG_FB_ADDR
Simon Glass1938f4a2013-03-11 06:49:53 +0000418 gd->fb_base = CONFIG_FB_ADDR;
Simon Glass5a541942016-01-18 19:52:21 -0700419# else
Simon Glass1938f4a2013-03-11 06:49:53 +0000420 /* reserve memory for LCD display (always full pages) */
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000421 gd->relocaddr = lcd_setmem(gd->relocaddr);
422 gd->fb_base = gd->relocaddr;
Simon Glass5a541942016-01-18 19:52:21 -0700423# endif /* CONFIG_FB_ADDR */
Simon Glass0f079eb2017-03-31 08:40:30 -0600424#elif defined(CONFIG_VIDEO) && \
Heiko Schocher5b8e76c2017-06-07 17:33:09 +0200425 (!defined(CONFIG_PPC)) && \
Simon Glass8703ef32016-01-18 19:52:20 -0700426 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
Tom Riniea3310e2017-03-14 11:08:10 -0400427 !defined(CONFIG_M68K)
Simon Glass8703ef32016-01-18 19:52:20 -0700428 /* reserve memory for video display (always full pages) */
429 gd->relocaddr = video_setmem(gd->relocaddr);
430 gd->fb_base = gd->relocaddr;
Simon Glass0f079eb2017-03-31 08:40:30 -0600431#endif
Simon Glass8703ef32016-01-18 19:52:20 -0700432
433 return 0;
434}
Simon Glass8703ef32016-01-18 19:52:20 -0700435
Simon Glass71c52db2013-06-11 11:14:42 -0700436static int reserve_trace(void)
437{
438#ifdef CONFIG_TRACE
439 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
440 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
441 debug("Reserving %dk for trace data at: %08lx\n",
442 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
443#endif
444
445 return 0;
446}
447
Simon Glass1938f4a2013-03-11 06:49:53 +0000448static int reserve_uboot(void)
449{
Alexey Brodkinff2b2ba2018-05-25 16:08:14 +0300450 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
451 /*
452 * reserve memory for U-Boot code, data & bss
453 * round down to next 4 kB limit
454 */
455 gd->relocaddr -= gd->mon_len;
456 gd->relocaddr &= ~(4096 - 1);
457 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
458 /* round down to next 64 kB limit so that IVPR stays aligned */
459 gd->relocaddr &= ~(65536 - 1);
460 #endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000461
Alexey Brodkinff2b2ba2018-05-25 16:08:14 +0300462 debug("Reserving %ldk for U-Boot at: %08lx\n",
463 gd->mon_len >> 10, gd->relocaddr);
464 }
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000465
466 gd->start_addr_sp = gd->relocaddr;
467
Simon Glass1938f4a2013-03-11 06:49:53 +0000468 return 0;
469}
470
471/* reserve memory for malloc() area */
472static int reserve_malloc(void)
473{
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000474 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
Simon Glass1938f4a2013-03-11 06:49:53 +0000475 debug("Reserving %dk for malloc() at: %08lx\n",
Mario Six16ef1472018-01-15 11:10:02 +0100476 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
Simon Glass1938f4a2013-03-11 06:49:53 +0000477 return 0;
478}
479
480/* (permanently) allocate a Board Info struct */
481static int reserve_board(void)
482{
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800483 if (!gd->bd) {
484 gd->start_addr_sp -= sizeof(bd_t);
485 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
486 memset(gd->bd, '\0', sizeof(bd_t));
487 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
488 sizeof(bd_t), gd->start_addr_sp);
489 }
Simon Glass1938f4a2013-03-11 06:49:53 +0000490 return 0;
491}
492
493static int setup_machine(void)
494{
495#ifdef CONFIG_MACH_TYPE
496 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
497#endif
498 return 0;
499}
500
501static int reserve_global_data(void)
502{
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000503 gd->start_addr_sp -= sizeof(gd_t);
504 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
Simon Glass1938f4a2013-03-11 06:49:53 +0000505 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
Mario Six16ef1472018-01-15 11:10:02 +0100506 sizeof(gd_t), gd->start_addr_sp);
Simon Glass1938f4a2013-03-11 06:49:53 +0000507 return 0;
508}
509
510static int reserve_fdt(void)
511{
Siva Durga Prasad Paladugue9acb9e2015-12-03 15:46:03 +0100512#ifndef CONFIG_OF_EMBED
Simon Glass1938f4a2013-03-11 06:49:53 +0000513 /*
Simon Glass4c509342015-04-28 20:25:03 -0600514 * If the device tree is sitting immediately above our image then we
Simon Glass1938f4a2013-03-11 06:49:53 +0000515 * must relocate it. If it is embedded in the data section, then it
516 * will be relocated with other data.
517 */
518 if (gd->fdt_blob) {
519 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
520
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000521 gd->start_addr_sp -= gd->fdt_size;
522 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
Simon Glassa733b062013-04-26 02:53:43 +0000523 debug("Reserving %lu Bytes for FDT at: %08lx\n",
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000524 gd->fdt_size, gd->start_addr_sp);
Simon Glass1938f4a2013-03-11 06:49:53 +0000525 }
Siva Durga Prasad Paladugue9acb9e2015-12-03 15:46:03 +0100526#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000527
528 return 0;
529}
530
Simon Glass25e7dc62017-05-22 05:05:30 -0600531static int reserve_bootstage(void)
532{
533#ifdef CONFIG_BOOTSTAGE
534 int size = bootstage_get_size();
535
536 gd->start_addr_sp -= size;
537 gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
538 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
539 gd->start_addr_sp);
540#endif
541
542 return 0;
543}
544
Patrick Delaunayd6f87712018-03-13 13:57:00 +0100545__weak int arch_reserve_stacks(void)
Andreas Bießmann68145d42015-02-06 23:06:45 +0100546{
547 return 0;
548}
549
Simon Glass1938f4a2013-03-11 06:49:53 +0000550static int reserve_stacks(void)
551{
Andreas Bießmann68145d42015-02-06 23:06:45 +0100552 /* make stack pointer 16-byte aligned */
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000553 gd->start_addr_sp -= 16;
554 gd->start_addr_sp &= ~0xf;
Simon Glass1938f4a2013-03-11 06:49:53 +0000555
556 /*
Simon Glass4c509342015-04-28 20:25:03 -0600557 * let the architecture-specific code tailor gd->start_addr_sp and
Andreas Bießmann68145d42015-02-06 23:06:45 +0100558 * gd->irq_sp
Simon Glass1938f4a2013-03-11 06:49:53 +0000559 */
Andreas Bießmann68145d42015-02-06 23:06:45 +0100560 return arch_reserve_stacks();
Simon Glass1938f4a2013-03-11 06:49:53 +0000561}
562
563static int display_new_sp(void)
564{
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000565 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
Simon Glass1938f4a2013-03-11 06:49:53 +0000566
567 return 0;
568}
569
Vladimir Zapolskiye2099d72016-11-28 00:15:24 +0200570#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
571 defined(CONFIG_SH)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000572static int setup_board_part1(void)
573{
574 bd_t *bd = gd->bd;
575
576 /*
577 * Save local variables to board info struct
578 */
Simon Glasse4fef6c2013-03-11 14:30:42 +0000579 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
580 bd->bi_memsize = gd->ram_size; /* size in bytes */
581
582#ifdef CONFIG_SYS_SRAM_BASE
583 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
584 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
585#endif
586
Heiko Schocher50258972017-06-07 17:33:11 +0200587#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000588 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
589#endif
Heiko Schocher064b55c2017-06-14 05:49:40 +0200590#if defined(CONFIG_M68K)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000591 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
592#endif
593#if defined(CONFIG_MPC83xx)
594 bd->bi_immrbar = CONFIG_SYS_IMMR;
595#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000596
597 return 0;
598}
Daniel Schwierzeckfb3db632015-11-01 17:36:13 +0100599#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000600
Daniel Schwierzeckfb3db632015-11-01 17:36:13 +0100601#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000602static int setup_board_part2(void)
603{
604 bd_t *bd = gd->bd;
605
606 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
607 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
608#if defined(CONFIG_CPM2)
609 bd->bi_cpmfreq = gd->arch.cpm_clk;
610 bd->bi_brgfreq = gd->arch.brg_clk;
611 bd->bi_sccfreq = gd->arch.scc_clk;
612 bd->bi_vco = gd->arch.vco_out;
613#endif /* CONFIG_CPM2 */
Alison Wang1313db42015-02-12 18:33:15 +0800614#if defined(CONFIG_M68K) && defined(CONFIG_PCI)
615 bd->bi_pcifreq = gd->pci_clk;
616#endif
617#if defined(CONFIG_EXTRA_CLOCK)
618 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
619 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
620 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
621#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000622
623 return 0;
624}
625#endif
626
Simon Glass1938f4a2013-03-11 06:49:53 +0000627#ifdef CONFIG_POST
628static int init_post(void)
629{
630 post_bootmode_init();
631 post_run(NULL, POST_ROM | post_bootmode_get(0));
632
633 return 0;
634}
635#endif
636
Simon Glass1938f4a2013-03-11 06:49:53 +0000637static int reloc_fdt(void)
638{
Siva Durga Prasad Paladugue9acb9e2015-12-03 15:46:03 +0100639#ifndef CONFIG_OF_EMBED
Simon Glassf05ad9b2015-08-04 12:33:39 -0600640 if (gd->flags & GD_FLG_SKIP_RELOC)
641 return 0;
Simon Glass1938f4a2013-03-11 06:49:53 +0000642 if (gd->new_fdt) {
643 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
644 gd->fdt_blob = gd->new_fdt;
645 }
Siva Durga Prasad Paladugue9acb9e2015-12-03 15:46:03 +0100646#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000647
648 return 0;
649}
650
Simon Glass25e7dc62017-05-22 05:05:30 -0600651static int reloc_bootstage(void)
652{
653#ifdef CONFIG_BOOTSTAGE
654 if (gd->flags & GD_FLG_SKIP_RELOC)
655 return 0;
656 if (gd->new_bootstage) {
657 int size = bootstage_get_size();
658
659 debug("Copying bootstage from %p to %p, size %x\n",
660 gd->bootstage, gd->new_bootstage, size);
661 memcpy(gd->new_bootstage, gd->bootstage, size);
662 gd->bootstage = gd->new_bootstage;
663 }
664#endif
665
666 return 0;
667}
668
Simon Glass1938f4a2013-03-11 06:49:53 +0000669static int setup_reloc(void)
670{
Simon Glassf05ad9b2015-08-04 12:33:39 -0600671 if (gd->flags & GD_FLG_SKIP_RELOC) {
672 debug("Skipping relocation due to flag\n");
673 return 0;
674 }
675
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800676#ifdef CONFIG_SYS_TEXT_BASE
Lothar Waßmann53207bf2017-06-08 10:18:25 +0200677#ifdef ARM
678 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
679#elif defined(CONFIG_M68K)
angelo@sysam.ite310b932015-02-12 01:40:17 +0100680 /*
681 * On all ColdFire arch cpu, monitor code starts always
682 * just after the default vector table location, so at 0x400
683 */
684 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
Lothar Waßmann53207bf2017-06-08 10:18:25 +0200685#else
686 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
angelo@sysam.ite310b932015-02-12 01:40:17 +0100687#endif
Sonic Zhangd54d7eb2014-07-17 19:01:34 +0800688#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000689 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
690
691 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
Simon Glassa733b062013-04-26 02:53:43 +0000692 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000693 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
694 gd->start_addr_sp);
Simon Glass1938f4a2013-03-11 06:49:53 +0000695
696 return 0;
697}
698
mario.six@gdsys.cc2a792752017-02-22 16:07:22 +0100699#ifdef CONFIG_OF_BOARD_FIXUP
700static int fix_fdt(void)
701{
702 return board_fix_fdt((void *)gd->fdt_blob);
703}
704#endif
705
Simon Glass1938f4a2013-03-11 06:49:53 +0000706/* ARM calls relocate_code from its crt0.S */
Simon Glass530f27e2017-01-16 07:03:49 -0700707#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
708 !CONFIG_IS_ENABLED(X86_64)
Simon Glass1938f4a2013-03-11 06:49:53 +0000709
710static int jump_to_copy(void)
711{
Simon Glassf05ad9b2015-08-04 12:33:39 -0600712 if (gd->flags & GD_FLG_SKIP_RELOC)
713 return 0;
Simon Glass48a33802013-03-05 14:39:52 +0000714 /*
715 * x86 is special, but in a nice way. It uses a trampoline which
716 * enables the dcache if possible.
717 *
718 * For now, other archs use relocate_code(), which is implemented
719 * similarly for all archs. When we do generic relocation, hopefully
720 * we can make all archs enable the dcache prior to relocation.
721 */
Alexey Brodkin3fb80162015-02-24 19:40:36 +0300722#if defined(CONFIG_X86) || defined(CONFIG_ARC)
Simon Glass48a33802013-03-05 14:39:52 +0000723 /*
724 * SDRAM and console are now initialised. The final stack can now
725 * be setup in SDRAM. Code execution will continue in Flash, but
726 * with the stack in SDRAM and Global Data in temporary memory
727 * (CPU cache)
728 */
Simon Glassf0c7d9c2015-08-10 20:44:32 -0600729 arch_setup_gd(gd->new_gd);
Simon Glass48a33802013-03-05 14:39:52 +0000730 board_init_f_r_trampoline(gd->start_addr_sp);
731#else
Masahiro Yamadaa0ba2792013-05-27 00:37:30 +0000732 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
Simon Glass48a33802013-03-05 14:39:52 +0000733#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000734
735 return 0;
736}
737#endif
738
739/* Record the board_init_f() bootstage (after arch_cpu_init()) */
Simon Glassb383d6c2017-05-22 05:05:25 -0600740static int initf_bootstage(void)
Simon Glass1938f4a2013-03-11 06:49:53 +0000741{
Simon Glassbaa7d342017-06-07 10:28:46 -0600742 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
743 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
Simon Glassb383d6c2017-05-22 05:05:25 -0600744 int ret;
745
Simon Glass824bb1b2017-05-22 05:05:35 -0600746 ret = bootstage_init(!from_spl);
Simon Glassb383d6c2017-05-22 05:05:25 -0600747 if (ret)
748 return ret;
Simon Glass824bb1b2017-05-22 05:05:35 -0600749 if (from_spl) {
750 const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
751 CONFIG_BOOTSTAGE_STASH_SIZE);
752
753 ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
754 if (ret && ret != -ENOENT) {
755 debug("Failed to unstash bootstage: err=%d\n", ret);
756 return ret;
757 }
758 }
Simon Glassb383d6c2017-05-22 05:05:25 -0600759
Simon Glass1938f4a2013-03-11 06:49:53 +0000760 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
761
762 return 0;
763}
764
Simon Glass9854a872015-11-08 23:47:48 -0700765static int initf_console_record(void)
766{
Andy Yanf1896c42017-07-24 17:43:34 +0800767#if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
Simon Glass9854a872015-11-08 23:47:48 -0700768 return console_record_init();
769#else
770 return 0;
771#endif
772}
773
Simon Glassab7cd622014-07-23 06:55:04 -0600774static int initf_dm(void)
775{
Andy Yanf1896c42017-07-24 17:43:34 +0800776#if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
Simon Glassab7cd622014-07-23 06:55:04 -0600777 int ret;
778
Simon Glass63c5bf42017-05-22 05:05:32 -0600779 bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
Simon Glassab7cd622014-07-23 06:55:04 -0600780 ret = dm_init_and_scan(true);
Simon Glass63c5bf42017-05-22 05:05:32 -0600781 bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
Simon Glassab7cd622014-07-23 06:55:04 -0600782 if (ret)
783 return ret;
784#endif
Simon Glass1057e6c2016-02-24 09:14:50 -0700785#ifdef CONFIG_TIMER_EARLY
786 ret = dm_timer_init();
787 if (ret)
788 return ret;
789#endif
Simon Glassab7cd622014-07-23 06:55:04 -0600790
791 return 0;
792}
793
Simon Glass146251f2015-01-19 22:16:12 -0700794/* Architecture-specific memory reservation */
795__weak int reserve_arch(void)
796{
797 return 0;
798}
799
Simon Glassd4c671c2015-03-05 12:25:16 -0700800__weak int arch_cpu_init_dm(void)
801{
802 return 0;
803}
804
Simon Glass4acff452017-01-16 07:03:50 -0700805static const init_fnc_t init_sequence_f[] = {
Simon Glass1938f4a2013-03-11 06:49:53 +0000806 setup_mon_len,
Simon Glassb45122f2015-02-27 22:06:34 -0700807#ifdef CONFIG_OF_CONTROL
Simon Glass08793612015-02-27 22:06:35 -0700808 fdtdec_setup,
Simon Glassb45122f2015-02-27 22:06:34 -0700809#endif
Kevin Hilmand2107182014-12-09 15:03:58 -0800810#ifdef CONFIG_TRACE
Simon Glass71c52db2013-06-11 11:14:42 -0700811 trace_early_init,
Kevin Hilmand2107182014-12-09 15:03:58 -0800812#endif
Simon Glass768e0f52014-11-10 18:00:18 -0700813 initf_malloc,
Simon Glassaf1bc0c2017-12-04 13:48:28 -0700814 log_init,
Simon Glass5ac44a52017-05-22 05:05:31 -0600815 initf_bootstage, /* uses its own timer, so does not need DM */
Simon Glass9854a872015-11-08 23:47:48 -0700816 initf_console_record,
Simon Glass671549e2017-03-28 10:27:18 -0600817#if defined(CONFIG_HAVE_FSP)
818 arch_fsp_init,
Bin Menga52a068e2015-08-20 06:40:18 -0700819#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000820 arch_cpu_init, /* basic arch cpu dependent setup */
Paul Burton8ebf5062016-09-21 11:18:46 +0100821 mach_cpu_init, /* SoC/machine dependent CPU setup */
Simon Glass3ea09532014-09-03 17:36:59 -0600822 initf_dm,
Simon Glassd4c671c2015-03-05 12:25:16 -0700823 arch_cpu_init_dm,
Simon Glass1938f4a2013-03-11 06:49:53 +0000824#if defined(CONFIG_BOARD_EARLY_INIT_F)
825 board_early_init_f,
826#endif
Simon Glass727e94a2017-03-28 10:27:26 -0600827#if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
Simon Glassc252c062017-03-28 10:27:19 -0600828 /* get CPU and bus clocks according to the environment variable */
Simon Glasse4fef6c2013-03-11 14:30:42 +0000829 get_clocks, /* get CPU and bus clocks (etc.) */
Simon Glass1793e782017-03-28 10:27:23 -0600830#endif
Angelo Dureghello0ce45282017-05-10 23:58:06 +0200831#if !defined(CONFIG_M68K)
Simon Glass1938f4a2013-03-11 06:49:53 +0000832 timer_init, /* initialize timer */
Angelo Dureghello0ce45282017-05-10 23:58:06 +0200833#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000834#if defined(CONFIG_BOARD_POSTCLK_INIT)
835 board_postclk_init,
836#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000837 env_init, /* initialize environment */
838 init_baud_rate, /* initialze baudrate settings */
839 serial_init, /* serial communications setup */
840 console_init_f, /* stage 1 init of console */
841 display_options, /* say that we are here */
842 display_text_info, /* show debugging info if required */
Angelo Dureghellob9153fe32017-08-20 00:01:55 +0200843#if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000844 checkcpu,
845#endif
Mario Six23471ae2018-08-06 10:23:34 +0200846#if defined(CONFIG_SYSRESET)
847 print_resetinfo,
848#endif
Simon Glasscc664002017-01-23 13:31:25 -0700849#if defined(CONFIG_DISPLAY_CPUINFO)
Simon Glass1938f4a2013-03-11 06:49:53 +0000850 print_cpuinfo, /* display cpu info (and speed) */
Simon Glasscc664002017-01-23 13:31:25 -0700851#endif
Cooper Jr., Franklinaf9e6ad2017-06-16 17:25:12 -0500852#if defined(CONFIG_DTB_RESELECT)
853 embedded_dtb_select,
854#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000855#if defined(CONFIG_DISPLAY_BOARDINFO)
Masahiro Yamada0365ffc2015-01-14 17:07:05 +0900856 show_board_info,
Simon Glass1938f4a2013-03-11 06:49:53 +0000857#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000858 INIT_FUNC_WATCHDOG_INIT
859#if defined(CONFIG_MISC_INIT_F)
860 misc_init_f,
861#endif
862 INIT_FUNC_WATCHDOG_RESET
Simon Glass69153982017-05-12 21:09:56 -0600863#if defined(CONFIG_SYS_I2C)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000864 init_func_i2c,
865#endif
Rajesh Bhagat1fab98f2018-01-17 16:13:08 +0530866#if defined(CONFIG_VID) && !defined(CONFIG_SPL)
867 init_func_vid,
868#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000869#if defined(CONFIG_HARD_SPI)
870 init_func_spi,
871#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000872 announce_dram_init,
Simon Glass1938f4a2013-03-11 06:49:53 +0000873 dram_init, /* configure available RAM banks */
Simon Glasse4fef6c2013-03-11 14:30:42 +0000874#ifdef CONFIG_POST
875 post_init_f,
876#endif
877 INIT_FUNC_WATCHDOG_RESET
878#if defined(CONFIG_SYS_DRAM_TEST)
879 testdram,
880#endif /* CONFIG_SYS_DRAM_TEST */
881 INIT_FUNC_WATCHDOG_RESET
882
Simon Glass1938f4a2013-03-11 06:49:53 +0000883#ifdef CONFIG_POST
884 init_post,
885#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000886 INIT_FUNC_WATCHDOG_RESET
Simon Glass1938f4a2013-03-11 06:49:53 +0000887 /*
888 * Now that we have DRAM mapped and working, we can
889 * relocate the code and continue running from DRAM.
890 *
891 * Reserve memory at end of RAM for (top down in that order):
892 * - area that won't get touched by U-Boot and Linux (optional)
893 * - kernel log buffer
894 * - protected RAM
895 * - LCD framebuffer
896 * - monitor code
897 * - board info struct
898 */
899 setup_dest_addr,
Simon Glass1938f4a2013-03-11 06:49:53 +0000900#ifdef CONFIG_PRAM
901 reserve_pram,
902#endif
903 reserve_round_4k,
Simon Glass80d4bcd2017-03-31 08:40:29 -0600904#ifdef CONFIG_ARM
Simon Glass1938f4a2013-03-11 06:49:53 +0000905 reserve_mmu,
906#endif
Simon Glass5a541942016-01-18 19:52:21 -0700907 reserve_video,
Simon Glass8703ef32016-01-18 19:52:20 -0700908 reserve_trace,
Simon Glass1938f4a2013-03-11 06:49:53 +0000909 reserve_uboot,
910 reserve_malloc,
911 reserve_board,
Simon Glass1938f4a2013-03-11 06:49:53 +0000912 setup_machine,
913 reserve_global_data,
914 reserve_fdt,
Simon Glass25e7dc62017-05-22 05:05:30 -0600915 reserve_bootstage,
Simon Glass146251f2015-01-19 22:16:12 -0700916 reserve_arch,
Simon Glass1938f4a2013-03-11 06:49:53 +0000917 reserve_stacks,
Simon Glass76b00ac2017-03-31 08:40:32 -0600918 dram_init_banksize,
Simon Glass1938f4a2013-03-11 06:49:53 +0000919 show_dram_config,
Vladimir Zapolskiye2099d72016-11-28 00:15:24 +0200920#if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
921 defined(CONFIG_SH)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000922 setup_board_part1,
Daniel Schwierzeckfb3db632015-11-01 17:36:13 +0100923#endif
924#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
Simon Glasse4fef6c2013-03-11 14:30:42 +0000925 INIT_FUNC_WATCHDOG_RESET
926 setup_board_part2,
927#endif
Simon Glass1938f4a2013-03-11 06:49:53 +0000928 display_new_sp,
mario.six@gdsys.cc2a792752017-02-22 16:07:22 +0100929#ifdef CONFIG_OF_BOARD_FIXUP
930 fix_fdt,
931#endif
Simon Glasse4fef6c2013-03-11 14:30:42 +0000932 INIT_FUNC_WATCHDOG_RESET
Simon Glass1938f4a2013-03-11 06:49:53 +0000933 reloc_fdt,
Simon Glass25e7dc62017-05-22 05:05:30 -0600934 reloc_bootstage,
Simon Glass1938f4a2013-03-11 06:49:53 +0000935 setup_reloc,
Alexey Brodkin3fb80162015-02-24 19:40:36 +0300936#if defined(CONFIG_X86) || defined(CONFIG_ARC)
Simon Glass313aef32015-01-01 16:18:09 -0700937 copy_uboot_to_ram,
Simon Glass313aef32015-01-01 16:18:09 -0700938 do_elf_reloc_fixups,
Simon Glass6bda55a2017-01-16 07:03:52 -0700939 clear_bss,
Simon Glass313aef32015-01-01 16:18:09 -0700940#endif
Chris Zankelde5e5ce2016-08-10 18:36:43 +0300941#if defined(CONFIG_XTENSA)
942 clear_bss,
943#endif
Simon Glass530f27e2017-01-16 07:03:49 -0700944#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
945 !CONFIG_IS_ENABLED(X86_64)
Simon Glass1938f4a2013-03-11 06:49:53 +0000946 jump_to_copy,
947#endif
948 NULL,
949};
950
951void board_init_f(ulong boot_flags)
952{
Simon Glass1938f4a2013-03-11 06:49:53 +0000953 gd->flags = boot_flags;
Alexey Brodkin9aed5a22013-11-27 22:32:40 +0400954 gd->have_console = 0;
Simon Glass1938f4a2013-03-11 06:49:53 +0000955
956 if (initcall_run_list(init_sequence_f))
957 hang();
958
Ben Stoltz9b217492015-07-31 09:31:37 -0600959#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
Alexey Brodkin264d2982015-12-16 19:24:10 +0300960 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
961 !defined(CONFIG_ARC)
Simon Glass1938f4a2013-03-11 06:49:53 +0000962 /* NOTREACHED - jump_to_copy() does not return */
963 hang();
964#endif
965}
966
Alexey Brodkin3fb80162015-02-24 19:40:36 +0300967#if defined(CONFIG_X86) || defined(CONFIG_ARC)
Simon Glass48a33802013-03-05 14:39:52 +0000968/*
969 * For now this code is only used on x86.
970 *
971 * init_sequence_f_r is the list of init functions which are run when
972 * U-Boot is executing from Flash with a semi-limited 'C' environment.
973 * The following limitations must be considered when implementing an
974 * '_f_r' function:
975 * - 'static' variables are read-only
976 * - Global Data (gd->xxx) is read/write
977 *
978 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
979 * supported). It _should_, if possible, copy global data to RAM and
980 * initialise the CPU caches (to speed up the relocation process)
981 *
982 * NOTE: At present only x86 uses this route, but it is intended that
983 * all archs will move to this when generic relocation is implemented.
984 */
Simon Glass4acff452017-01-16 07:03:50 -0700985static const init_fnc_t init_sequence_f_r[] = {
Simon Glass530f27e2017-01-16 07:03:49 -0700986#if !CONFIG_IS_ENABLED(X86_64)
Simon Glass48a33802013-03-05 14:39:52 +0000987 init_cache_f_r,
Simon Glass530f27e2017-01-16 07:03:49 -0700988#endif
Simon Glass48a33802013-03-05 14:39:52 +0000989
990 NULL,
991};
992
993void board_init_f_r(void)
994{
995 if (initcall_run_list(init_sequence_f_r))
996 hang();
997
998 /*
Simon Glasse4d6ab02016-03-11 22:06:51 -0700999 * The pre-relocation drivers may be using memory that has now gone
1000 * away. Mark serial as unavailable - this will fall back to the debug
1001 * UART if available.
Simon Glassaf1bc0c2017-12-04 13:48:28 -07001002 *
1003 * Do the same with log drivers since the memory may not be available.
Simon Glasse4d6ab02016-03-11 22:06:51 -07001004 */
Simon Glassaf1bc0c2017-12-04 13:48:28 -07001005 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
Simon Glass5ee94b42017-09-05 19:49:45 -06001006#ifdef CONFIG_TIMER
1007 gd->timer = NULL;
1008#endif
Simon Glasse4d6ab02016-03-11 22:06:51 -07001009
1010 /*
Simon Glass48a33802013-03-05 14:39:52 +00001011 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1012 * Transfer execution from Flash to RAM by calculating the address
1013 * of the in-RAM copy of board_init_r() and calling it
1014 */
Alexey Brodkin7bf9f202015-02-25 17:59:02 +03001015 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
Simon Glass48a33802013-03-05 14:39:52 +00001016
1017 /* NOTREACHED - board_init_r() does not return */
1018 hang();
1019}
Alexey Brodkin5bcd19a2015-03-24 11:12:47 +03001020#endif /* CONFIG_X86 */