Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2016 samtec automotive software & electronics gmbh |
| 4 | * |
| 5 | * Author: Christoph Fritz <chf.fritz@googlemail.com> |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <asm/arch/clock.h> |
| 9 | #include <asm/arch/crm_regs.h> |
| 10 | #include <asm/arch/iomux.h> |
| 11 | #include <asm/arch/imx-regs.h> |
| 12 | #include <asm/arch/mx6-pins.h> |
| 13 | #include <asm/arch/sys_proto.h> |
| 14 | #include <asm/gpio.h> |
Stefano Babic | 552a848 | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 15 | #include <asm/mach-imx/iomux-v3.h> |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 16 | #include <asm/io.h> |
Stefano Babic | 552a848 | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 17 | #include <asm/mach-imx/mxc_i2c.h> |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 18 | #include <linux/sizes.h> |
| 19 | #include <common.h> |
Alex Kiernan | 9925f1d | 2018-04-01 09:22:38 +0000 | [diff] [blame] | 20 | #include <environment.h> |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 21 | #include <fsl_esdhc.h> |
| 22 | #include <mmc.h> |
| 23 | #include <i2c.h> |
| 24 | #include <miiphy.h> |
| 25 | #include <netdev.h> |
| 26 | #include <power/pmic.h> |
| 27 | #include <power/pfuze100_pmic.h> |
| 28 | #include <usb.h> |
| 29 | #include <usb/ehci-ci.h> |
| 30 | #include <pwm.h> |
| 31 | #include <wait_bit.h> |
| 32 | |
| 33 | DECLARE_GLOBAL_DATA_PTR; |
| 34 | |
| 35 | #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ |
| 36 | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| 37 | PAD_CTL_SRE_FAST) |
| 38 | |
| 39 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \ |
| 40 | PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \ |
| 41 | PAD_CTL_SRE_FAST) |
| 42 | |
| 43 | #define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm |
| 44 | |
| 45 | #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \ |
| 46 | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \ |
| 47 | PAD_CTL_SRE_FAST) |
| 48 | |
| 49 | #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ |
| 50 | PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \ |
| 51 | PAD_CTL_DSE_40ohm) |
| 52 | |
| 53 | #define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ |
| 54 | PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST) |
| 55 | |
| 56 | #define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ |
| 57 | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \ |
| 58 | PAD_CTL_SRE_FAST) |
| 59 | |
Christoph Fritz | d578630 | 2019-05-17 21:19:31 +0200 | [diff] [blame^] | 60 | #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ |
| 61 | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm) |
| 62 | |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 63 | #define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ |
| 64 | PAD_CTL_PKE) |
| 65 | |
| 66 | int dram_init(void) |
| 67 | { |
| 68 | gd->ram_size = imx_ddr_size(); |
| 69 | |
| 70 | return 0; |
| 71 | } |
| 72 | |
| 73 | static iomux_v3_cfg_t const uart1_pads[] = { |
| 74 | MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 75 | MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 76 | }; |
| 77 | |
| 78 | static iomux_v3_cfg_t const usdhc2_pads[] = { |
| 79 | MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL), |
| 80 | MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 81 | MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 82 | MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 83 | MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 84 | MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 85 | MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL), |
| 86 | }; |
| 87 | |
| 88 | static iomux_v3_cfg_t const usdhc4_pads[] = { |
| 89 | MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL), |
| 90 | MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 91 | MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 92 | MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 93 | MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 94 | MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 95 | MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 96 | MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 97 | MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 98 | MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
Christoph Fritz | d578630 | 2019-05-17 21:19:31 +0200 | [diff] [blame^] | 99 | MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(USDHC_RESET_CTRL), |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | static iomux_v3_cfg_t const fec1_pads[] = { |
| 103 | MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 104 | MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 105 | MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| 106 | MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| 107 | MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 108 | MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 109 | MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), |
| 110 | MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 111 | MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) | |
| 112 | MUX_MODE_SION, |
| 113 | /* LAN8720 PHY Reset */ |
| 114 | MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 115 | }; |
| 116 | |
| 117 | static iomux_v3_cfg_t const pwm_led_pads[] = { |
| 118 | MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */ |
| 119 | MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */ |
| 120 | MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */ |
| 121 | }; |
| 122 | |
| 123 | static void setup_iomux_uart(void) |
| 124 | { |
| 125 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 126 | } |
| 127 | |
| 128 | #define PHY_RESET IMX_GPIO_NR(5, 9) |
| 129 | |
| 130 | int board_eth_init(bd_t *bis) |
| 131 | { |
| 132 | struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 133 | int ret; |
| 134 | unsigned char eth1addr[6]; |
| 135 | |
| 136 | /* just to get secound mac address */ |
| 137 | imx_get_mac_from_fuse(1, eth1addr); |
Simon Glass | 00caae6 | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 138 | if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr)) |
Simon Glass | fd1e959 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 139 | eth_env_set_enetaddr("eth1addr", eth1addr); |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 140 | |
| 141 | imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); |
| 142 | |
| 143 | /* |
| 144 | * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing |
| 145 | * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by |
| 146 | * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver. |
| 147 | */ |
| 148 | clrsetbits_le32(&iomuxc_regs->gpr[1], |
| 149 | IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK | |
| 150 | IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, |
| 151 | IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK | |
| 152 | IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); |
| 153 | |
| 154 | ret = enable_fec_anatop_clock(0, ENET_50MHZ); |
| 155 | if (ret) |
| 156 | goto eth_fail; |
| 157 | |
| 158 | /* reset phy */ |
| 159 | gpio_direction_output(PHY_RESET, 0); |
| 160 | mdelay(16); |
| 161 | gpio_set_value(PHY_RESET, 1); |
| 162 | mdelay(1); |
| 163 | |
| 164 | ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR, |
| 165 | IMX_FEC_BASE); |
| 166 | if (ret) |
| 167 | goto eth_fail; |
| 168 | |
| 169 | return ret; |
| 170 | |
| 171 | eth_fail: |
| 172 | printf("FEC MXC: %s:failed (%i)\n", __func__, ret); |
| 173 | gpio_set_value(PHY_RESET, 0); |
| 174 | return ret; |
| 175 | } |
| 176 | |
| 177 | #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) |
| 178 | /* I2C1 for PMIC */ |
| 179 | static struct i2c_pads_info i2c_pad_info1 = { |
| 180 | .scl = { |
| 181 | .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, |
| 182 | .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, |
| 183 | .gp = IMX_GPIO_NR(1, 0), |
| 184 | }, |
| 185 | .sda = { |
| 186 | .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, |
| 187 | .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, |
| 188 | .gp = IMX_GPIO_NR(1, 1), |
| 189 | }, |
| 190 | }; |
| 191 | |
| 192 | static struct pmic *pfuze_init(unsigned char i2cbus) |
| 193 | { |
| 194 | struct pmic *p; |
| 195 | int ret; |
| 196 | u32 reg; |
| 197 | |
| 198 | ret = power_pfuze100_init(i2cbus); |
| 199 | if (ret) |
| 200 | return NULL; |
| 201 | |
| 202 | p = pmic_get("PFUZE100"); |
| 203 | ret = pmic_probe(p); |
| 204 | if (ret) |
| 205 | return NULL; |
| 206 | |
| 207 | pmic_reg_read(p, PFUZE100_DEVICEID, ®); |
| 208 | printf("PMIC: PFUZE100 ID=0x%02x\n", reg); |
| 209 | |
| 210 | /* Set SW1AB stanby volage to 0.975V */ |
| 211 | pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); |
| 212 | reg &= ~SW1x_STBY_MASK; |
| 213 | reg |= SW1x_0_975V; |
| 214 | pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); |
| 215 | |
| 216 | /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ |
| 217 | pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); |
| 218 | reg &= ~SW1xCONF_DVSSPEED_MASK; |
| 219 | reg |= SW1xCONF_DVSSPEED_4US; |
| 220 | pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); |
| 221 | |
| 222 | /* Set SW1C standby voltage to 0.975V */ |
| 223 | pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); |
| 224 | reg &= ~SW1x_STBY_MASK; |
| 225 | reg |= SW1x_0_975V; |
| 226 | pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); |
| 227 | |
| 228 | /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ |
| 229 | pmic_reg_read(p, PFUZE100_SW1CCONF, ®); |
| 230 | reg &= ~SW1xCONF_DVSSPEED_MASK; |
| 231 | reg |= SW1xCONF_DVSSPEED_4US; |
| 232 | pmic_reg_write(p, PFUZE100_SW1CCONF, reg); |
| 233 | |
| 234 | return p; |
| 235 | } |
| 236 | |
| 237 | static int pfuze_mode_init(struct pmic *p, u32 mode) |
| 238 | { |
| 239 | unsigned char offset, i, switch_num; |
| 240 | u32 id; |
| 241 | int ret; |
| 242 | |
| 243 | pmic_reg_read(p, PFUZE100_DEVICEID, &id); |
| 244 | id = id & 0xf; |
| 245 | |
| 246 | if (id == 0) { |
| 247 | switch_num = 6; |
| 248 | offset = PFUZE100_SW1CMODE; |
| 249 | } else if (id == 1) { |
| 250 | switch_num = 4; |
| 251 | offset = PFUZE100_SW2MODE; |
| 252 | } else { |
| 253 | printf("Not supported, id=%d\n", id); |
| 254 | return -EINVAL; |
| 255 | } |
| 256 | |
| 257 | ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); |
| 258 | if (ret < 0) { |
| 259 | printf("Set SW1AB mode error!\n"); |
| 260 | return ret; |
| 261 | } |
| 262 | |
| 263 | for (i = 0; i < switch_num - 1; i++) { |
| 264 | ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); |
| 265 | if (ret < 0) { |
| 266 | printf("Set switch 0x%x mode error!\n", |
| 267 | offset + i * SWITCH_SIZE); |
| 268 | return ret; |
| 269 | } |
| 270 | } |
| 271 | |
| 272 | return ret; |
| 273 | } |
| 274 | |
| 275 | int power_init_board(void) |
| 276 | { |
| 277 | struct pmic *p; |
| 278 | int ret; |
| 279 | |
| 280 | p = pfuze_init(I2C_PMIC); |
| 281 | if (!p) |
| 282 | return -ENODEV; |
| 283 | |
| 284 | ret = pfuze_mode_init(p, APS_PFM); |
| 285 | if (ret < 0) |
| 286 | return ret; |
| 287 | |
| 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | #ifdef CONFIG_USB_EHCI_MX6 |
| 292 | static iomux_v3_cfg_t const usb_otg_pads[] = { |
| 293 | /* OGT1 */ |
| 294 | MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 295 | MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 296 | /* OTG2 */ |
| 297 | MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) |
| 298 | }; |
| 299 | |
| 300 | static void setup_iomux_usb(void) |
| 301 | { |
| 302 | imx_iomux_v3_setup_multiple_pads(usb_otg_pads, |
| 303 | ARRAY_SIZE(usb_otg_pads)); |
| 304 | } |
| 305 | |
| 306 | int board_usb_phy_mode(int port) |
| 307 | { |
| 308 | if (port == 1) |
| 309 | return USB_INIT_HOST; |
| 310 | else |
| 311 | return usb_phy_mode(port); |
| 312 | } |
| 313 | #endif |
| 314 | |
| 315 | #ifdef CONFIG_PWM_IMX |
| 316 | static int set_pwm_leds(void) |
| 317 | { |
| 318 | int ret; |
| 319 | |
| 320 | imx_iomux_v3_setup_multiple_pads(pwm_led_pads, |
| 321 | ARRAY_SIZE(pwm_led_pads)); |
| 322 | /* enable backlight PWM 2, green LED */ |
| 323 | ret = pwm_init(1, 0, 0); |
| 324 | if (ret) |
| 325 | goto error; |
| 326 | /* duty cycle 200ns, period: 8000ns */ |
| 327 | ret = pwm_config(1, 200, 8000); |
| 328 | if (ret) |
| 329 | goto error; |
| 330 | ret = pwm_enable(1); |
| 331 | if (ret) |
| 332 | goto error; |
| 333 | |
| 334 | /* enable backlight PWM 1, blue LED */ |
| 335 | ret = pwm_init(0, 0, 0); |
| 336 | if (ret) |
| 337 | goto error; |
| 338 | /* duty cycle 200ns, period: 8000ns */ |
| 339 | ret = pwm_config(0, 200, 8000); |
| 340 | if (ret) |
| 341 | goto error; |
| 342 | ret = pwm_enable(0); |
| 343 | if (ret) |
| 344 | goto error; |
| 345 | |
| 346 | /* enable backlight PWM 6, red LED */ |
| 347 | ret = pwm_init(5, 0, 0); |
| 348 | if (ret) |
| 349 | goto error; |
| 350 | /* duty cycle 200ns, period: 8000ns */ |
| 351 | ret = pwm_config(5, 200, 8000); |
| 352 | if (ret) |
| 353 | goto error; |
| 354 | ret = pwm_enable(5); |
| 355 | |
| 356 | error: |
| 357 | return ret; |
| 358 | } |
| 359 | #else |
| 360 | static int set_pwm_leds(void) |
| 361 | { |
| 362 | return 0; |
| 363 | } |
| 364 | #endif |
| 365 | |
| 366 | #define ADCx_HC0 0x00 |
| 367 | #define ADCx_HS 0x08 |
| 368 | #define ADCx_HS_C0 BIT(0) |
| 369 | #define ADCx_R0 0x0c |
| 370 | #define ADCx_CFG 0x14 |
| 371 | #define ADCx_CFG_SWMODE 0x308 |
| 372 | #define ADCx_GC 0x18 |
| 373 | #define ADCx_GC_CAL BIT(7) |
| 374 | |
| 375 | static int read_adc(u32 *val) |
| 376 | { |
| 377 | int ret; |
| 378 | void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE); |
| 379 | |
| 380 | /* use software mode */ |
| 381 | writel(ADCx_CFG_SWMODE, b + ADCx_CFG); |
| 382 | |
| 383 | /* start auto calibration */ |
| 384 | setbits_le32(b + ADCx_GC, ADCx_GC_CAL); |
Álvaro Fernández Rojas | 4826350 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 385 | ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0); |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 386 | if (ret) |
| 387 | goto adc_exit; |
| 388 | |
| 389 | /* start conversion */ |
| 390 | writel(0, b + ADCx_HC0); |
| 391 | |
| 392 | /* wait for conversion */ |
Álvaro Fernández Rojas | 4826350 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 393 | ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0); |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 394 | if (ret) |
| 395 | goto adc_exit; |
| 396 | |
| 397 | /* read result */ |
| 398 | *val = readl(b + ADCx_R0); |
| 399 | |
| 400 | adc_exit: |
| 401 | if (ret) |
| 402 | printf("ADC failure (ret=%i)\n", ret); |
| 403 | unmap_physmem(b, MAP_NOCACHE); |
| 404 | return ret; |
| 405 | } |
| 406 | |
| 407 | #define VAL_UPPER 2498 |
| 408 | #define VAL_LOWER 1550 |
| 409 | |
| 410 | static int set_pin_state(void) |
| 411 | { |
| 412 | u32 val; |
| 413 | int ret; |
| 414 | |
| 415 | ret = read_adc(&val); |
| 416 | if (ret) |
| 417 | return ret; |
| 418 | |
| 419 | if (val >= VAL_UPPER) |
Simon Glass | 382bee5 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 420 | env_set("pin_state", "connected"); |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 421 | else if (val < VAL_UPPER && val > VAL_LOWER) |
Simon Glass | 382bee5 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 422 | env_set("pin_state", "open"); |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 423 | else |
Simon Glass | 382bee5 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 424 | env_set("pin_state", "button"); |
Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 425 | |
| 426 | return ret; |
| 427 | } |
| 428 | |
| 429 | int board_late_init(void) |
| 430 | { |
| 431 | int ret; |
| 432 | |
| 433 | ret = set_pwm_leds(); |
| 434 | if (ret) |
| 435 | return ret; |
| 436 | |
| 437 | ret = set_pin_state(); |
| 438 | |
| 439 | return ret; |
| 440 | } |
| 441 | |
| 442 | int board_early_init_f(void) |
| 443 | { |
| 444 | setup_iomux_uart(); |
| 445 | |
| 446 | setup_iomux_usb(); |
| 447 | |
| 448 | return 0; |
| 449 | } |
| 450 | |
| 451 | static struct fsl_esdhc_cfg usdhc_cfg[2] = { |
| 452 | {USDHC4_BASE_ADDR, 0, 8}, |
| 453 | {USDHC2_BASE_ADDR, 0, 4}, |
| 454 | }; |
| 455 | |
| 456 | #define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28) |
| 457 | |
| 458 | int board_mmc_getcd(struct mmc *mmc) |
| 459 | { |
| 460 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 461 | |
| 462 | if (cfg->esdhc_base == USDHC4_BASE_ADDR) |
| 463 | return 1; |
| 464 | if (cfg->esdhc_base == USDHC2_BASE_ADDR) |
| 465 | return !gpio_get_value(USDHC2_CD_GPIO); |
| 466 | |
| 467 | return -EINVAL; |
| 468 | } |
| 469 | |
| 470 | int board_mmc_init(bd_t *bis) |
| 471 | { |
| 472 | int ret; |
| 473 | |
| 474 | /* |
| 475 | * According to the board_mmc_init() the following map is done: |
| 476 | * (U-Boot device node) (Physical Port) |
| 477 | * mmc0 USDHC4 |
| 478 | * mmc1 USDHC2 |
| 479 | */ |
| 480 | imx_iomux_v3_setup_multiple_pads( |
| 481 | usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| 482 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| 483 | |
| 484 | imx_iomux_v3_setup_multiple_pads( |
| 485 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| 486 | gpio_direction_input(USDHC2_CD_GPIO); |
| 487 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 488 | |
| 489 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
| 490 | if (ret) { |
| 491 | printf("Warning: failed to initialize USDHC4\n"); |
| 492 | return ret; |
| 493 | } |
| 494 | |
| 495 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]); |
| 496 | if (ret) { |
| 497 | printf("Warning: failed to initialize USDHC2\n"); |
| 498 | return ret; |
| 499 | } |
| 500 | |
| 501 | return 0; |
| 502 | } |
| 503 | |
| 504 | int board_init(void) |
| 505 | { |
| 506 | /* Address of boot parameters */ |
| 507 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 508 | |
| 509 | #ifdef CONFIG_SYS_I2C_MXC |
| 510 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); |
| 511 | #endif |
| 512 | |
| 513 | return 0; |
| 514 | } |
| 515 | |
| 516 | int checkboard(void) |
| 517 | { |
| 518 | puts("Board: VIN|ING 2000\n"); |
| 519 | |
| 520 | return 0; |
| 521 | } |