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Aubrey Li26bf7de2007-03-19 01:24:52 +08001/*
2 * U-boot - Configuration file for BF537 STAMP board
3 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF537_STAMP_H__
6#define __CONFIG_BF537_STAMP_H__
Aubrey Li26bf7de2007-03-19 01:24:52 +08007
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05009
Aubrey Li26bf7de2007-03-19 01:24:52 +080010
11/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040012 * Processor Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +080013 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf537-0.2
Mike Frysingercf6f4692008-06-01 09:09:48 -040015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 20
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
Mike Frysingerf82caac2008-12-08 16:16:11 -050039#define CONFIG_SCLK_DIV 4
Mike Frysingercf6f4692008-06-01 09:09:48 -040040
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL 0x306
49#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
50
51#define CONFIG_EBIU_AMGCTL_VAL 0xFF
52#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
53#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
54
Mike Frysinger6f5fd562009-01-21 20:47:12 -050055#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Mike Frysingercf6f4692008-06-01 09:09:48 -040056#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
57
Aubrey Li26bf7de2007-03-19 01:24:52 +080058
59/*
60 * Network Settings
61 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040062#ifndef __ADSPBF534__
63#define ADI_CMDS_NETWORK 1
64#define CONFIG_BFIN_MAC
Aubrey Li26bf7de2007-03-19 01:24:52 +080065#define CONFIG_NETCONSOLE 1
66#define CONFIG_NET_MULTI 1
Mike Frysingercf6f4692008-06-01 09:09:48 -040067#endif
68#define CONFIG_HOSTNAME bf537-stamp
69/* Uncomment next line to use fixed MAC address */
70/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
Jon Loeliger079a1362007-07-10 10:12:10 -050071
72
73/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040074 * Flash Settings
Jon Loeligerba2351f2007-07-04 22:31:49 -050075 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040076#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040078#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_FLASH_PROTECTION
80#define CONFIG_SYS_MAX_FLASH_BANKS 1
Mike Frysingercf6f4692008-06-01 09:09:48 -040081/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
82#define CONFIG_SYS_MAX_FLASH_SECT 71
Aubrey Li26bf7de2007-03-19 01:24:52 +080083
Aubrey Li26bf7de2007-03-19 01:24:52 +080084
Mike Frysingercf6f4692008-06-01 09:09:48 -040085/*
86 * SPI Settings
87 */
88#define CONFIG_BFIN_SPI
89#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysingerafac8b02009-06-14 22:29:35 -040090#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040091#define CONFIG_SPI_FLASH
Mike Frysingerf4532202010-09-19 16:26:55 -040092#define CONFIG_SPI_FLASH_ALL
Mike Frysingercf6f4692008-06-01 09:09:48 -040093
94
95/*
96 * Env Storage Settings
97 */
Mike Frysinger9171fc82008-03-30 15:46:13 -040098#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysingercf6f4692008-06-01 09:09:48 -040099#define CONFIG_ENV_IS_IN_SPI_FLASH
Vivi Libc43a8d2009-06-12 10:53:22 +0000100#define CONFIG_ENV_OFFSET 0x10000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200101#define CONFIG_ENV_SIZE 0x2000
Vivi Libc43a8d2009-06-12 10:53:22 +0000102#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400103#else
104#define CONFIG_ENV_IS_IN_FLASH
105#define CONFIG_ENV_OFFSET 0x4000
106#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
107#define CONFIG_ENV_SIZE 0x2000
108#define CONFIG_ENV_SECT_SIZE 0x2000
109#endif
110#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800111#define ENV_IS_EMBEDDED
Mike Frysingercf6f4692008-06-01 09:09:48 -0400112#else
Mike Frysinger76d82182009-07-21 22:17:36 -0400113#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysingercf6f4692008-06-01 09:09:48 -0400114#endif
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400115#ifdef ENV_IS_EMBEDDED
116/* WARNING - the following is hand-optimized to fit within
117 * the sector before the environment sector. If it throws
118 * an error during compilation remove an object here to get
119 * it linked after the configuration sector.
120 */
121# define LDS_BOARD_TEXT \
Mike Frysingerc70e7dd2010-11-19 19:28:56 -0500122 arch/blackfin/lib/libblackfin.o (.text*); \
123 arch/blackfin/cpu/libblackfin.o (.text*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400124 . = DEFINED(env_offset) ? env_offset : .; \
Mike Frysingerc70e7dd2010-11-19 19:28:56 -0500125 common/env_embedded.o (.text*);
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400126#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800127
Aubrey Li26bf7de2007-03-19 01:24:52 +0800128
129/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400130 * I2C Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +0800131 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400132#define CONFIG_BFIN_TWI_I2C 1
133#define CONFIG_HARD_I2C 1
Aubrey Li26bf7de2007-03-19 01:24:52 +0800134
Aubrey Li26bf7de2007-03-19 01:24:52 +0800135
136/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400137 * SPI_MMC Settings
Aubrey Li26bf7de2007-03-19 01:24:52 +0800138 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400139#define CONFIG_MMC
Mike Frysinger14dda9d2010-12-24 12:53:47 -0500140#define CONFIG_GENERIC_MMC
141#define CONFIG_MMC_SPI
Mike Frysingercf6f4692008-06-01 09:09:48 -0400142
143
144/*
145 * NAND Settings
146 */
Mike Frysingercd844232009-05-25 22:42:28 -0400147/* #define CONFIG_NAND_PLAT */
148#define CONFIG_SYS_NAND_BASE 0x20212000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_MAX_NAND_DEVICE 1
Aubrey Li26bf7de2007-03-19 01:24:52 +0800150
Mike Frysingercd844232009-05-25 22:42:28 -0400151#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
152#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
Mike Frysingercd844232009-05-25 22:42:28 -0400153#define BFIN_NAND_WRITE(addr, cmd) \
Mike Frysingercf6f4692008-06-01 09:09:48 -0400154 do { \
Mike Frysingercd844232009-05-25 22:42:28 -0400155 bfin_write8(addr, cmd); \
156 SSYNC(); \
Aubrey Li26bf7de2007-03-19 01:24:52 +0800157 } while (0)
158
Mike Frysingercd844232009-05-25 22:42:28 -0400159#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
160#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
Mike Frysinger67ceefa2010-07-05 04:55:05 -0400161#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
Aubrey Li26bf7de2007-03-19 01:24:52 +0800162
Aubrey Li26bf7de2007-03-19 01:24:52 +0800163
164/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400165 * CF-CARD IDE-HDD Support
Aubrey Li26bf7de2007-03-19 01:24:52 +0800166 */
Michael Hennerichaa7b2482009-06-18 09:12:50 +0000167
168/*
169 * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
170 * Strange address mapping Blackfin A13 connects to CF_A0
171 */
172
173/* #define CONFIG_BFIN_TRUE_IDE */
174
175/*
176 * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
177 * This should be the preferred mode
178 */
179
180/* #define CONFIG_BFIN_CF_IDE */
181
182/*
183 * Add IDE Disk Drive (HDD) support
184 * See example interface here:
185 * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
186 */
187
188/* #define CONFIG_BFIN_HDD_IDE */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800189
Mike Frysingercf6f4692008-06-01 09:09:48 -0400190#if defined(CONFIG_BFIN_CF_IDE) || \
191 defined(CONFIG_BFIN_HDD_IDE) || \
192 defined(CONFIG_BFIN_TRUE_IDE)
193# define CONFIG_BFIN_IDE 1
194# define CONFIG_CMD_IDE
195#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800196
Aubrey Li26bf7de2007-03-19 01:24:52 +0800197#if defined(CONFIG_BFIN_IDE)
198
199#define CONFIG_DOS_PARTITION 1
200/*
201 * IDE/ATA stuff
202 */
203#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
204#undef CONFIG_IDE_LED /* no led for ide supported */
205#undef CONFIG_IDE_RESET /* no reset for ide supported */
206
Mike Frysingercf6f4692008-06-01 09:09:48 -0400207#define CONFIG_SYS_IDE_MAXBUS 1
208#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
Aubrey Li26bf7de2007-03-19 01:24:52 +0800209
Mike Frysingercf6f4692008-06-01 09:09:48 -0400210#undef CONFIG_EBIU_AMBCTL1_VAL
211#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
Aubrey Li26bf7de2007-03-19 01:24:52 +0800212
213#define CONFIG_CF_ATASEL_DIS 0x20311800
214#define CONFIG_CF_ATASEL_ENA 0x20311802
215
216#if defined(CONFIG_BFIN_TRUE_IDE)
217/*
218 * Note that these settings aren't for the most part used in include/ata.h
219 * when all of the ATA registers are setup
220 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
222#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400223#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
224#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
225#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
Michael Hennerichaa7b2482009-06-18 09:12:50 +0000226#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800227
Mike Frysingercf6f4692008-06-01 09:09:48 -0400228#elif defined(CONFIG_BFIN_CF_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
230#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400231#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
232#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
233#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
Michael Hennerichaa7b2482009-06-18 09:12:50 +0000234#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800235
Mike Frysingercf6f4692008-06-01 09:09:48 -0400236#elif defined(CONFIG_BFIN_HDD_IDE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
238#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400239#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
240#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
241#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
Aubrey Li26bf7de2007-03-19 01:24:52 +0800243#undef CONFIG_SCLK_DIV
244#define CONFIG_SCLK_DIV 8
Mike Frysingercf6f4692008-06-01 09:09:48 -0400245#endif
Aubrey Li26bf7de2007-03-19 01:24:52 +0800246
Mike Frysingercf6f4692008-06-01 09:09:48 -0400247#endif
248
249
250/*
251 * Misc Settings
252 */
253#define CONFIG_MISC_INIT_R
254#define CONFIG_RTC_BFIN
255#define CONFIG_UART_CONSOLE 0
256
Mike Frysingercf6f4692008-06-01 09:09:48 -0400257/* Define if want to do post memory test */
258#undef CONFIG_POST
259#ifdef CONFIG_POST
260#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
261#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
262#endif
Michael Zaidman800eb092010-09-20 08:51:53 +0200263#define CONFIG_SYS_POST_WORD_ADDR 0xFF903FFC
Mike Frysingercf6f4692008-06-01 09:09:48 -0400264
Mike Frysinger216818c2010-01-21 23:29:18 -0500265/* These are for board tests */
266#if 0
267#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
268#define CONFIG_AUTOBOOT_KEYED
269#define CONFIG_AUTOBOOT_PROMPT \
270 "autoboot in %d seconds: press space to stop\n", bootdelay
271#define CONFIG_AUTOBOOT_STOP_STR " "
272#endif
273
Mike Frysingercf6f4692008-06-01 09:09:48 -0400274
275/*
276 * Pull in common ADI header for remaining command/environment setup
277 */
278#include <configs/bfin_adi_common.h>
Aubrey Li26bf7de2007-03-19 01:24:52 +0800279
Aubrey Li26bf7de2007-03-19 01:24:52 +0800280#endif