Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010-2014 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef _TEGRA_PINMUX_H_ |
| 9 | #define _TEGRA_PINMUX_H_ |
| 10 | |
| 11 | #include <asm/arch/tegra.h> |
| 12 | |
| 13 | /* The pullup/pulldown state of a pin group */ |
| 14 | enum pmux_pull { |
| 15 | PMUX_PULL_NORMAL = 0, |
| 16 | PMUX_PULL_DOWN, |
| 17 | PMUX_PULL_UP, |
| 18 | }; |
| 19 | |
| 20 | /* Defines whether a pin group is tristated or in normal operation */ |
| 21 | enum pmux_tristate { |
| 22 | PMUX_TRI_NORMAL = 0, |
| 23 | PMUX_TRI_TRISTATE = 1, |
| 24 | }; |
| 25 | |
| 26 | #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC |
| 27 | enum pmux_pin_io { |
| 28 | PMUX_PIN_OUTPUT = 0, |
| 29 | PMUX_PIN_INPUT = 1, |
| 30 | PMUX_PIN_NONE, |
| 31 | }; |
| 32 | |
| 33 | enum pmux_pin_lock { |
| 34 | PMUX_PIN_LOCK_DEFAULT = 0, |
| 35 | PMUX_PIN_LOCK_DISABLE, |
| 36 | PMUX_PIN_LOCK_ENABLE, |
| 37 | }; |
| 38 | |
| 39 | enum pmux_pin_od { |
| 40 | PMUX_PIN_OD_DEFAULT = 0, |
| 41 | PMUX_PIN_OD_DISABLE, |
| 42 | PMUX_PIN_OD_ENABLE, |
| 43 | }; |
| 44 | |
| 45 | enum pmux_pin_ioreset { |
| 46 | PMUX_PIN_IO_RESET_DEFAULT = 0, |
| 47 | PMUX_PIN_IO_RESET_DISABLE, |
| 48 | PMUX_PIN_IO_RESET_ENABLE, |
| 49 | }; |
| 50 | |
| 51 | #ifdef TEGRA_PMX_HAS_RCV_SEL |
| 52 | enum pmux_pin_rcv_sel { |
| 53 | PMUX_PIN_RCV_SEL_DEFAULT = 0, |
| 54 | PMUX_PIN_RCV_SEL_NORMAL, |
| 55 | PMUX_PIN_RCV_SEL_HIGH, |
| 56 | }; |
| 57 | #endif /* TEGRA_PMX_HAS_RCV_SEL */ |
| 58 | #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ |
| 59 | |
| 60 | /* |
| 61 | * This defines the configuration for a pin, including the function assigned, |
| 62 | * pull up/down settings and tristate settings. Having set up one of these |
| 63 | * you can call pinmux_config_pingroup() to configure a pin in one step. Also |
| 64 | * available is pinmux_config_table() to configure a list of pins. |
| 65 | */ |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 66 | struct pmux_pingrp_config { |
| 67 | enum pmux_pingrp pingrp; /* pin group PMUX_PINGRP_... */ |
| 68 | enum pmux_func func; /* function to assign PMUX_FUNC_... */ |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 69 | enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ |
| 70 | enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ |
| 71 | #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 72 | enum pmux_pin_io io; /* input or output PMUX_PIN_... */ |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 73 | enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 74 | enum pmux_pin_od od; /* open-drain or push-pull driver */ |
| 75 | enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 76 | #ifdef TEGRA_PMX_HAS_RCV_SEL |
| 77 | enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ |
| 78 | /* VIL/VIH receivers */ |
| 79 | #endif |
| 80 | #endif |
| 81 | }; |
| 82 | |
| 83 | /* Set the mux function for a pin group */ |
| 84 | void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); |
| 85 | |
| 86 | /* Set the pull up/down feature for a pin group */ |
| 87 | void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); |
| 88 | |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 89 | /* Set a pin group to tristate */ |
| 90 | void pinmux_tristate_enable(enum pmux_pingrp pin); |
| 91 | |
| 92 | /* Set a pin group to normal (non tristate) */ |
| 93 | void pinmux_tristate_disable(enum pmux_pingrp pin); |
| 94 | |
| 95 | #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC |
| 96 | /* Set a pin group as input or output */ |
| 97 | void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); |
| 98 | #endif |
| 99 | |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 100 | /** |
| 101 | * Configure a list of pin groups |
| 102 | * |
| 103 | * @param config List of config items |
| 104 | * @param len Number of config items in list |
| 105 | */ |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 106 | void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, |
| 107 | int len); |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 108 | |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 109 | #ifdef TEGRA_PMX_HAS_DRVGRPS |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 110 | |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 111 | #define PMUX_SLWF_MIN 0 |
| 112 | #define PMUX_SLWF_MAX 3 |
| 113 | #define PMUX_SLWF_NONE -1 |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 114 | |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 115 | #define PMUX_SLWR_MIN 0 |
| 116 | #define PMUX_SLWR_MAX 3 |
| 117 | #define PMUX_SLWR_NONE -1 |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 118 | |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 119 | #define PMUX_DRVUP_MIN 0 |
| 120 | #define PMUX_DRVUP_MAX 127 |
| 121 | #define PMUX_DRVUP_NONE -1 |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 122 | |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 123 | #define PMUX_DRVDN_MIN 0 |
| 124 | #define PMUX_DRVDN_MAX 127 |
| 125 | #define PMUX_DRVDN_NONE -1 |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 126 | |
| 127 | /* Defines a pin group cfg's low-power mode select */ |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 128 | enum pmux_lpmd { |
| 129 | PMUX_LPMD_X8 = 0, |
| 130 | PMUX_LPMD_X4, |
| 131 | PMUX_LPMD_X2, |
| 132 | PMUX_LPMD_X, |
| 133 | PMUX_LPMD_NONE = -1, |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 134 | }; |
| 135 | |
| 136 | /* Defines whether a pin group cfg's schmidt is enabled or not */ |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 137 | enum pmux_schmt { |
| 138 | PMUX_SCHMT_DISABLE = 0, |
| 139 | PMUX_SCHMT_ENABLE = 1, |
| 140 | PMUX_SCHMT_NONE = -1, |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 141 | }; |
| 142 | |
| 143 | /* Defines whether a pin group cfg's high-speed mode is enabled or not */ |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 144 | enum pmux_hsm { |
| 145 | PMUX_HSM_DISABLE = 0, |
| 146 | PMUX_HSM_ENABLE = 1, |
| 147 | PMUX_HSM_NONE = -1, |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 148 | }; |
| 149 | |
| 150 | /* |
| 151 | * This defines the configuration for a pin group's pad control config |
| 152 | */ |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 153 | struct pmux_drvgrp_config { |
| 154 | enum pmux_drvgrp drvgrp; /* pin group PMUX_DRVGRP_x */ |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 155 | int slwf; /* falling edge slew */ |
| 156 | int slwr; /* rising edge slew */ |
| 157 | int drvup; /* pull-up drive strength */ |
| 158 | int drvdn; /* pull-down drive strength */ |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 159 | enum pmux_lpmd lpmd; /* low-power mode selection */ |
| 160 | enum pmux_schmt schmt; /* schmidt enable */ |
| 161 | enum pmux_hsm hsm; /* high-speed mode enable */ |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 162 | }; |
| 163 | |
| 164 | /** |
| 165 | * Set the GP pad configs |
| 166 | * |
| 167 | * @param config List of config items |
| 168 | * @param len Number of config items in list |
| 169 | */ |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 170 | void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, |
| 171 | int len); |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 172 | |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 173 | #endif /* TEGRA_PMX_HAS_DRVGRPS */ |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 174 | |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 175 | struct pmux_pingrp_desc { |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 176 | enum pmux_func funcs[4]; |
| 177 | #if defined(CONFIG_TEGRA20) |
| 178 | u32 ctl_id; |
| 179 | u32 pull_id; |
| 180 | #endif /* CONFIG_TEGRA20 */ |
| 181 | }; |
| 182 | |
Stephen Warren | dfb42fc | 2014-03-21 12:28:56 -0600 | [diff] [blame] | 183 | extern const struct pmux_pingrp_desc *tegra_soc_pingroups; |
Stephen Warren | e296995 | 2014-03-21 12:28:54 -0600 | [diff] [blame] | 184 | |
| 185 | #endif /* _TEGRA_PINMUX_H_ */ |