blob: e90a9136c363ba91a747832da29692359f6506da [file] [log] [blame]
Stefan Roesec0132f62016-08-30 16:48:20 +02001/*
2 * Copyright (C) 2015-2016 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <fdtdec.h>
9#include <asm/io.h>
10#include <asm/arch/cpu.h>
11#include <asm/arch/soc.h>
12
13#include "comphy.h"
14#include "comphy_hpipe.h"
15#include "sata.h"
16#include "utmi_phy.h"
17
18DECLARE_GLOBAL_DATA_PTR;
19
20#define SD_ADDR(base, lane) (base + 0x1000 * lane)
21#define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800)
22#define COMPHY_ADDR(base, lane) (base + 0x28 * lane)
23
24struct utmi_phy_data {
25 void __iomem *utmi_base_addr;
26 void __iomem *usb_cfg_addr;
27 void __iomem *utmi_cfg_addr;
28 u32 utmi_phy_port;
29};
30
31/*
32 * For CP-110 we have 2 Selector registers "PHY Selectors",
33 * and "PIPE Selectors".
34 * PIPE selector include USB and PCIe options.
35 * PHY selector include the Ethernet and SATA options, every Ethernet
36 * option has different options, for example: serdes lane2 had option
Stefan Roesecb686452017-04-24 18:45:21 +030037 * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, SFI)
Stefan Roesec0132f62016-08-30 16:48:20 +020038 */
39struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
40 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */
41 {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
42 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, /* Lane 1 */
43 {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA0, 0x4} } },
44 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
45 {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1},
Stefan Roesecb686452017-04-24 18:45:21 +030046 {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4} } },
Stefan Roesec0132f62016-08-30 16:48:20 +020047 {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 3 */
48 {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1},
Stefan Roesecb686452017-04-24 18:45:21 +030049 {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_XAUI1, 0x1},
Stefan Roesec0132f62016-08-30 16:48:20 +020050 {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
51 {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
Stefan Roesed37f0202017-04-24 18:45:25 +030052 {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x2},
Stefan Roesec0132f62016-08-30 16:48:20 +020053 {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } },
54 {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */
55 {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1},
56 {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } },
57};
58
59struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
60 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
61 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
62 {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2},
63 {PHY_TYPE_PEX0, 0x4} } },
64 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
65 {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
66 {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
67 {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
68 {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
69 {PHY_TYPE_USB3_HOST1, 0x1},
70 {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } },
71 {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
72};
73
74static u32 polling_with_timeout(void __iomem *addr, u32 val,
75 u32 mask, unsigned long usec_timout)
76{
77 u32 data;
78
79 do {
80 udelay(1);
81 data = readl(addr) & mask;
82 } while (data != val && --usec_timout > 0);
83
84 if (usec_timout == 0)
85 return data;
86
87 return 0;
88}
89
Stefan Roese7dda98e2017-04-24 18:45:22 +030090static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src,
91 bool is_end_point, void __iomem *hpipe_base,
Stefan Roesec0132f62016-08-30 16:48:20 +020092 void __iomem *comphy_base)
93{
94 u32 mask, data, ret = 1;
95 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
96 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
97 void __iomem *addr;
98 u32 pcie_clk = 0; /* set input by default */
99
100 debug_enter();
101
102 /*
103 * ToDo:
104 * Add SAR (Sample-At-Reset) configuration for the PCIe clock
105 * direction. SAR code is currently not ported from Marvell
106 * U-Boot to mainline version.
107 *
108 * SerDes Lane 4/5 got the PCIe ref-clock #1,
109 * and SerDes Lane 0 got PCIe ref-clock #0
110 */
111 debug("PCIe clock = %x\n", pcie_clk);
Stefan Roese7dda98e2017-04-24 18:45:22 +0300112 debug("PCIe RC = %d\n", !is_end_point);
Stefan Roesec0132f62016-08-30 16:48:20 +0200113 debug("PCIe width = %d\n", pcie_width);
114
115 /* enable PCIe by4 and by2 */
116 if (lane == 0) {
117 if (pcie_width == 4) {
118 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
119 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET,
120 COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK);
121 } else if (pcie_width == 2) {
122 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
123 0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET,
124 COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK);
125 }
126 }
127
128 /*
129 * If PCIe clock is output and clock source from SerDes lane 5,
130 * we need to configure the clock-source MUX.
131 * By default, the clock source is from lane 4
132 */
133 if (pcie_clk && clk_src && (lane == 5)) {
134 reg_set((void __iomem *)DFX_DEV_GEN_CTRL12,
135 0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET,
136 DFX_DEV_GEN_PCIE_CLK_SRC_MASK);
137 }
138
139 debug("stage: RFU configurations - hard reset comphy\n");
140 /* RFU configurations - hard reset comphy */
141 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
142 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
143 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
144 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
145 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
146 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
147 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
148 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
149 mask |= COMMON_PHY_PHY_MODE_MASK;
150 data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET;
151 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
152
153 /* release from hard reset */
154 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
155 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
156 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
157 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
158 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
159
160 /* Wait 1ms - until band gap and ref clock ready */
161 mdelay(1);
162 /* Start comphy Configuration */
163 debug("stage: Comphy configuration\n");
164 /* Set PIPE soft reset */
165 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
166 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
167 /* Set PHY datapath width mode for V0 */
168 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
169 data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
170 /* Set Data bus width USB mode for V0 */
171 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
172 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
173 /* Set CORE_CLK output frequency for 250Mhz */
174 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
175 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
176 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
177 /* Set PLL ready delay for 0x2 */
178 data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET;
179 mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK;
180 if (pcie_width != 1) {
181 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET;
182 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK;
183 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET;
184 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK;
185 }
186 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask);
187
188 /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */
189 data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET;
190 mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK;
191 if (pcie_width != 1) {
192 mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK;
193 mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK;
194 mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK;
195 if (lane == 0) {
196 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET;
197 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET;
198 } else if (lane == (pcie_width - 1)) {
199 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET;
200 }
201 }
202 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask);
203 /* Config update polarity equalization */
204 reg_set(hpipe_addr + HPIPE_LANE_EQ_CFG1_REG,
205 0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET,
206 HPIPE_CFG_UPDATE_POLARITY_MASK);
207 /* Set PIPE version 4 to mode enable */
208 reg_set(hpipe_addr + HPIPE_DFE_CTRL_28_REG,
209 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET,
210 HPIPE_DFE_CTRL_28_PIPE4_MASK);
211 /* TODO: check if pcie clock is output/input - for bringup use input*/
212 /* Enable PIN clock 100M_125M */
213 mask = 0;
214 data = 0;
215 /* Only if clock is output, configure the clock-source mux */
216 if (pcie_clk) {
217 mask |= HPIPE_MISC_CLK100M_125M_MASK;
218 data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET;
219 }
220 /*
221 * Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz
222 * clock
223 */
224 mask |= HPIPE_MISC_TXDCLK_2X_MASK;
225 data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET;
226 /* Enable 500MHz Clock */
227 mask |= HPIPE_MISC_CLK500_EN_MASK;
228 data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET;
229 if (pcie_clk) { /* output */
230 /* Set reference clock comes from group 1 */
231 mask |= HPIPE_MISC_REFCLK_SEL_MASK;
232 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
233 } else {
234 /* Set reference clock comes from group 2 */
235 mask |= HPIPE_MISC_REFCLK_SEL_MASK;
236 data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET;
237 }
238 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
239 if (pcie_clk) { /* output */
240 /* Set reference frequcency select - 0x2 for 25MHz*/
241 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
242 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
243 } else {
244 /* Set reference frequcency select - 0x0 for 100MHz*/
245 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
246 data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
247 }
248 /* Set PHY mode to PCIe */
249 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
250 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
251 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
252
253 /* ref clock alignment */
254 if (pcie_width != 1) {
255 mask = HPIPE_LANE_ALIGN_OFF_MASK;
256 data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET;
257 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask);
258 }
259
260 /*
261 * Set the amount of time spent in the LoZ state - set for 0x7 only if
262 * the PCIe clock is output
263 */
264 if (pcie_clk) {
265 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
266 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
267 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
268 }
269
270 /* Set Maximal PHY Generation Setting(8Gbps) */
271 mask = HPIPE_INTERFACE_GEN_MAX_MASK;
272 data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET;
273 /* Set Link Train Mode (Tx training control pins are used) */
274 mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK;
275 data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET;
276 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask);
277
278 /* Set Idle_sync enable */
279 mask = HPIPE_PCIE_IDLE_SYNC_MASK;
280 data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET;
281 /* Select bits for PCIE Gen3(32bit) */
282 mask |= HPIPE_PCIE_SEL_BITS_MASK;
283 data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET;
284 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask);
285
286 /* Enable Tx_adapt_g1 */
287 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK;
288 data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET;
289 /* Enable Tx_adapt_gn1 */
290 mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK;
291 data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET;
292 /* Disable Tx_adapt_g0 */
293 mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK;
294 data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
295 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
296
297 /* Set reg_tx_train_chk_init */
298 mask = HPIPE_TX_TRAIN_CHK_INIT_MASK;
299 data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET;
300 /* Enable TX_COE_FM_PIN_PCIE3_EN */
301 mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK;
302 data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET;
303 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask);
304
305 debug("stage: TRx training parameters\n");
306 /* Set Preset sweep configurations */
307 mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK;
308 data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET;
309
310 mask |= HPIPE_TX_NUM_OF_PRESET_MASK;
311 data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET;
312
313 mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK;
314 data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET;
315 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask);
316
317 /* Tx train start configuration */
318 mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK;
319 data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET;
320
321 mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK;
322 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET;
323
324 mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK;
325 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET;
326
327 mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK;
328 data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET;
329 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask);
330
331 /* Enable Tx train P2P */
332 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK;
333 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET;
334 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask);
335
336 /* Configure Tx train timeout */
337 mask = HPIPE_TRX_TRAIN_TIMER_MASK;
338 data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET;
339 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask);
340
341 /* Disable G0/G1/GN1 adaptation */
342 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK
343 | HPIPE_TX_TRAIN_CTRL_G0_OFFSET;
344 data = 0;
345 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask);
346
347 /* Disable DTL frequency loop */
348 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
349 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
350 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
351
352 /* Configure G3 DFE */
353 mask = HPIPE_G3_DFE_RES_MASK;
354 data = 0x3 << HPIPE_G3_DFE_RES_OFFSET;
355 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);
356
357 /* Force DFE resolution (use GEN table value) */
358 mask = HPIPE_DFE_RES_FORCE_MASK;
359 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
360 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
361
362 /* Configure initial and final coefficient value for receiver */
363 mask = HPIPE_G3_RX_SELMUPI_MASK;
364 data = 0x1 << HPIPE_G3_RX_SELMUPI_OFFSET;
365
366 mask |= HPIPE_G3_RX_SELMUPF_MASK;
367 data |= 0x1 << HPIPE_G3_RX_SELMUPF_OFFSET;
368
369 mask |= HPIPE_G3_SETTING_BIT_MASK;
370 data |= 0x0 << HPIPE_G3_SETTING_BIT_OFFSET;
371 reg_set(hpipe_addr + HPIPE_G3_SETTINGS_1_REG, data, mask);
372
373 /* Trigger sampler enable pulse */
374 mask = HPIPE_SMAPLER_MASK;
375 data = 0x1 << HPIPE_SMAPLER_OFFSET;
376 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask);
377 udelay(5);
378 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask);
379
380 /* FFE resistor tuning for different bandwidth */
381 mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK;
382 data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;
383
384 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK;
385 data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET;
386 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);
387
Stefan Roese7dda98e2017-04-24 18:45:22 +0300388 if (!is_end_point) {
389 /* Set phy in root complex mode */
390 mask = HPIPE_CFG_PHY_RC_EP_MASK;
391 data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET;
392 reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask);
393 }
Stefan Roesec0132f62016-08-30 16:48:20 +0200394
395 debug("stage: Comphy power up\n");
396
397 /*
398 * For PCIe by4 or by2 - release from reset only after finish to
399 * configure all lanes
400 */
401 if ((pcie_width == 1) || (lane == (pcie_width - 1))) {
402 u32 i, start_lane, end_lane;
403
404 if (pcie_width != 1) {
405 /* allows writing to all lanes in one write */
406 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
407 0x0 <<
408 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
409 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
410 start_lane = 0;
411 end_lane = pcie_width;
412
413 /*
414 * Release from PIPE soft reset
415 * for PCIe by4 or by2 - release from soft reset
416 * all lanes - can't use read modify write
417 */
418 reg_set(HPIPE_ADDR(hpipe_base, 0) +
419 HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff);
420 } else {
421 start_lane = lane;
422 end_lane = lane + 1;
423
424 /*
425 * Release from PIPE soft reset
426 * for PCIe by4 or by2 - release from soft reset
427 * all lanes
428 */
429 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
430 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
431 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
432 }
433
434
435 if (pcie_width != 1) {
436 /* disable writing to all lanes with one write */
437 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
438 0x3210 <<
439 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET,
440 COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK);
441 }
442
443 debug("stage: Check PLL\n");
444 /* Read lane status */
445 for (i = start_lane; i < end_lane; i++) {
446 addr = HPIPE_ADDR(hpipe_base, i) +
447 HPIPE_LANE_STATUS1_REG;
448 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
449 mask = data;
450 data = polling_with_timeout(addr, data, mask, 15000);
451 if (data != 0) {
452 debug("Read from reg = %p - value = 0x%x\n",
453 hpipe_addr + HPIPE_LANE_STATUS1_REG,
454 data);
455 error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
456 ret = 0;
457 }
458 }
459 }
460
461 debug_exit();
462 return ret;
463}
464
465static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
466 void __iomem *comphy_base)
467{
468 u32 mask, data, ret = 1;
469 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
470 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
471 void __iomem *addr;
472
473 debug_enter();
474 debug("stage: RFU configurations - hard reset comphy\n");
475 /* RFU configurations - hard reset comphy */
476 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
477 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
478 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
479 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
480 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
481 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
482 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
483 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
484 mask |= COMMON_PHY_PHY_MODE_MASK;
485 data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
486 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
487
488 /* release from hard reset */
489 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
490 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
491 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
492 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
493 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
494
495 /* Wait 1ms - until band gap and ref clock ready */
496 mdelay(1);
497
498 /* Start comphy Configuration */
499 debug("stage: Comphy configuration\n");
500 /* Set PIPE soft reset */
501 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
502 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
503 /* Set PHY datapath width mode for V0 */
504 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
505 data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
506 /* Set Data bus width USB mode for V0 */
507 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
508 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
509 /* Set CORE_CLK output frequency for 250Mhz */
510 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
511 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
512 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
513 /* Set PLL ready delay for 0x2 */
514 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
515 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
516 HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
517 /* Set reference clock to come from group 1 - 25Mhz */
518 reg_set(hpipe_addr + HPIPE_MISC_REG,
519 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
520 HPIPE_MISC_REFCLK_SEL_MASK);
521 /* Set reference frequcency select - 0x2 */
522 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
523 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
524 /* Set PHY mode to USB - 0x5 */
525 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
526 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
527 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
528 /* Set the amount of time spent in the LoZ state - set for 0x7 */
529 reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
530 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
531 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
532 /* Set max PHY generation setting - 5Gbps */
533 reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
534 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
535 HPIPE_INTERFACE_GEN_MAX_MASK);
536 /* Set select data width 20Bit (SEL_BITS[2:0]) */
537 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
538 0x1 << HPIPE_LOOPBACK_SEL_OFFSET,
539 HPIPE_LOOPBACK_SEL_MASK);
540 /* select de-emphasize 3.5db */
541 reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
542 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET,
543 HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK);
544 /* override tx margining from the MAC */
545 reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
546 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
547 HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
548
549 /* Start analog paramters from ETP(HW) */
550 debug("stage: Analog paramters from ETP(HW)\n");
551 /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
552 mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
553 data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
554 /* Set Override PHY DFE control pins for 0x1 */
555 mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
556 data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
557 /* Set Spread Spectrum Clock Enable fot 0x1 */
558 mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
559 data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
560 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
561 /* End of analog parameters */
562
563 debug("stage: Comphy power up\n");
564 /* Release from PIPE soft reset */
565 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
566 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
567 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
568
569 /* wait 15ms - for comphy calibration done */
570 debug("stage: Check PLL\n");
571 /* Read lane status */
572 addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
573 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
574 mask = data;
575 data = polling_with_timeout(addr, data, mask, 15000);
576 if (data != 0) {
577 debug("Read from reg = %p - value = 0x%x\n",
578 hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
579 error("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
580 ret = 0;
581 }
582
583 debug_exit();
584 return ret;
585}
586
587static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
588 void __iomem *comphy_base, int comphy_index)
589{
590 u32 mask, data, i, ret = 1;
591 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
592 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
593 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
594 void __iomem *addr;
595 void __iomem *sata_base = NULL;
596 int sata_node = -1; /* Set to -1 in order to read the first sata node */
597
598 debug_enter();
599
600 /*
601 * Assumption - each CP has only one SATA controller
602 * Calling fdt_node_offset_by_compatible first time (with sata_node = -1
603 * will return the first node always.
604 * In order to parse each CPs SATA node, fdt_node_offset_by_compatible
605 * must be called again (according to the CP id)
606 */
607 for (i = 0; i < (comphy_index + 1); i++)
608 sata_node = fdt_node_offset_by_compatible(
609 gd->fdt_blob, sata_node, "marvell,armada-8k-ahci");
610
611 if (sata_node == 0) {
612 error("SATA node not found in FDT\n");
613 return 0;
614 }
615
616 sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
617 gd->fdt_blob, sata_node, "reg", 0, NULL, true);
618 if (sata_base == NULL) {
619 error("SATA address not found in FDT\n");
620 return 0;
621 }
622
623 debug("SATA address found in FDT %p\n", sata_base);
624
625 debug("stage: MAC configuration - power down comphy\n");
626 /*
627 * MAC configuration powe down comphy use indirect address for
628 * vendor spesific SATA control register
629 */
630 reg_set(sata_base + SATA3_VENDOR_ADDRESS,
631 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
632 SATA3_VENDOR_ADDR_MASK);
633 /* SATA 0 power down */
634 mask = SATA3_CTRL_SATA0_PD_MASK;
635 data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET;
636 /* SATA 1 power down */
637 mask |= SATA3_CTRL_SATA1_PD_MASK;
638 data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET;
639 /* SATA SSU disable */
640 mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
641 data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
642 /* SATA port 1 disable */
643 mask |= SATA3_CTRL_SATA_SSU_MASK;
644 data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET;
645 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
646
647 debug("stage: RFU configurations - hard reset comphy\n");
648 /* RFU configurations - hard reset comphy */
649 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
650 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
651 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
652 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
653 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
654 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
655 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
656 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
657 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
658
659 /* Set select data width 40Bit - SATA mode only */
660 reg_set(comphy_addr + COMMON_PHY_CFG6_REG,
661 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET,
662 COMMON_PHY_CFG6_IF_40_SEL_MASK);
663
664 /* release from hard reset in SD external */
665 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
666 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
667 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
668 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
669 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
670
671 /* Wait 1ms - until band gap and ref clock ready */
672 mdelay(1);
673
674 debug("stage: Comphy configuration\n");
675 /* Start comphy Configuration */
676 /* Set reference clock to comes from group 1 - choose 25Mhz */
677 reg_set(hpipe_addr + HPIPE_MISC_REG,
678 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
679 HPIPE_MISC_REFCLK_SEL_MASK);
680 /* Reference frequency select set 1 (for SATA = 25Mhz) */
681 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
682 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
683 /* PHY mode select (set SATA = 0x0 */
684 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
685 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
686 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
687 /* Set max PHY generation setting - 6Gbps */
688 reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
689 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
690 HPIPE_INTERFACE_GEN_MAX_MASK);
691 /* Set select data width 40Bit (SEL_BITS[2:0]) */
692 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
693 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
694
695 debug("stage: Analog paramters from ETP(HW)\n");
696 /*
697 * TODO: Set analog paramters from ETP(HW) - for now use the
698 * default datas
699 */
700
701 /* DFE reset sequence */
702 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
703 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
704 HPIPE_PWR_CTR_RST_DFE_MASK);
705 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
706 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET,
707 HPIPE_PWR_CTR_RST_DFE_MASK);
708 /* SW reset for interupt logic */
709 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
710 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
711 HPIPE_PWR_CTR_SFT_RST_MASK);
712 reg_set(hpipe_addr + HPIPE_PWR_CTR_REG,
713 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET,
714 HPIPE_PWR_CTR_SFT_RST_MASK);
715
716 debug("stage: Comphy power up\n");
717 /*
718 * MAC configuration power up comphy - power up PLL/TX/RX
719 * use indirect address for vendor spesific SATA control register
720 */
721 reg_set(sata_base + SATA3_VENDOR_ADDRESS,
722 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
723 SATA3_VENDOR_ADDR_MASK);
724 /* SATA 0 power up */
725 mask = SATA3_CTRL_SATA0_PD_MASK;
726 data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET;
727 /* SATA 1 power up */
728 mask |= SATA3_CTRL_SATA1_PD_MASK;
729 data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET;
730 /* SATA SSU enable */
731 mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
732 data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
733 /* SATA port 1 enable */
734 mask |= SATA3_CTRL_SATA_SSU_MASK;
735 data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET;
736 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
737
738 /* MBUS request size and interface select register */
739 reg_set(sata_base + SATA3_VENDOR_ADDRESS,
740 SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET,
741 SATA3_VENDOR_ADDR_MASK);
742 /* Mbus regret enable */
743 reg_set(sata_base + SATA3_VENDOR_DATA,
744 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK);
745
746 debug("stage: Check PLL\n");
747
748 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
749 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK &
750 SD_EXTERNAL_STATUS0_PLL_RX_MASK;
751 mask = data;
752 data = polling_with_timeout(addr, data, mask, 15000);
753 if (data != 0) {
754 debug("Read from reg = %p - value = 0x%x\n",
755 hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
756 error("SD_EXTERNAL_STATUS0_PLL_TX is %d, SD_EXTERNAL_STATUS0_PLL_RX is %d\n",
757 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK),
758 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK));
759 ret = 0;
760 }
761
762 debug_exit();
763 return ret;
764}
765
766static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed,
767 void __iomem *hpipe_base,
768 void __iomem *comphy_base)
769{
770 u32 mask, data, ret = 1;
771 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
772 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
773 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
774 void __iomem *addr;
775
776 debug_enter();
777 debug("stage: RFU configurations - hard reset comphy\n");
778 /* RFU configurations - hard reset comphy */
779 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
780 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
781 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
782 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
783 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
784
785 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
786 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
787 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
788 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
789 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
790 if (sgmii_speed == PHY_SPEED_1_25G) {
791 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
792 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
793 } else {
794 /* 3.125G */
795 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
796 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
797 }
798 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
799 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
800 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
801 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
802 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
803 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
804 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
805
806 /* release from hard reset */
807 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
808 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
809 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
810 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
811 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
812 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
813 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
814
815 /* release from hard reset */
816 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
817 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
818 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
819 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
820 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
821
822
823 /* Wait 1ms - until band gap and ref clock ready */
824 mdelay(1);
825
826 /* Start comphy Configuration */
827 debug("stage: Comphy configuration\n");
828 /* set reference clock */
829 mask = HPIPE_MISC_REFCLK_SEL_MASK;
830 data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
831 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
832 /* Power and PLL Control */
833 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
834 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
835 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
836 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
837 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
838 /* Loopback register */
839 mask = HPIPE_LOOPBACK_SEL_MASK;
840 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
841 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
842 /* rx control 1 */
843 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
844 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
845 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
846 data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
847 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
848 /* DTL Control */
849 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
850 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
851 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
852
853 /* Set analog paramters from ETP(HW) - for now use the default datas */
854 debug("stage: Analog paramters from ETP(HW)\n");
855
856 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
857 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
858 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
859
860 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
861 /* SERDES External Configuration */
862 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
863 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
864 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
865 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
866 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
867 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
868 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
869
870 /* check PLL rx & tx ready */
871 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
872 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
873 SD_EXTERNAL_STATUS0_PLL_TX_MASK;
874 mask = data;
875 data = polling_with_timeout(addr, data, mask, 15000);
876 if (data != 0) {
877 debug("Read from reg = %p - value = 0x%x\n",
878 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
879 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
880 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
881 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
882 ret = 0;
883 }
884
885 /* RX init */
886 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
887 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
888 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
889
890 /* check that RX init done */
891 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
892 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
893 mask = data;
894 data = polling_with_timeout(addr, data, mask, 100);
895 if (data != 0) {
896 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
897 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
898 ret = 0;
899 }
900
901 debug("stage: RF Reset\n");
902 /* RF Reset */
903 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
904 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
905 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
906 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
907 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
908
909 debug_exit();
910 return ret;
911}
912
Stefan Roesecb686452017-04-24 18:45:21 +0300913static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base,
914 void __iomem *comphy_base)
Stefan Roesec0132f62016-08-30 16:48:20 +0200915{
916 u32 mask, data, ret = 1;
917 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
918 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
919 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
920 void __iomem *addr;
921
922 debug_enter();
923 debug("stage: RFU configurations - hard reset comphy\n");
924 /* RFU configurations - hard reset comphy */
925 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
926 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
927 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
928 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
929 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
930
931 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
932 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
933 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
934 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
935 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
936 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
937 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
938 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
939 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
940 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
941 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
942 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
943 data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
944 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
945
946 /* release from hard reset */
947 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
948 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
949 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
950 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
951 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
952 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
953 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
954
955 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
956 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
957 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
958 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
959 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
960
961
962 /* Wait 1ms - until band gap and ref clock ready */
963 mdelay(1);
964
965 /* Start comphy Configuration */
966 debug("stage: Comphy configuration\n");
967 /* set reference clock */
968 mask = HPIPE_MISC_ICP_FORCE_MASK;
969 data = 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET;
970 mask |= HPIPE_MISC_REFCLK_SEL_MASK;
971 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET;
972 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask);
973 /* Power and PLL Control */
974 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
975 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
976 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
977 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
978 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
979 /* Loopback register */
980 mask = HPIPE_LOOPBACK_SEL_MASK;
981 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET;
982 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
983 /* rx control 1 */
984 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
985 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
986 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
987 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
988 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
989 /* DTL Control */
990 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK;
991 data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET;
992 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);
993
994 /* Set analog paramters from ETP(HW) */
995 debug("stage: Analog paramters from ETP(HW)\n");
996 /* SERDES External Configuration 2 */
997 mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK;
998 data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET;
999 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);
1000 /* 0x7-DFE Resolution control */
1001 mask = HPIPE_DFE_RES_FORCE_MASK;
1002 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
1003 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
1004 /* 0xd-G1_Setting_0 */
1005 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK;
1006 data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET;
1007 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK;
1008 data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET;
1009 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask);
1010 /* Genration 1 setting 2 (G1_Setting_2) */
1011 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK;
1012 data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET;
1013 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK;
1014 data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET;
1015 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask);
1016 /* Transmitter Slew Rate Control register (tx_reg1) */
1017 mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK;
1018 data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET;
1019 mask |= HPIPE_TX_REG1_SLC_EN_MASK;
1020 data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET;
1021 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask);
1022 /* Impedance Calibration Control register (cal_reg1) */
1023 mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK;
1024 data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
1025 mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK;
1026 data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET;
1027 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask);
1028 /* Generation 1 Setting 5 (g1_setting_5) */
1029 mask = HPIPE_G1_SETTING_5_G1_ICP_MASK;
1030 data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET;
1031 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask);
1032 /* 0xE-G1_Setting_1 */
1033 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1034 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
1035 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
1036 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
1037 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
1038 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
1039 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1040 /* 0xA-DFE_Reg3 */
1041 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
1042 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
1043 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
1044 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
1045 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1046
1047 /* 0x111-G1_Setting_4 */
1048 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
1049 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
1050 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1051 /* Genration 1 setting 3 (G1_Setting_3) */
1052 mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK;
1053 data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET;
1054 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
1055
1056 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
1057 /* SERDES External Configuration */
1058 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1059 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1060 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1061 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1062 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1063 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1064 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1065
1066
1067 /* check PLL rx & tx ready */
1068 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1069 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1070 SD_EXTERNAL_STATUS0_PLL_TX_MASK;
1071 mask = data;
1072 data = polling_with_timeout(addr, data, mask, 15000);
1073 if (data != 0) {
1074 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1075 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
1076 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
1077 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
1078 ret = 0;
1079 }
1080
1081 /* RX init */
1082 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1083 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1084 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1085
1086
1087 /* check that RX init done */
1088 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1089 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1090 mask = data;
1091 data = polling_with_timeout(addr, data, mask, 100);
1092 if (data != 0) {
1093 debug("Read from reg = %p - value = 0x%x\n",
1094 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1095 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
1096 ret = 0;
1097 }
1098
1099 debug("stage: RF Reset\n");
1100 /* RF Reset */
1101 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1102 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1103 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1104 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1105 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1106
1107 debug_exit();
1108 return ret;
1109}
1110
1111static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base,
1112 void __iomem *comphy_base)
1113{
1114 u32 mask, data, ret = 1;
1115 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
1116 void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
1117 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
1118 void __iomem *addr;
1119
1120 debug_enter();
1121 debug("stage: RFU configurations - hard reset comphy\n");
1122 /* RFU configurations - hard reset comphy */
1123 mask = COMMON_PHY_CFG1_PWR_UP_MASK;
1124 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
1125 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
1126 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
1127 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
1128
1129 if (lane == 2) {
1130 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
1131 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET,
1132 COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
1133 }
1134 if (lane == 4) {
1135 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
1136 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET,
1137 COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
1138 }
1139
1140 /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
1141 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1142 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1143 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
1144 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
1145 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
1146 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
1147 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1148 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1149 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1150 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1151 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
1152 data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
1153 mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
1154 data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET;
1155 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1156
1157 /* release from hard reset */
1158 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1159 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1160 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1161 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1162 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1163 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1164 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1165
1166 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
1167 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
1168 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
1169 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
1170 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1171
1172 /* Wait 1ms - until band gap and ref clock ready */
1173 mdelay(1);
1174
1175 /* Start comphy Configuration */
1176 debug("stage: Comphy configuration\n");
1177 /* set reference clock */
1178 reg_set(hpipe_addr + HPIPE_MISC_REG,
1179 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
1180 HPIPE_MISC_REFCLK_SEL_MASK);
1181 /* Power and PLL Control */
1182 mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
1183 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
1184 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
1185 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
1186 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
1187 /* Loopback register */
1188 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
1189 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
1190 /* rx control 1 */
1191 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
1192 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
1193 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
1194 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
1195 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
1196 /* DTL Control */
1197 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG,
1198 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET,
1199 HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
1200
1201 /* Set analog paramters from ETP(HW) */
1202 debug("stage: Analog paramters from ETP(HW)\n");
1203 /* SERDES External Configuration 2 */
1204 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG,
1205 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET,
1206 SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
1207 /* 0x7-DFE Resolution control */
1208 reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET,
1209 HPIPE_DFE_RES_FORCE_MASK);
1210 /* 0xd-G1_Setting_0 */
1211 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
1212 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
1213 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
1214 /* 0xE-G1_Setting_1 */
1215 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
1216 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
1217 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
1218 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
1219 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
1220 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
1221 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
1222 /* 0xA-DFE_Reg3 */
1223 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
1224 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
1225 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
1226 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
1227 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
1228
1229 /* 0x111-G1_Setting_4 */
1230 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
1231 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
1232 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
1233
1234 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
1235 /* SERDES External Configuration */
1236 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
1237 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
1238 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
1239 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
1240 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
1241 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
1242 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
1243
1244
1245 /* check PLL rx & tx ready */
1246 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1247 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
1248 SD_EXTERNAL_STATUS0_PLL_TX_MASK;
1249 mask = data;
1250 data = polling_with_timeout(addr, data, mask, 15000);
1251 if (data != 0) {
1252 debug("Read from reg = %p - value = 0x%x\n",
1253 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1254 error("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
1255 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
1256 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
1257 ret = 0;
1258 }
1259
1260 /* RX init */
1261 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG,
1262 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET,
1263 SD_EXTERNAL_CONFIG1_RX_INIT_MASK);
1264
1265 /* check that RX init done */
1266 addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
1267 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
1268 mask = data;
1269 data = polling_with_timeout(addr, data, mask, 100);
1270 if (data != 0) {
1271 debug("Read from reg = %p - value = 0x%x\n",
1272 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
1273 error("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
1274 ret = 0;
1275 }
1276
1277 debug("stage: RF Reset\n");
1278 /* RF Reset */
1279 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
1280 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
1281 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
1282 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
1283 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
1284
1285 debug_exit();
1286 return ret;
1287}
1288
1289static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
1290 void __iomem *usb_cfg_addr,
1291 void __iomem *utmi_cfg_addr,
1292 u32 utmi_phy_port)
1293{
1294 u32 mask, data;
1295
1296 debug_enter();
1297 debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n",
1298 utmi_index);
1299 /* Power down UTMI PHY */
1300 reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET,
1301 UTMI_PHY_CFG_PU_MASK);
1302
1303 /*
1304 * If UTMI connected to USB Device, configure mux prior to PHY init
1305 * (Device can be connected to UTMI0 or to UTMI1)
1306 */
Stefan Roesee89acc42017-04-24 18:45:23 +03001307 if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) {
Stefan Roesec0132f62016-08-30 16:48:20 +02001308 debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n",
1309 utmi_index);
1310 /* USB3 Device UTMI enable */
1311 mask = UTMI_USB_CFG_DEVICE_EN_MASK;
1312 data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET;
1313 /* USB3 Device UTMI MUX */
1314 mask |= UTMI_USB_CFG_DEVICE_MUX_MASK;
1315 data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET;
1316 reg_set(usb_cfg_addr, data, mask);
1317 }
1318
1319 /* Set Test suspendm mode */
1320 mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK;
1321 data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET;
1322 /* Enable Test UTMI select */
1323 mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK;
1324 data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET;
1325 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask);
1326
1327 /* Wait for UTMI power down */
1328 mdelay(1);
1329
1330 debug_exit();
1331 return;
1332}
1333
1334static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
1335 void __iomem *usb_cfg_addr,
1336 void __iomem *utmi_cfg_addr,
1337 u32 utmi_phy_port)
1338{
1339 u32 mask, data;
1340
1341 debug_exit();
1342 debug("stage: Configure UTMI PHY %d registers\n", utmi_index);
1343 /* Reference Clock Divider Select */
1344 mask = UTMI_PLL_CTRL_REFDIV_MASK;
1345 data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET;
1346 /* Feedback Clock Divider Select - 90 for 25Mhz*/
1347 mask |= UTMI_PLL_CTRL_FBDIV_MASK;
1348 data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET;
1349 /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
1350 mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
1351 data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
1352 reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask);
1353
1354 /* Impedance Calibration Threshold Setting */
1355 reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG,
1356 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
1357 UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
1358
1359 /* Set LS TX driver strength coarse control */
1360 mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
1361 data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
1362 /* Set LS TX driver fine adjustment */
1363 mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
1364 data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
1365 reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
1366
1367 /* Enable SQ */
1368 mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
1369 data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
1370 /* Enable analog squelch detect */
1371 mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
1372 data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
1373 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
1374
1375 /* Set External squelch calibration number */
1376 mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK;
1377 data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET;
1378 /* Enable the External squelch calibration */
1379 mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK;
1380 data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET;
1381 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask);
1382
1383 /* Set Control VDAT Reference Voltage - 0.325V */
1384 mask = UTMI_CHGDTC_CTRL_VDAT_MASK;
1385 data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET;
1386 /* Set Control VSRC Reference Voltage - 0.6V */
1387 mask |= UTMI_CHGDTC_CTRL_VSRC_MASK;
1388 data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET;
1389 reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask);
1390
1391 debug_exit();
1392 return;
1393}
1394
1395static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
1396 void __iomem *usb_cfg_addr,
1397 void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
1398{
1399 u32 data, mask, ret = 1;
1400 void __iomem *addr;
1401
1402 debug_enter();
1403 debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n",
1404 utmi_index);
1405 /* Power UP UTMI PHY */
1406 reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET,
1407 UTMI_PHY_CFG_PU_MASK);
1408 /* Disable Test UTMI select */
1409 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG,
1410 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET,
1411 UTMI_CTRL_STATUS0_TEST_SEL_MASK);
1412
1413 debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
1414 addr = utmi_base_addr + UTMI_CALIB_CTRL_REG;
1415 data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
1416 mask = data;
1417 data = polling_with_timeout(addr, data, mask, 100);
1418 if (data != 0) {
1419 error("Impedance calibration is not done\n");
1420 debug("Read from reg = %p - value = 0x%x\n", addr, data);
1421 ret = 0;
1422 }
1423
1424 data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK;
1425 mask = data;
1426 data = polling_with_timeout(addr, data, mask, 100);
1427 if (data != 0) {
1428 error("PLL calibration is not done\n");
1429 debug("Read from reg = %p - value = 0x%x\n", addr, data);
1430 ret = 0;
1431 }
1432
1433 addr = utmi_base_addr + UTMI_PLL_CTRL_REG;
1434 data = UTMI_PLL_CTRL_PLL_RDY_MASK;
1435 mask = data;
1436 data = polling_with_timeout(addr, data, mask, 100);
1437 if (data != 0) {
1438 error("PLL is not ready\n");
1439 debug("Read from reg = %p - value = 0x%x\n", addr, data);
1440 ret = 0;
1441 }
1442
1443 if (ret)
1444 debug("Passed\n");
1445 else
1446 debug("\n");
1447
1448 debug_exit();
1449 return ret;
1450}
1451
1452/*
1453 * comphy_utmi_phy_init initialize the UTMI PHY
1454 * the init split in 3 parts:
1455 * 1. Power down transceiver and PLL
1456 * 2. UTMI PHY configure
1457 * 3. Powe up transceiver and PLL
1458 * Note: - Power down/up should be once for both UTMI PHYs
1459 * - comphy_dedicated_phys_init call this function if at least there is
1460 * one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
1461 * legal
1462 */
1463static void comphy_utmi_phy_init(u32 utmi_phy_count,
1464 struct utmi_phy_data *cp110_utmi_data)
1465{
1466 u32 i;
1467
1468 debug_enter();
1469 /* UTMI Power down */
1470 for (i = 0; i < utmi_phy_count; i++) {
1471 comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr,
1472 cp110_utmi_data[i].usb_cfg_addr,
1473 cp110_utmi_data[i].utmi_cfg_addr,
1474 cp110_utmi_data[i].utmi_phy_port);
1475 }
1476 /* PLL Power down */
1477 debug("stage: UTMI PHY power down PLL\n");
1478 for (i = 0; i < utmi_phy_count; i++) {
1479 reg_set(cp110_utmi_data[i].usb_cfg_addr,
1480 0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
1481 }
1482 /* UTMI configure */
1483 for (i = 0; i < utmi_phy_count; i++) {
1484 comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr,
1485 cp110_utmi_data[i].usb_cfg_addr,
1486 cp110_utmi_data[i].utmi_cfg_addr,
1487 cp110_utmi_data[i].utmi_phy_port);
1488 }
1489 /* UTMI Power up */
1490 for (i = 0; i < utmi_phy_count; i++) {
1491 if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr,
1492 cp110_utmi_data[i].usb_cfg_addr,
1493 cp110_utmi_data[i].utmi_cfg_addr,
1494 cp110_utmi_data[i].utmi_phy_port)) {
1495 error("Failed to initialize UTMI PHY %d\n", i);
1496 continue;
1497 }
1498 printf("UTMI PHY %d initialized to ", i);
Stefan Roesee89acc42017-04-24 18:45:23 +03001499 if (cp110_utmi_data[i].utmi_phy_port ==
1500 UTMI_PHY_TO_USB3_DEVICE0)
Stefan Roesec0132f62016-08-30 16:48:20 +02001501 printf("USB Device\n");
1502 else
1503 printf("USB Host%d\n",
1504 cp110_utmi_data[i].utmi_phy_port);
1505 }
1506 /* PLL Power up */
1507 debug("stage: UTMI PHY power up PLL\n");
1508 for (i = 0; i < utmi_phy_count; i++) {
1509 reg_set(cp110_utmi_data[i].usb_cfg_addr,
1510 0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
1511 }
1512
1513 debug_exit();
1514 return;
1515}
1516
1517/*
1518 * comphy_dedicated_phys_init initialize the dedicated PHYs
1519 * - not muxed SerDes lanes e.g. UTMI PHY
1520 */
1521void comphy_dedicated_phys_init(void)
1522{
1523 struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
1524 int node;
1525 int i;
1526
1527 debug_enter();
1528 debug("Initialize USB UTMI PHYs\n");
1529
1530 /* Find the UTMI phy node in device tree and go over them */
1531 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
1532 "marvell,mvebu-utmi-2.6.0");
1533
1534 i = 0;
1535 while (node > 0) {
1536 /* get base address of UTMI phy */
1537 cp110_utmi_data[i].utmi_base_addr =
1538 (void __iomem *)fdtdec_get_addr_size_auto_noparent(
1539 gd->fdt_blob, node, "reg", 0, NULL, true);
1540 if (cp110_utmi_data[i].utmi_base_addr == NULL) {
1541 error("UTMI PHY base address is invalid\n");
1542 i++;
1543 continue;
1544 }
1545
1546 /* get usb config address */
1547 cp110_utmi_data[i].usb_cfg_addr =
1548 (void __iomem *)fdtdec_get_addr_size_auto_noparent(
1549 gd->fdt_blob, node, "reg", 1, NULL, true);
1550 if (cp110_utmi_data[i].usb_cfg_addr == NULL) {
1551 error("UTMI PHY base address is invalid\n");
1552 i++;
1553 continue;
1554 }
1555
1556 /* get UTMI config address */
1557 cp110_utmi_data[i].utmi_cfg_addr =
1558 (void __iomem *)fdtdec_get_addr_size_auto_noparent(
1559 gd->fdt_blob, node, "reg", 2, NULL, true);
1560 if (cp110_utmi_data[i].utmi_cfg_addr == NULL) {
1561 error("UTMI PHY base address is invalid\n");
1562 i++;
1563 continue;
1564 }
1565
1566 /*
1567 * get the port number (to check if the utmi connected to
1568 * host/device)
1569 */
1570 cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int(
1571 gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
1572 if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) {
1573 error("UTMI PHY port type is invalid\n");
1574 i++;
1575 continue;
1576 }
1577
1578 node = fdt_node_offset_by_compatible(
1579 gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0");
1580 i++;
1581 }
1582
1583 if (i > 0)
1584 comphy_utmi_phy_init(i, cp110_utmi_data);
1585
1586 debug_exit();
1587}
1588
1589static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
1590 struct comphy_map *serdes_map)
1591{
1592 void __iomem *comphy_base_addr;
1593 struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS];
1594 struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS];
1595 u32 lane, comphy_max_count;
1596
1597 comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
1598 comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
1599
1600 /*
1601 * Copy the SerDes map configuration for PIPE map and PHY map
1602 * the comphy_mux_init modify the type of the lane if the type
1603 * is not valid because we have 2 selectores run the
1604 * comphy_mux_init twice and after that update the original
1605 * serdes_map
1606 */
1607 for (lane = 0; lane < comphy_max_count; lane++) {
1608 comphy_map_pipe_data[lane].type = serdes_map[lane].type;
1609 comphy_map_pipe_data[lane].speed = serdes_map[lane].speed;
1610 comphy_map_phy_data[lane].type = serdes_map[lane].type;
1611 comphy_map_phy_data[lane].speed = serdes_map[lane].speed;
1612 }
1613 ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data;
1614 comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data,
1615 comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET);
1616
1617 ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data;
1618 comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data,
1619 comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET);
1620 /* Fix the type after check the PHY and PIPE configuration */
1621 for (lane = 0; lane < comphy_max_count; lane++) {
1622 if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) &&
1623 (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED))
1624 serdes_map[lane].type = PHY_TYPE_UNCONNECTED;
1625 }
1626}
1627
1628int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
1629 struct comphy_map *serdes_map)
1630{
1631 struct comphy_map *ptr_comphy_map;
1632 void __iomem *comphy_base_addr, *hpipe_base_addr;
1633 u32 comphy_max_count, lane, ret = 0;
1634 u32 pcie_width = 0;
1635
1636 debug_enter();
1637
1638 comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
1639 comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
1640 hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
1641
1642 /* Config Comphy mux configuration */
1643 comphy_mux_cp110_init(ptr_chip_cfg, serdes_map);
1644
1645 /* Check if the first 4 lanes configured as By-4 */
1646 for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
1647 lane++, ptr_comphy_map++) {
1648 if (ptr_comphy_map->type != PHY_TYPE_PEX0)
1649 break;
1650 pcie_width++;
1651 }
1652
1653 for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count;
1654 lane++, ptr_comphy_map++) {
1655 debug("Initialize serdes number %d\n", lane);
1656 debug("Serdes type = 0x%x\n", ptr_comphy_map->type);
1657 if (lane == 4) {
1658 /*
1659 * PCIe lanes above the first 4 lanes, can be only
1660 * by1
1661 */
1662 pcie_width = 1;
1663 }
1664 switch (ptr_comphy_map->type) {
1665 case PHY_TYPE_UNCONNECTED:
Stefan Roese6ecc0b12017-04-24 18:45:24 +03001666 case PHY_TYPE_IGNORE:
Stefan Roesec0132f62016-08-30 16:48:20 +02001667 continue;
1668 break;
1669 case PHY_TYPE_PEX0:
1670 case PHY_TYPE_PEX1:
1671 case PHY_TYPE_PEX2:
1672 case PHY_TYPE_PEX3:
1673 ret = comphy_pcie_power_up(
1674 lane, pcie_width, ptr_comphy_map->clk_src,
Stefan Roese7dda98e2017-04-24 18:45:22 +03001675 serdes_map->end_point,
Stefan Roesec0132f62016-08-30 16:48:20 +02001676 hpipe_base_addr, comphy_base_addr);
1677 break;
1678 case PHY_TYPE_SATA0:
1679 case PHY_TYPE_SATA1:
1680 case PHY_TYPE_SATA2:
1681 case PHY_TYPE_SATA3:
1682 ret = comphy_sata_power_up(
1683 lane, hpipe_base_addr, comphy_base_addr,
1684 ptr_chip_cfg->comphy_index);
1685 break;
1686 case PHY_TYPE_USB3_HOST0:
1687 case PHY_TYPE_USB3_HOST1:
1688 case PHY_TYPE_USB3_DEVICE:
1689 ret = comphy_usb3_power_up(lane, hpipe_base_addr,
1690 comphy_base_addr);
1691 break;
1692 case PHY_TYPE_SGMII0:
1693 case PHY_TYPE_SGMII1:
1694 case PHY_TYPE_SGMII2:
1695 case PHY_TYPE_SGMII3:
1696 if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
1697 debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
1698 lane);
1699 ptr_comphy_map->speed = PHY_SPEED_1_25G;
1700 }
1701 ret = comphy_sgmii_power_up(
1702 lane, ptr_comphy_map->speed, hpipe_base_addr,
1703 comphy_base_addr);
1704 break;
Stefan Roesecb686452017-04-24 18:45:21 +03001705 case PHY_TYPE_SFI:
1706 ret = comphy_sfi_power_up(lane, hpipe_base_addr,
1707 comphy_base_addr);
Stefan Roesec0132f62016-08-30 16:48:20 +02001708 break;
1709 case PHY_TYPE_RXAUI0:
1710 case PHY_TYPE_RXAUI1:
1711 ret = comphy_rxauii_power_up(lane, hpipe_base_addr,
1712 comphy_base_addr);
1713 break;
1714 default:
1715 debug("Unknown SerDes type, skip initialize SerDes %d\n",
1716 lane);
1717 break;
1718 }
1719 if (ret == 0) {
1720 /*
Stefan Roesed37f0202017-04-24 18:45:25 +03001721 * If interface wans't initialized, set the lane to
Stefan Roesec0132f62016-08-30 16:48:20 +02001722 * PHY_TYPE_UNCONNECTED state.
1723 */
1724 ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;
1725 error("PLL is not locked - Failed to initialize lane %d\n",
1726 lane);
1727 }
1728 }
1729
1730 debug_exit();
1731 return 0;
1732}