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Priyanka Jain4909b892018-10-29 09:17:09 +00001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP lx2160a SOC common device tree source
4 *
5 * Copyright 2018 NXP
6 *
7 */
8
Kuldeep Singhe5720642019-11-06 16:38:01 +05309#include <dt-bindings/interrupt-controller/arm-gic.h>
10
Priyanka Jain4909b892018-10-29 09:17:09 +000011/ {
12 compatible = "fsl,lx2160a";
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 memory@80000000 {
18 device_type = "memory";
19 reg = <0x00000000 0x80000000 0 0x80000000>;
20 /* DRAM space - 1, size : 2 GB DRAM */
21 };
22
23 sysclk: sysclk {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <100000000>;
27 clock-output-names = "sysclk";
28 };
29
30 clockgen: clocking@1300000 {
31 compatible = "fsl,ls2080a-clockgen";
32 reg = <0 0x1300000 0 0xa0000>;
33 #clock-cells = <2>;
34 clocks = <&sysclk>;
35 };
36
37 gic: interrupt-controller@6000000 {
38 compatible = "arm,gic-v3";
39 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
40 <0x0 0x06200000 0 0x100000>; /* GICR */
41 #interrupt-cells = <3>;
42 interrupt-controller;
43 interrupts = <1 9 0x4>;
44 };
45
46 timer {
47 compatible = "arm,armv8-timer";
48 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
49 <1 14 0x8>, /* Physical NS PPI, active-low */
50 <1 11 0x8>, /* Virtual PPI, active-low */
51 <1 10 0x8>; /* Hypervisor PPI, active-low */
52 };
53
Kuldeep Singhe5720642019-11-06 16:38:01 +053054 fspi: flexspi@20c0000 {
55 compatible = "nxp,lx2160a-fspi";
56 #address-cells = <1>;
57 #size-cells = <0>;
58 reg = <0x0 0x20c0000 0x0 0x10000>,
59 <0x0 0x20000000 0x0 0x10000000>;
60 reg-names = "fspi_base", "fspi_mmap";
61 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
62 clock-names = "fspi_en", "fspi";
63 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
64 status = "disabled";
65 };
66
Chuanhua Hand1edea22019-07-10 21:00:24 +080067 i2c0: i2c@2000000 {
68 compatible = "fsl,vf610-i2c";
69 #address-cells = <1>;
70 #size-cells = <0>;
71 reg = <0x0 0x2000000 0x0 0x10000>;
72 interrupts = <0 34 4>;
73 scl-gpio = <&gpio2 15 0>;
74 status = "disabled";
75 };
76
77 i2c1: i2c@2010000 {
78 compatible = "fsl,vf610-i2c";
79 #address-cells = <1>;
80 #size-cells = <0>;
81 reg = <0x0 0x2010000 0x0 0x10000>;
82 interrupts = <0 34 4>;
83 status = "disabled";
84 };
85
86 i2c2: i2c@2020000 {
87 compatible = "fsl,vf610-i2c";
88 #address-cells = <1>;
89 #size-cells = <0>;
90 reg = <0x0 0x2020000 0x0 0x10000>;
91 interrupts = <0 35 4>;
92 status = "disabled";
93 };
94
95 i2c3: i2c@2030000 {
96 compatible = "fsl,vf610-i2c";
97 #address-cells = <1>;
98 #size-cells = <0>;
99 reg = <0x0 0x2030000 0x0 0x10000>;
100 interrupts = <0 35 4>;
101 status = "disabled";
102 };
103
104 i2c4: i2c@2040000 {
105 compatible = "fsl,vf610-i2c";
106 #address-cells = <1>;
107 #size-cells = <0>;
108 reg = <0x0 0x2040000 0x0 0x10000>;
109 interrupts = <0 74 4>;
110 scl-gpio = <&gpio2 16 0>;
111 status = "disabled";
112 };
113
114 i2c5: i2c@2050000 {
115 compatible = "fsl,vf610-i2c";
116 #address-cells = <1>;
117 #size-cells = <0>;
118 reg = <0x0 0x2050000 0x0 0x10000>;
119 interrupts = <0 74 4>;
120 status = "disabled";
121 };
122
123 i2c6: i2c@2060000 {
124 compatible = "fsl,vf610-i2c";
125 #address-cells = <1>;
126 #size-cells = <0>;
127 reg = <0x0 0x2060000 0x0 0x10000>;
128 interrupts = <0 75 4>;
129 status = "disabled";
130 };
131
132 i2c7: i2c@2070000 {
133 compatible = "fsl,vf610-i2c";
134 #address-cells = <1>;
135 #size-cells = <0>;
136 reg = <0x0 0x2070000 0x0 0x10000>;
137 interrupts = <0 75 4>;
138 status = "disabled";
139 };
140
Priyanka Jain4909b892018-10-29 09:17:09 +0000141 uart0: serial@21c0000 {
142 compatible = "arm,pl011";
143 reg = <0x0 0x21c0000 0x0 0x1000>;
144 clocks = <&clockgen 4 0>;
Vabhav Sharmac1ead042019-11-26 11:30:51 +0000145 status = "disabled";
Priyanka Jain4909b892018-10-29 09:17:09 +0000146 };
147
148 uart1: serial@21d0000 {
149 compatible = "arm,pl011";
150 reg = <0x0 0x21d0000 0x0 0x1000>;
151 clocks = <&clockgen 4 0>;
Vabhav Sharmac1ead042019-11-26 11:30:51 +0000152 status = "disabled";
Priyanka Jain4909b892018-10-29 09:17:09 +0000153 };
154
155 uart2: serial@21e0000 {
156 compatible = "arm,pl011";
157 reg = <0x0 0x21e0000 0x0 0x1000>;
158 clocks = <&clockgen 4 0>;
159 status = "disabled";
160 };
161
162 uart3: serial@21f0000 {
163 compatible = "arm,pl011";
164 reg = <0x0 0x21f0000 0x0 0x1000>;
165 clocks = <&clockgen 4 0>;
166 status = "disabled";
167 };
168
169 dspi0: dspi@2100000 {
170 compatible = "fsl,vf610-dspi";
171 #address-cells = <1>;
172 #size-cells = <0>;
173 reg = <0x0 0x2100000 0x0 0x10000>;
174 interrupts = <0 26 0x4>; /* Level high type */
175 num-cs = <6>;
176 };
177
178 dspi1: dspi@2110000 {
179 compatible = "fsl,vf610-dspi";
180 #address-cells = <1>;
181 #size-cells = <0>;
182 reg = <0x0 0x2110000 0x0 0x10000>;
Priyanka Jain58c3e622018-11-28 13:04:27 +0000183 interrupts = <0 26 0x4>; /* Level high type */
Priyanka Jain4909b892018-10-29 09:17:09 +0000184 num-cs = <6>;
185 };
186
187 dspi2: dspi@2120000 {
188 compatible = "fsl,vf610-dspi";
189 #address-cells = <1>;
190 #size-cells = <0>;
191 reg = <0x0 0x2120000 0x0 0x10000>;
192 interrupts = <0 241 0x4>; /* Level high type */
193 num-cs = <6>;
194 };
195
Chuanhua Hand1edea22019-07-10 21:00:24 +0800196 gpio2: gpio@2320000 {
197 compatible = "fsl,qoriq-gpio";
198 reg = <0x0 0x2320000 0x0 0x10000>;
199 interrupts = <0 37 4>;
200 gpio-controller;
201 little-endian;
202 #gpio-cells = <2>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
205 };
206
Priyanka Jain4909b892018-10-29 09:17:09 +0000207 usb0: usb3@3100000 {
208 compatible = "fsl,layerscape-dwc3";
209 reg = <0x0 0x3100000 0x0 0x10000>;
210 interrupts = <0 80 0x4>; /* Level high type */
211 dr_mode = "host";
212 };
213
214 usb1: usb3@3110000 {
215 compatible = "fsl,layerscape-dwc3";
216 reg = <0x0 0x3110000 0x0 0x10000>;
217 interrupts = <0 81 0x4>; /* Level high type */
218 dr_mode = "host";
219 };
Priyanka Jain58c3e622018-11-28 13:04:27 +0000220
221 esdhc0: esdhc@2140000 {
222 compatible = "fsl,esdhc";
223 reg = <0x0 0x2140000 0x0 0x10000>;
224 interrupts = <0 28 0x4>; /* Level high type */
225 clocks = <&clockgen 4 1>;
226 voltage-ranges = <1800 1800 3300 3300>;
227 sdhci,auto-cmd12;
228 little-endian;
229 bus-width = <4>;
230 status = "disabled";
231 };
232
233 esdhc1: esdhc@2150000 {
234 compatible = "fsl,esdhc";
235 reg = <0x0 0x2150000 0x0 0x10000>;
236 interrupts = <0 63 0x4>; /* Level high type */
237 clocks = <&clockgen 4 1>;
238 voltage-ranges = <1800 1800 3300 3300>;
239 sdhci,auto-cmd12;
240 non-removable;
241 little-endian;
242 bus-width = <4>;
243 status = "disabled";
244 };
245
246 sata0: sata@3200000 {
247 compatible = "fsl,ls2080a-ahci";
248 reg = <0x0 0x3200000 0x0 0x10000>;
249 interrupts = <0 133 4>;
250 clocks = <&clockgen 4 3>;
251 status = "disabled";
252
253 };
254
255 sata1: sata@3210000 {
256 compatible = "fsl,ls2080a-ahci";
257 reg = <0x0 0x3210000 0x0 0x10000>;
258 interrupts = <0 136 4>;
259 clocks = <&clockgen 4 3>;
260 status = "disabled";
261
262 };
263
264 sata2: sata@3220000 {
265 compatible = "fsl,ls2080a-ahci";
266 reg = <0x0 0x3220000 0x0 0x10000>;
267 interrupts = <0 97 4>;
268 clocks = <&clockgen 4 3>;
269 status = "disabled";
270
271 };
272
273 sata3: sata@3230000 {
274 compatible = "fsl,ls2080a-ahci";
275 reg = <0x0 0x3230000 0x0 0x10000>;
276 interrupts = <0 100 4>;
277 clocks = <&clockgen 4 3>;
278 status = "disabled";
279
280 };
Hou Zhiqianga8d60502019-04-08 10:15:58 +0000281
282 pcie@3400000 {
283 compatible = "fsl,lx2160a-pcie";
284 reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
285 0x00 0x03480000 0x0 0x40000 /* LUT registers */
286 0x00 0x034c0000 0x0 0x40000 /* PF control registers */
287 0x80 0x00000000 0x0 0x1000>; /* configuration space */
288 reg-names = "ccsr", "lut", "pf_ctrl", "config";
289 #address-cells = <3>;
290 #size-cells = <2>;
291 device_type = "pci";
292 bus-range = <0x0 0xff>;
293 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
294 };
295
296 pcie@3500000 {
297 compatible = "fsl,lx2160a-pcie";
298 reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
299 0x00 0x03580000 0x0 0x40000 /* LUT registers */
300 0x00 0x035c0000 0x0 0x40000 /* PF control registers */
301 0x88 0x00000000 0x0 0x1000>; /* configuration space */
302 reg-names = "ccsr", "lut", "pf_ctrl", "config";
303 #address-cells = <3>;
304 #size-cells = <2>;
305 device_type = "pci";
306 num-lanes = <2>;
307 bus-range = <0x0 0xff>;
308 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
309 };
310
311 pcie@3600000 {
312 compatible = "fsl,lx2160a-pcie";
313 reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
314 0x00 0x03680000 0x0 0x40000 /* LUT registers */
315 0x00 0x036c0000 0x0 0x40000 /* PF control registers */
316 0x90 0x00000000 0x0 0x1000>; /* configuration space */
317 reg-names = "ccsr", "lut", "pf_ctrl", "config";
318 #address-cells = <3>;
319 #size-cells = <2>;
320 device_type = "pci";
321 bus-range = <0x0 0xff>;
322 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
323 };
324
325 pcie@3700000 {
326 compatible = "fsl,lx2160a-pcie";
327 reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
328 0x00 0x03780000 0x0 0x40000 /* LUT registers */
329 0x00 0x037c0000 0x0 0x40000 /* PF control registers */
330 0x98 0x00000000 0x0 0x1000>; /* configuration space */
331 reg-names = "ccsr", "lut", "pf_ctrl", "config";
332 #address-cells = <3>;
333 #size-cells = <2>;
334 device_type = "pci";
335 bus-range = <0x0 0xff>;
336 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
337 };
338
339 pcie@3800000 {
340 compatible = "fsl,lx2160a-pcie";
341 reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
342 0x00 0x03880000 0x0 0x40000 /* LUT registers */
343 0x00 0x038c0000 0x0 0x40000 /* PF control registers */
344 0xa0 0x00000000 0x0 0x1000>; /* configuration space */
345 reg-names = "ccsr", "lut", "pf_ctrl", "config";
346 #address-cells = <3>;
347 #size-cells = <2>;
348 device_type = "pci";
349 bus-range = <0x0 0xff>;
350 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
351 };
352
353 pcie@3900000 {
354 compatible = "fsl,lx2160a-pcie";
355 reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
356 0x00 0x03980000 0x0 0x40000 /* LUT registers */
357 0x00 0x039c0000 0x0 0x40000 /* PF control registers */
358 0xa8 0x00000000 0x0 0x1000>; /* configuration space */
359 reg-names = "ccsr", "lut", "pf_ctrl", "config";
360 #address-cells = <3>;
361 #size-cells = <2>;
362 device_type = "pci";
363 bus-range = <0x0 0xff>;
364 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
365 };
Priyanka Jain4909b892018-10-29 09:17:09 +0000366};