blob: 1faa084f94ef84bb50b7f73231cbfcab434f7842 [file] [log] [blame]
wdenk1eaeb582004-06-08 00:22:43 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * Texas Instruments, <www.ti.com>
15 * Rishi Bhattacharya <rishi@ti.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36#include <common.h>
37#if defined(CONFIG_OMAP1610)
38#include <./configs/omap1510.h>
39#endif
40
41void flash__init (void);
42void ether__init (void);
43void set_muxconf_regs (void);
44void peripheral_power_enable (void);
45
46#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
47
48static inline void delay (unsigned long loops)
49{
50 __asm__ volatile ("1:\n"
51 "subs %0, %1, #1\n"
52 "bne 1b":"=r" (loops):"0" (loops));
53}
54
55/*
56 * Miscellaneous platform dependent initialisations
57 */
58
59int board_init (void)
60{
61 DECLARE_GLOBAL_DATA_PTR;
62
wdenk731215e2004-10-10 18:41:04 +000063 gd->bd->bi_arch_number = MACH_TYPE_OMAP_OSK;
wdenk1eaeb582004-06-08 00:22:43 +000064
65 /* adress of boot parameters */
66 gd->bd->bi_boot_params = 0x10000100;
67
68 /* Configure MUX settings */
69 set_muxconf_regs ();
70 peripheral_power_enable ();
71
72/* this speeds up your boot a quite a bit. However to make it
73 * work, you need make sure your kernel startup flush bug is fixed.
74 * ... rkw ...
75 */
76 icache_enable ();
77
78 flash__init ();
79 ether__init ();
80 return 0;
81}
82
83
84int misc_init_r (void)
85{
86 /* currently empty */
87 return (0);
88}
89
90/******************************
91 Routine:
92 Description:
93******************************/
94void flash__init (void)
95{
96#define EMIFS_GlB_Config_REG 0xfffecc0c
97 unsigned int regval;
98 regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
99 /* Turn off write protection for flash devices. */
100 regval = regval | 0x0001;
101 *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
102}
103/*************************************************************
104 Routine:ether__init
105 Description: take the Ethernet controller out of reset and wait
106 for the EEPROM load to complete.
107*************************************************************/
108void ether__init (void)
109{
110#define ETH_CONTROL_REG 0x0480000b
111 int i;
112
113 *((volatile unsigned short *) 0xfffece08) = 0x03FF;
114 *((volatile unsigned short *) 0xfffb3824) = 0x8000;
115 *((volatile unsigned short *) 0xfffb3830) = 0x0000;
116 *((volatile unsigned short *) 0xfffb3834) = 0x0009;
117 *((volatile unsigned short *) 0xfffb3838) = 0x0009;
118 *((volatile unsigned short *) 0xfffb3818) = 0x0002;
119 *((volatile unsigned short *) 0xfffb382C) = 0x0048;
120 *((volatile unsigned short *) 0xfffb3824) = 0x8603;
121 udelay (3);
122 for (i=0;i<2000;i++);
123 *((volatile unsigned short *) 0xfffb381C) = 0x6610;
124 udelay (30);
125 for (i=0;i<10000;i++);
126
127 *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
128 udelay (3);
129
130
131}
132
133/******************************
134 Routine:
135 Description:
136******************************/
137int dram_init (void)
138{
139 DECLARE_GLOBAL_DATA_PTR;
140
141 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
142 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
143
144 return 0;
145}
146
147/******************************************************
148 Routine: set_muxconf_regs
149 Description: Setting up the configuration Mux registers
150 specific to the hardware
151*******************************************************/
152void set_muxconf_regs (void)
153{
154 volatile unsigned int *MuxConfReg;
155 /* set each registers to its reset value; */
156 MuxConfReg =
157 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
158 /* setup for UART1 */
159 *MuxConfReg &= ~(0x02000000); /* bit 25 */
160 /* setup for UART2 */
161 *MuxConfReg &= ~(0x01000000); /* bit 24 */
162 /* Disable Uwire CS Hi-Z */
163 *MuxConfReg |= 0x08000000;
164 MuxConfReg =
165 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3);
166 *MuxConfReg = 0x00000000;
167 MuxConfReg =
168 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4);
169 *MuxConfReg = 0x00000000;
170 MuxConfReg =
171 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5);
172 *MuxConfReg = 0x00000000;
173 MuxConfReg =
174 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6);
175 /*setup mux for UART3 */
176 *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */
177 *MuxConfReg &= ~0x0000003e;
178 MuxConfReg =
179 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7);
180 *MuxConfReg = 0x00000000;
181 MuxConfReg =
182 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8);
183 /* Disable Uwire CS Hi-Z */
184 *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */
185 MuxConfReg =
186 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9);
187 /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */
188 /* hardware will actually use TX and RTS based on bit 25 in */
189 /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */
190 *MuxConfReg |= 0x00201000;
191 MuxConfReg =
192 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A);
193 *MuxConfReg = 0x00000000;
194 MuxConfReg =
195 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B);
196 *MuxConfReg = 0x00000000;
197 MuxConfReg =
198 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C);
199 /* setup for UART2 */
200 /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */
201 /* hardware will actually use TX and RTS based on bit 24 in */
202 /* FUNC_MUX_CTRL_0. */
203 *MuxConfReg |= 0x09000000;
204 MuxConfReg =
205 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_D);
206 *MuxConfReg |= 0x00000020;
207 MuxConfReg =
208 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0);
209 *MuxConfReg = 0x00000000;
210 MuxConfReg =
211 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1);
212 *MuxConfReg = 0x00000000;
213 /* mux setup for SD/MMC driver */
214 MuxConfReg =
215 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2);
216 *MuxConfReg &= 0xFFFE0FFF;
217 MuxConfReg =
218 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3);
219 *MuxConfReg = 0x00000000;
220 MuxConfReg =
221 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
222 /* bit 13 for MMC2 XOR_CLK */
223 *MuxConfReg &= ~(0x00002000);
224 /* bit 29 for UART 1 */
225 *MuxConfReg &= ~(0x00002000);
226 MuxConfReg =
227 (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0);
228 /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */
229 *MuxConfReg |= 0x000C0000;
230 MuxConfReg =
231 (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL);
232 *MuxConfReg &= ~(0x00000070);
233 *MuxConfReg &= ~(0x00000008);
234 *MuxConfReg |= 0x00000003;
235 *MuxConfReg |= 0x00000180;
236 MuxConfReg =
237 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
238 /* bit 17, software controls VBUS */
239 *MuxConfReg &= ~(0x00020000);
240 /* Enable USB 48 and 12M clocks */
241 *MuxConfReg |= 0x00000200;
242 *MuxConfReg &= ~(0x00000180);
243 /*2.75V for MMCSDIO1 */
244 MuxConfReg =
245 (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0);
246 *MuxConfReg = 0x00001FE7;
247 MuxConfReg =
248 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0);
249 *MuxConfReg = 0x00000000;
250 MuxConfReg =
251 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1);
252 *MuxConfReg = 0x00000000;
253 MuxConfReg =
254 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
255 *MuxConfReg = 0x00000000;
256 MuxConfReg =
257 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3);
258 *MuxConfReg = 0x00000000;
259 MuxConfReg =
260 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4);
261 *MuxConfReg = 0x00000000;
262 MuxConfReg =
263 (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4);
264 *MuxConfReg = 0x00000000;
265 /* Turn on UART2 48 MHZ clock */
266 MuxConfReg =
267 (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0);
268 *MuxConfReg |= 0x40000000;
269 MuxConfReg =
270 (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL);
271 /* setup for USB VBus detection OMAP161x */
272 *MuxConfReg |= 0x00040000; /* bit 18 */
273 MuxConfReg =
274 (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2);
275 /* PullUps for SD/MMC driver */
276 *MuxConfReg |= ~(0xFFFE0FFF);
277 MuxConfReg =
278 (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0);
279 *MuxConfReg = COMP_MODE_ENABLE;
280}
281
282/******************************************************
283 Routine: peripheral_power_enable
284 Description: Enable the power for UART1
285*******************************************************/
286void peripheral_power_enable (void)
287{
288#define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
289#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834)
290
291 *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
292}